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(parent: 5848299) | patch
[ramips] uart_clk on Rt3352F is always 40MHz
authorJohn Crispin <john@openwrt.org>
Tue, 24 Jul 2012 20:37:50 +0000 (20:37 +0000)
committerJohn Crispin <john@openwrt.org>
Tue, 24 Jul 2012 20:37:50 +0000 (20:37 +0000)
commit466f939f6ea0e154cb707dd7ceeb8d00efc70050
tree0c5f16afaac5b361c18502777986bb81167f234etree | snapshot
parent5848299ba15a99061bf7ca2c8cbc9a96a589dfc4commit | diff
[ramips] uart_clk on Rt3352F is always 40MHz

Currently, sys_clk/10 is used which is just wrong.
cpu_clk/10 would work for systems with 400MHz CPU clock.

Signed-off-by: Daniel Golle <dgolle@allnet.de>
SVN-Revision: 32812
target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c diff | blob | history
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