ar71xx: rework patch for qca953x/956x

Patch cherry-picked from the following location:
https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h=release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c0e

Changelist,
    - add more register defines
    - add EHCI support
    - fix GPIO pin count to 18
    - fix chained irq disabled
    - fix GMAC0/GMAC1 initial
    - fix WMAC irq number to 47
    - merge the changes of dev-eth.c from the patch to file.

Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
SVN-Revision: 46207

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index ae3db4c3ef9ff35aee63cc9e15295cbbf2dc9875..ff94e2ec3733b9473c4c3191cb47bd4ba8ac784d 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -198,6 +198,8 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
        case ATH79_SOC_AR9330:
        case ATH79_SOC_AR9331:
        case ATH79_SOC_QCA9533:
        case ATH79_SOC_AR9330:
        case ATH79_SOC_AR9331:
        case ATH79_SOC_QCA9533:

+       case ATH79_SOC_QCA9561:
+       case ATH79_SOC_TP9343:

                mdio_dev = &ath79_mdio1_device;
                mdio_data = &ath79_mdio1_data;
                break;
                mdio_dev = &ath79_mdio1_device;
                mdio_data = &ath79_mdio1_data;
                break;


@@ -256,6 +258,8 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
                break;
 
        case ATH79_SOC_QCA9533:
                break;
 
        case ATH79_SOC_QCA9533:

+       case ATH79_SOC_QCA9561:
+       case ATH79_SOC_TP9343:

                mdio_data->builtin_switch = 1;
                break;
 
                mdio_data->builtin_switch = 1;
                break;
 


@@ -571,6 +575,8 @@ static void __init ath79_init_eth_pll_data(unsigned int id)
        case ATH79_SOC_QCA9533:
        case ATH79_SOC_QCA9556:
        case ATH79_SOC_QCA9558:
        case ATH79_SOC_QCA9533:
        case ATH79_SOC_QCA9556:
        case ATH79_SOC_QCA9558:

+       case ATH79_SOC_QCA9561:
+       case ATH79_SOC_TP9343:

                pll_10 = AR934X_PLL_VAL_10;
                pll_100 = AR934X_PLL_VAL_100;
                pll_1000 = AR934X_PLL_VAL_1000;
                pll_10 = AR934X_PLL_VAL_10;
                pll_100 = AR934X_PLL_VAL_100;
                pll_1000 = AR934X_PLL_VAL_1000;


@@ -627,6 +633,8 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
                case ATH79_SOC_AR9330:
                case ATH79_SOC_AR9331:
                case ATH79_SOC_QCA9533:
                case ATH79_SOC_AR9330:
                case ATH79_SOC_AR9331:
                case ATH79_SOC_QCA9533:

+               case ATH79_SOC_QCA9561:
+               case ATH79_SOC_TP9343:

                        pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
                        break;
 
                        pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
                        break;
 


@@ -687,7 +695,8 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
                case ATH79_SOC_AR7241:
                case ATH79_SOC_AR9330:
                case ATH79_SOC_AR9331:
                case ATH79_SOC_AR7241:
                case ATH79_SOC_AR9330:
                case ATH79_SOC_AR9331:

-               case ATH79_SOC_QCA9533:
+               case ATH79_SOC_QCA9561:
+               case ATH79_SOC_TP9343:

                        pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
                        break;
 
                        pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
                        break;
 


@@ -697,6 +706,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
                case ATH79_SOC_AR9341:
                case ATH79_SOC_AR9342:
                case ATH79_SOC_AR9344:
                case ATH79_SOC_AR9341:
                case ATH79_SOC_AR9342:
                case ATH79_SOC_AR9344:

+               case ATH79_SOC_QCA9533:

                        switch (pdata->phy_if_mode) {
                        case PHY_INTERFACE_MODE_MII:
                        case PHY_INTERFACE_MODE_GMII:
                        switch (pdata->phy_if_mode) {
                        case PHY_INTERFACE_MODE_MII:
                        case PHY_INTERFACE_MODE_GMII:


@@ -986,6 +996,7 @@ void __init ath79_register_eth(unsigned int id)
        case ATH79_SOC_AR9341:
        case ATH79_SOC_AR9342:
        case ATH79_SOC_AR9344:
        case ATH79_SOC_AR9341:
        case ATH79_SOC_AR9342:
        case ATH79_SOC_AR9344:

+       case ATH79_SOC_QCA9533:

                if (id == 0) {
                        pdata->reset_bit = AR934X_RESET_GE0_MAC |
                                           AR934X_RESET_GE0_MDIO;
                if (id == 0) {
                        pdata->reset_bit = AR934X_RESET_GE0_MAC |
                                           AR934X_RESET_GE0_MDIO;


@@ -1017,7 +1028,8 @@ void __init ath79_register_eth(unsigned int id)
                        pdata->fifo_cfg3 = 0x01f00140;
                break;
 
                        pdata->fifo_cfg3 = 0x01f00140;
                break;
 

-       case ATH79_SOC_QCA9533:
+       case ATH79_SOC_QCA9561:
+       case ATH79_SOC_TP9343:

                if (id == 0) {
                        pdata->reset_bit = AR933X_RESET_GE0_MAC |
                                           AR933X_RESET_GE0_MDIO;
                if (id == 0) {
                        pdata->reset_bit = AR933X_RESET_GE0_MAC |
                                           AR933X_RESET_GE0_MDIO;


@@ -1123,6 +1135,8 @@ void __init ath79_register_eth(unsigned int id)
                case ATH79_SOC_AR9330:
                case ATH79_SOC_AR9331:
                case ATH79_SOC_QCA9533:
                case ATH79_SOC_AR9330:
                case ATH79_SOC_AR9331:
                case ATH79_SOC_QCA9533:

+               case ATH79_SOC_QCA9561:
+               case ATH79_SOC_TP9343:

                        pdata->mii_bus_dev = &ath79_mdio1_device.dev;
                        break;
 
                        pdata->mii_bus_dev = &ath79_mdio1_device.dev;
                        break;
 

diff --git a/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
index 4f5d20314fb3756f643d8e2b2632d2f5d58e6c88..be4f547529f0aa5702e92e9b5317323efc527d06 100644 (file)
--- a/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+++ b/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
@@ -44,7 +44,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  config ATH79_NVRAM
 --- a/arch/mips/ath79/clock.c
 +++ b/arch/mips/ath79/clock.c
  config ATH79_NVRAM
 --- a/arch/mips/ath79/clock.c
 +++ b/arch/mips/ath79/clock.c

-@@ -350,6 +350,91 @@ static void __init ar934x_clocks_init(vo
+@@ -350,6 +350,91 @@ static void __init ar934x_clocks_init(void)

        iounmap(dpll_base);
  }
  
        iounmap(dpll_base);
  }
  


@@ -175,6 +175,48 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
            soc_is_qca955x()) {
                ath79_uart_data[0].uartclk = uart_clk_rate;
                platform_device_register(&ath79_uart_device);
            soc_is_qca955x()) {
                ath79_uart_data[0].uartclk = uart_clk_rate;
                platform_device_register(&ath79_uart_device);

+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void)
+                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
+ 
++static void __init qca953x_usb_setup(void)
++{
++      u32 bootstrap;
++
++      bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
++
++      ath79_device_reset_set(QCA953X_RESET_USBSUS_OVERRIDE);
++      udelay(1000);
++
++      ath79_device_reset_clear(QCA953X_RESET_USB_PHY);
++      udelay(1000);
++
++      ath79_device_reset_clear(QCA953X_RESET_USB_PHY_ANALOG);
++      udelay(1000);
++
++      ath79_device_reset_clear(QCA953X_RESET_USB_HOST);
++      udelay(1000);
++
++      ath79_usb_register("ehci-platform", -1,
++                         QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE,
++                         ATH79_CPU_IRQ(3),
++                         &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
++}
++
+ static void qca955x_usb_reset_notifier(struct platform_device *pdev)
+ {
+       u32 base;
+@@ -286,6 +310,8 @@ void __init ath79_register_usb(void)
+               ar933x_usb_setup();
+       else if (soc_is_ar934x())
+               ar934x_usb_setup();
++      else if (soc_is_qca953x())
++              qca953x_usb_setup();
+       else if (soc_is_qca955x())
+               qca955x_usb_setup();
+       else

 --- a/arch/mips/ath79/dev-wmac.c
 +++ b/arch/mips/ath79/dev-wmac.c
 @@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void)
 --- a/arch/mips/ath79/dev-wmac.c
 +++ b/arch/mips/ath79/dev-wmac.c
 @@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void)


@@ -186,7 +228,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  {
        return ath79_soc_rev;
  }
  {
        return ath79_soc_rev;
  }

-@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi
+@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(void)

                ath79_wmac_data.is_clk_25mhz = true;
  
        if (ath79_soc_rev == 1)
                ath79_wmac_data.is_clk_25mhz = true;
  
        if (ath79_soc_rev == 1)


@@ -195,8 +237,8 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  
        ath79_wmac_data.external_reset = ar933x_wmac_reset;
  }
  
        ath79_wmac_data.external_reset = ar933x_wmac_reset;
  }

-@@ -149,6 +149,26 @@ static void ar934x_wmac_setup(void)
-               ath79_wmac_data.is_clk_25mhz = true;
+@@ -151,6 +151,26 @@ static void ar934x_wmac_setup(void)
+       ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;

  }
  
 +static void qca953x_wmac_setup(void)
  }
  
 +static void qca953x_wmac_setup(void)


@@ -207,8 +249,8 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
 +
 +      ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
 +      ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
 +
 +      ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
 +      ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;

-+      ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
-+      ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
++      ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
++      ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);

 +
 +      t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
 +      if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
 +
 +      t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
 +      if (t & QCA953X_BOOTSTRAP_REF_CLK_40)


@@ -222,7 +264,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  static void qca955x_wmac_setup(void)
  {
        u32 t;
  static void qca955x_wmac_setup(void)
  {
        u32 t;

-@@ -366,6 +386,8 @@ void __init ath79_register_wmac(u8 *cal_
+@@ -368,6 +388,8 @@ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)

                ar933x_wmac_setup();
        else if (soc_is_ar934x())
                ar934x_wmac_setup();
                ar933x_wmac_setup();
        else if (soc_is_ar934x())
                ar934x_wmac_setup();


@@ -244,6 +286,24 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
                _prom_putchar = prom_putchar_ar71xx;
 --- a/arch/mips/ath79/gpio.c
 +++ b/arch/mips/ath79/gpio.c
                _prom_putchar = prom_putchar_ar71xx;
 --- a/arch/mips/ath79/gpio.c
 +++ b/arch/mips/ath79/gpio.c

+@@ -148,7 +148,7 @@ static void __iomem *ath79_gpio_get_function_reg(void)
+           soc_is_ar913x() ||
+           soc_is_ar933x())
+               reg = AR71XX_GPIO_REG_FUNC;
+-      else if (soc_is_ar934x())
++      else if (soc_is_ar934x() || soc_is_qca953x())
+               reg = AR934X_GPIO_REG_FUNC;
+       else
+               BUG();
+@@ -187,7 +187,7 @@ void __init ath79_gpio_output_select(unsigned gpio, u8 val)
+       unsigned int reg;
+       u32 t, s;
+ 
+-      BUG_ON(!soc_is_ar934x());
++      BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
+ 
+       if (gpio >= AR934X_GPIO_COUNT)
+               return;

 @@ -224,6 +224,8 @@ void __init ath79_gpio_init(void)
                ath79_gpio_count = AR933X_GPIO_COUNT;
        else if (soc_is_ar934x())
 @@ -224,6 +224,8 @@ void __init ath79_gpio_init(void)
                ath79_gpio_count = AR933X_GPIO_COUNT;
        else if (soc_is_ar934x())


@@ -264,7 +324,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
        }
 --- a/arch/mips/ath79/irq.c
 +++ b/arch/mips/ath79/irq.c
        }
 --- a/arch/mips/ath79/irq.c
 +++ b/arch/mips/ath79/irq.c

-@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v
+@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(void)

        else if (soc_is_ar724x() ||
                 soc_is_ar933x() ||
                 soc_is_ar934x() ||
        else if (soc_is_ar724x() ||
                 soc_is_ar933x() ||
                 soc_is_ar934x() ||


@@ -272,19 +332,80 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
                 soc_is_qca955x())
                ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
        else
                 soc_is_qca955x())
                ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
        else

-@@ -352,6 +353,9 @@ void __init arch_init_irq(void)
+@@ -153,6 +154,38 @@ static void ar934x_ip2_irq_init(void)
+       irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
+ }
+ 
++static void qca953x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
++{
++      u32 status;
++
++      disable_irq_nosync(irq);
++
++      status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
++
++      if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
++              ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_PCIE);
++              generic_handle_irq(ATH79_IP2_IRQ(0));
++      } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
++              ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_WMAC);
++              generic_handle_irq(ATH79_IP2_IRQ(1));
++      } else {
++              spurious_interrupt();
++      }
++
++      enable_irq(irq);
++}
++
++static void qca953x_irq_init(void)
++{
++      int i;
++
++      for (i = ATH79_IP2_IRQ_BASE;
++           i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
++              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
++
++      irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
++}
++
+ static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
+ {
+       u32 status;
+@@ -335,6 +368,12 @@ static void ar934x_ip3_handler(void)
+       do_IRQ(ATH79_CPU_IRQ(3));
+ }
+ 
++static void qca953x_ip3_handler(void)
++{
++      ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_USB);
++      do_IRQ(ATH79_CPU_IRQ(3));
++}
++
+ void __init arch_init_irq(void)
+ {
+       if (soc_is_ar71xx()) {
+@@ -352,6 +391,9 @@ void __init arch_init_irq(void)

        } else if (soc_is_ar934x()) {
                ath79_ip2_handler = ath79_default_ip2_handler;
                ath79_ip3_handler = ar934x_ip3_handler;
 +      } else if (soc_is_qca953x()) {
 +              ath79_ip2_handler = ath79_default_ip2_handler;
        } else if (soc_is_ar934x()) {
                ath79_ip2_handler = ath79_default_ip2_handler;
                ath79_ip3_handler = ar934x_ip3_handler;
 +      } else if (soc_is_qca953x()) {
 +              ath79_ip2_handler = ath79_default_ip2_handler;

-+              ath79_ip3_handler = ath79_default_ip3_handler;
++              ath79_ip3_handler = qca953x_ip3_handler;

        } else if (soc_is_qca955x()) {
                ath79_ip2_handler = ath79_default_ip2_handler;
                ath79_ip3_handler = ath79_default_ip3_handler;
        } else if (soc_is_qca955x()) {
                ath79_ip2_handler = ath79_default_ip2_handler;
                ath79_ip3_handler = ath79_default_ip3_handler;

+@@ -365,6 +407,8 @@ void __init arch_init_irq(void)
+ 
+       if (soc_is_ar934x())
+               ar934x_ip2_irq_init();
++      else if (soc_is_qca953x())
++              qca953x_irq_init();
+       else if (soc_is_qca955x())
+               qca955x_irq_init();
+ }

 --- a/arch/mips/ath79/setup.c
 +++ b/arch/mips/ath79/setup.c
 --- a/arch/mips/ath79/setup.c
 +++ b/arch/mips/ath79/setup.c

-@@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
+@@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type(void)

        u32 major;
        u32 minor;
        u32 rev = 0;
        u32 major;
        u32 minor;
        u32 rev = 0;


@@ -292,7 +413,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  
        id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
        major = id & REV_ID_MAJOR_MASK;
  
        id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
        major = id & REV_ID_MAJOR_MASK;

-@@ -151,6 +152,16 @@ static void __init ath79_detect_sys_type
+@@ -152,6 +153,16 @@ static void __init ath79_detect_sys_type(void)

                rev = id & AR934X_REV_ID_REVISION_MASK;
                break;
  
                rev = id & AR934X_REV_ID_REVISION_MASK;
                break;
  


@@ -309,38 +430,60 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
        case REV_ID_MAJOR_QCA9556:
                ath79_soc = ATH79_SOC_QCA9556;
                chip = "9556";
        case REV_ID_MAJOR_QCA9556:
                ath79_soc = ATH79_SOC_QCA9556;
                chip = "9556";

-@@ -169,9 +180,9 @@ static void __init ath79_detect_sys_type
+@@ -170,7 +181,7 @@ static void __init ath79_detect_sys_type(void)

  
        ath79_soc_rev = rev;
  
 -      if (soc_is_qca955x())
  
        ath79_soc_rev = rev;
  
 -      if (soc_is_qca955x())

--              sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
--                      chip, rev);

 +      if (soc_is_qca953x() || soc_is_qca955x())
 +      if (soc_is_qca953x() || soc_is_qca955x())

-+              sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
-+                      chip, ver, rev);
+               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
+                       chip, rev);

        else
        else

-               sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
-       pr_info("SoC: %s\n", ath79_sys_type);

 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h

-@@ -105,6 +105,9 @@
+@@ -105,6 +105,21 @@

  #define AR934X_SRIF_BASE      (AR71XX_APB_BASE + 0x00116000)
  #define AR934X_SRIF_SIZE      0x1000
  
  #define AR934X_SRIF_BASE      (AR71XX_APB_BASE + 0x00116000)
  #define AR934X_SRIF_SIZE      0x1000
  

++#define QCA953X_GMAC_BASE     (AR71XX_APB_BASE + 0x00070000)
++#define QCA953X_GMAC_SIZE     0x14

 +#define QCA953X_WMAC_BASE     (AR71XX_APB_BASE + 0x00100000)
 +#define QCA953X_WMAC_SIZE     0x20000
 +#define QCA953X_WMAC_BASE     (AR71XX_APB_BASE + 0x00100000)
 +#define QCA953X_WMAC_SIZE     0x20000

++#define QCA953X_EHCI_BASE     0x1b000000
++#define QCA953X_EHCI_SIZE     0x200
++#define QCA953X_SRIF_BASE     (AR71XX_APB_BASE + 0x00116000)
++#define QCA953X_SRIF_SIZE     0x1000
++
++#define QCA953X_PCI_CFG_BASE0 0x14000000
++#define QCA953X_PCI_CTRL_BASE0        (AR71XX_APB_BASE + 0x000f0000)
++#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
++#define QCA953X_PCI_MEM_BASE0 0x10000000
++#define QCA953X_PCI_MEM_SIZE  0x02000000

 +
  #define QCA955X_PCI_MEM_BASE0 0x10000000
  #define QCA955X_PCI_MEM_BASE1 0x12000000
  #define QCA955X_PCI_MEM_SIZE  0x02000000
 +
  #define QCA955X_PCI_MEM_BASE0 0x10000000
  #define QCA955X_PCI_MEM_BASE1 0x12000000
  #define QCA955X_PCI_MEM_SIZE  0x02000000

-@@ -279,6 +282,43 @@
+@@ -173,6 +188,12 @@
+ #define AR934X_DDR_REG_FLUSH_PCIE     0xa8
+ #define AR934X_DDR_REG_FLUSH_WMAC     0xac
+ 
++#define QCA953X_DDR_REG_FLUSH_GE0     0x9c
++#define QCA953X_DDR_REG_FLUSH_GE1     0xa0
++#define QCA953X_DDR_REG_FLUSH_USB     0xa4
++#define QCA953X_DDR_REG_FLUSH_PCIE    0xa8
++#define QCA953X_DDR_REG_FLUSH_WMAC    0xac
++
+ /*
+  * PLL block
+  */
+@@ -279,6 +300,44 @@

  
  #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL  BIT(6)
  
 +#define QCA953X_PLL_CPU_CONFIG_REG            0x00
 +#define QCA953X_PLL_DDR_CONFIG_REG            0x04
 +#define QCA953X_PLL_CLK_CTRL_REG              0x08
  
  #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL  BIT(6)
  
 +#define QCA953X_PLL_CPU_CONFIG_REG            0x00
 +#define QCA953X_PLL_DDR_CONFIG_REG            0x04
 +#define QCA953X_PLL_CLK_CTRL_REG              0x08

++#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG  0x24

 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG      0x2c
 +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG     0x48
 +
 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG      0x2c
 +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG     0x48
 +


@@ -351,7 +494,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT   12
 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK    0x1f
 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT   19
 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT   12
 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK    0x1f
 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT   19

-+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK    0x3
++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK    0x7

 +
 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT    0
 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK     0x3ff
 +
 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT    0
 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK     0x3ff


@@ -378,27 +521,85 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_PLL_CPU_CONFIG_REG            0x00
  #define QCA955X_PLL_DDR_CONFIG_REG            0x04
  #define QCA955X_PLL_CLK_CTRL_REG              0x08
  #define QCA955X_PLL_CPU_CONFIG_REG            0x00
  #define QCA955X_PLL_DDR_CONFIG_REG            0x04
  #define QCA955X_PLL_CLK_CTRL_REG              0x08

-@@ -355,6 +395,10 @@
+@@ -355,6 +414,10 @@

  #define AR934X_RESET_REG_BOOTSTRAP            0xb0
  #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
  
 +#define QCA953X_RESET_REG_RESET_MODULE                0x1c
 +#define QCA953X_RESET_REG_BOOTSTRAP           0xb0
  #define AR934X_RESET_REG_BOOTSTRAP            0xb0
  #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
  
 +#define QCA953X_RESET_REG_RESET_MODULE                0x1c
 +#define QCA953X_RESET_REG_BOOTSTRAP           0xb0

-+#define QCA953X_RESET_REG_EXT_INT_STATUS      0xac
++#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS        0xac

 +
  #define QCA955X_RESET_REG_RESET_MODULE                0x1c
  #define QCA955X_RESET_REG_BOOTSTRAP           0xb0
  #define QCA955X_RESET_REG_EXT_INT_STATUS      0xac
 +
  #define QCA955X_RESET_REG_RESET_MODULE                0x1c
  #define QCA955X_RESET_REG_BOOTSTRAP           0xb0
  #define QCA955X_RESET_REG_EXT_INT_STATUS      0xac

-@@ -503,6 +547,8 @@
+@@ -450,6 +513,27 @@
+ #define AR934X_RESET_MBOX             BIT(1)
+ #define AR934X_RESET_I2S              BIT(0)
+ 
++#define QCA953X_RESET_USB_EXT_PWR     BIT(29)
++#define QCA953X_RESET_EXTERNAL                BIT(28)
++#define QCA953X_RESET_RTC             BIT(27)
++#define QCA953X_RESET_FULL_CHIP               BIT(24)
++#define QCA953X_RESET_GE1_MDIO                BIT(23)
++#define QCA953X_RESET_GE0_MDIO                BIT(22)
++#define QCA953X_RESET_CPU_NMI         BIT(21)
++#define QCA953X_RESET_CPU_COLD                BIT(20)
++#define QCA953X_RESET_DDR             BIT(16)
++#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
++#define QCA953X_RESET_GE1_MAC         BIT(13)
++#define QCA953X_RESET_ETH_SWITCH_ANALOG       BIT(12)
++#define QCA953X_RESET_USB_PHY_ANALOG  BIT(11)
++#define QCA953X_RESET_GE0_MAC         BIT(9)
++#define QCA953X_RESET_ETH_SWITCH      BIT(8)
++#define QCA953X_RESET_PCIE_PHY                BIT(7)
++#define QCA953X_RESET_PCIE            BIT(6)
++#define QCA953X_RESET_USB_HOST                BIT(5)
++#define QCA953X_RESET_USB_PHY         BIT(4)
++#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
++
+ #define QCA955X_RESET_HOST            BIT(31)
+ #define QCA955X_RESET_SLIC            BIT(30)
+ #define QCA955X_RESET_HDMA            BIT(29)
+@@ -503,6 +587,13 @@

  #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
  #define AR934X_BOOTSTRAP_DDR1         BIT(0)
  
  #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
  #define AR934X_BOOTSTRAP_DDR1         BIT(0)
  

++#define QCA953X_BOOTSTRAP_SW_OPTION2  BIT(12)
++#define QCA953X_BOOTSTRAP_SW_OPTION1  BIT(11)
++#define QCA953X_BOOTSTRAP_EJTAG_MODE  BIT(5)

 +#define QCA953X_BOOTSTRAP_REF_CLK_40  BIT(4)
 +#define QCA953X_BOOTSTRAP_REF_CLK_40  BIT(4)

++#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
++#define QCA953X_BOOTSTRAP_DDR1                BIT(0)

 +
  #define QCA955X_BOOTSTRAP_REF_CLK_40  BIT(4)
  
  #define AR934X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)
 +
  #define QCA955X_BOOTSTRAP_REF_CLK_40  BIT(4)
  
  #define AR934X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)

-@@ -565,6 +611,8 @@
+@@ -523,6 +614,24 @@
+        AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+        AR934X_PCIE_WMAC_INT_PCIE_RC3)
+ 
++#define QCA953X_PCIE_WMAC_INT_WMAC_MISC               BIT(0)
++#define QCA953X_PCIE_WMAC_INT_WMAC_TX         BIT(1)
++#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP               BIT(2)
++#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP               BIT(3)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC         BIT(4)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC0                BIT(5)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC1                BIT(6)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC2                BIT(7)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC3                BIT(8)
++#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
++      (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
++       QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
++
++#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
++      (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
++       QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
++       QCA953X_PCIE_WMAC_INT_PCIE_RC3)
++
+ #define QCA955X_EXT_INT_WMAC_MISC             BIT(0)
+ #define QCA955X_EXT_INT_WMAC_TX                       BIT(1)
+ #define QCA955X_EXT_INT_WMAC_RXLP             BIT(2)
+@@ -565,6 +674,8 @@

  #define REV_ID_MAJOR_AR9341           0x0120
  #define REV_ID_MAJOR_AR9342           0x1120
  #define REV_ID_MAJOR_AR9344           0x2120
  #define REV_ID_MAJOR_AR9341           0x0120
  #define REV_ID_MAJOR_AR9342           0x1120
  #define REV_ID_MAJOR_AR9344           0x2120


@@ -407,7 +608,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define REV_ID_MAJOR_QCA9556          0x0130
  #define REV_ID_MAJOR_QCA9558          0x1130
  
  #define REV_ID_MAJOR_QCA9556          0x0130
  #define REV_ID_MAJOR_QCA9558          0x1130
  

-@@ -587,6 +635,8 @@
+@@ -587,6 +698,8 @@

  
  #define AR934X_REV_ID_REVISION_MASK   0xf
  
  
  #define AR934X_REV_ID_REVISION_MASK   0xf
  


@@ -416,14 +617,81 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_REV_ID_REVISION_MASK  0xf
  
  /*
  #define QCA955X_REV_ID_REVISION_MASK  0xf
  
  /*

-@@ -640,6 +690,7 @@
+@@ -634,12 +747,32 @@
+ #define AR934X_GPIO_REG_OUT_FUNC5     0x40
+ #define AR934X_GPIO_REG_FUNC          0x6c
+ 
++#define QCA953X_GPIO_REG_OUT_FUNC0    0x2c
++#define QCA953X_GPIO_REG_OUT_FUNC1    0x30
++#define QCA953X_GPIO_REG_OUT_FUNC2    0x34
++#define QCA953X_GPIO_REG_OUT_FUNC3    0x38
++#define QCA953X_GPIO_REG_OUT_FUNC4    0x3c
++#define QCA953X_GPIO_REG_IN_ENABLE0   0x44
++#define QCA953X_GPIO_REG_FUNC         0x6c
++
++#define QCA953X_GPIO_OUT_MUX_SPI_CS1          10
++#define QCA953X_GPIO_OUT_MUX_SPI_CS2          11
++#define QCA953X_GPIO_OUT_MUX_SPI_CS0          9
++#define QCA953X_GPIO_OUT_MUX_SPI_CLK          8
++#define QCA953X_GPIO_OUT_MUX_SPI_MOSI         12
++#define QCA953X_GPIO_OUT_MUX_LED_LINK1                41
++#define QCA953X_GPIO_OUT_MUX_LED_LINK2                42
++#define QCA953X_GPIO_OUT_MUX_LED_LINK3                43
++#define QCA953X_GPIO_OUT_MUX_LED_LINK4                44
++#define QCA953X_GPIO_OUT_MUX_LED_LINK5                45
++
+ #define AR71XX_GPIO_COUNT             16
+ #define AR7240_GPIO_COUNT             18
+ #define AR7241_GPIO_COUNT             20

  #define AR913X_GPIO_COUNT             22
  #define AR933X_GPIO_COUNT             30
  #define AR934X_GPIO_COUNT             23
  #define AR913X_GPIO_COUNT             22
  #define AR933X_GPIO_COUNT             30
  #define AR934X_GPIO_COUNT             23

-+#define QCA953X_GPIO_COUNT            24
++#define QCA953X_GPIO_COUNT            18

  #define QCA955X_GPIO_COUNT            24
  
  /*
  #define QCA955X_GPIO_COUNT            24
  
  /*

+@@ -663,6 +796,24 @@
+ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
+ #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
+ 
++#define QCA953X_SRIF_CPU_DPLL1_REG    0x1c0
++#define QCA953X_SRIF_CPU_DPLL2_REG    0x1c4
++#define QCA953X_SRIF_CPU_DPLL3_REG    0x1c8
++
++#define QCA953X_SRIF_DDR_DPLL1_REG    0x240
++#define QCA953X_SRIF_DDR_DPLL2_REG    0x244
++#define QCA953X_SRIF_DDR_DPLL3_REG    0x248
++
++#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT       27
++#define QCA953X_SRIF_DPLL1_REFDIV_MASK        0x1f
++#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
++#define QCA953X_SRIF_DPLL1_NINT_MASK  0x1ff
++#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
++
++#define QCA953X_SRIF_DPLL2_LOCAL_PLL  BIT(30)
++#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT       13
++#define QCA953X_SRIF_DPLL2_OUTDIV_MASK        0x7
++
+ #define AR71XX_GPIO_FUNC_STEREO_EN            BIT(17)
+ #define AR71XX_GPIO_FUNC_SLIC_EN              BIT(16)
+ #define AR71XX_GPIO_FUNC_SPI_CS2_EN           BIT(13)
+@@ -804,6 +955,16 @@
+ #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
+ 
+ /*
++ * QCA953X GMAC Interface
++ */
++#define QCA953X_GMAC_REG_ETH_CFG              0x00
++
++#define QCA953X_ETH_CFG_SW_ONLY_MODE          BIT(6)
++#define QCA953X_ETH_CFG_SW_PHY_SWAP           BIT(7)
++#define QCA953X_ETH_CFG_SW_APB_ACCESS         BIT(9)
++#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST      BIT(13)
++
++/*
+  * QCA955X GMAC Interface
+  */
+ 

 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
 @@ -32,6 +32,7 @@ enum ath79_soc_type {
 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
 @@ -32,6 +32,7 @@ enum ath79_soc_type {

diff --git a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
index 608f9f42e8ec504e41b56019a060634237149a76..027163fe687e1c3095e33ea03da16456c30d3319 100644 (file)
--- a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
+++ b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
@@ -1,3 +1,27 @@
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -1213,6 +1213,12 @@ config SOC_QCA955X
+       select PCI_AR724X if PCI
+       def_bool n
+ 
++config SOC_QCA956X
++      select USB_ARCH_HAS_EHCI
++      select HW_HAS_PCI
++      select PCI_AR724X if PCI
++      def_bool n
++
+ config ATH79_DEV_M25P80
+       select ATH79_DEV_SPI
+       def_bool n
+@@ -1250,7 +1256,7 @@ config ATH79_DEV_USB
+       def_bool n
+ 
+ config ATH79_DEV_WMAC
+-      depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
++      depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
+       def_bool n
+ 
+ config ATH79_NVRAM

 --- a/arch/mips/ath79/clock.c
 +++ b/arch/mips/ath79/clock.c
 @@ -520,6 +520,100 @@ static void __init qca955x_clocks_init(v
 --- a/arch/mips/ath79/clock.c
 +++ b/arch/mips/ath79/clock.c
 @@ -520,6 +520,100 @@ static void __init qca955x_clocks_init(v


@@ -142,74 +166,9 @@
                ath79_uart_data[0].uartclk = uart_clk_rate;
                platform_device_register(&ath79_uart_device);
        } else if (soc_is_ar933x()) {
                ath79_uart_data[0].uartclk = uart_clk_rate;
                platform_device_register(&ath79_uart_device);
        } else if (soc_is_ar933x()) {

---- a/arch/mips/ath79/dev-eth.c
-+++ b/arch/mips/ath79/dev-eth.c
-@@ -198,6 +198,8 @@ void __init ath79_register_mdio(unsigned
-       case ATH79_SOC_AR9330:
-       case ATH79_SOC_AR9331:
-       case ATH79_SOC_QCA9533:
-+      case ATH79_SOC_QCA9561:
-+      case ATH79_SOC_TP9343:
-               mdio_dev = &ath79_mdio1_device;
-               mdio_data = &ath79_mdio1_data;
-               break;
-@@ -256,6 +258,8 @@ void __init ath79_register_mdio(unsigned
-               break;
- 
-       case ATH79_SOC_QCA9533:
-+      case ATH79_SOC_QCA9561:
-+      case ATH79_SOC_TP9343:
-               mdio_data->builtin_switch = 1;
-               break;
- 
-@@ -571,6 +575,8 @@ static void __init ath79_init_eth_pll_da
-       case ATH79_SOC_QCA9533:
-       case ATH79_SOC_QCA9556:
-       case ATH79_SOC_QCA9558:
-+      case ATH79_SOC_QCA9561:
-+      case ATH79_SOC_TP9343:
-               pll_10 = AR934X_PLL_VAL_10;
-               pll_100 = AR934X_PLL_VAL_100;
-               pll_1000 = AR934X_PLL_VAL_1000;
-@@ -627,6 +633,8 @@ static int __init ath79_setup_phy_if_mod
-               case ATH79_SOC_AR9330:
-               case ATH79_SOC_AR9331:
-               case ATH79_SOC_QCA9533:
-+              case ATH79_SOC_QCA9561:
-+              case ATH79_SOC_TP9343:
-                       pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
-                       break;
- 
-@@ -688,6 +696,8 @@ static int __init ath79_setup_phy_if_mod
-               case ATH79_SOC_AR9330:
-               case ATH79_SOC_AR9331:
-               case ATH79_SOC_QCA9533:
-+              case ATH79_SOC_QCA9561:
-+              case ATH79_SOC_TP9343:
-                       pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
-                       break;
- 
-@@ -1018,6 +1028,8 @@ void __init ath79_register_eth(unsigned
-               break;
- 
-       case ATH79_SOC_QCA9533:
-+      case ATH79_SOC_QCA9561:
-+      case ATH79_SOC_TP9343:
-               if (id == 0) {
-                       pdata->reset_bit = AR933X_RESET_GE0_MAC |
-                                          AR933X_RESET_GE0_MDIO;
-@@ -1123,6 +1135,8 @@ void __init ath79_register_eth(unsigned
-               case ATH79_SOC_AR9330:
-               case ATH79_SOC_AR9331:
-               case ATH79_SOC_QCA9533:
-+              case ATH79_SOC_QCA9561:
-+              case ATH79_SOC_TP9343:
-                       pdata->mii_bus_dev = &ath79_mdio1_device.dev;
-                       break;
- 

 --- a/arch/mips/ath79/dev-usb.c
 +++ b/arch/mips/ath79/dev-usb.c
 --- a/arch/mips/ath79/dev-usb.c
 +++ b/arch/mips/ath79/dev-usb.c

-@@ -272,6 +272,19 @@ static void __init qca955x_usb_setup(voi
+@@ -296,6 +296,19 @@ static void __init qca955x_usb_setup(voi

                           &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  }
  
                           &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  }
  


@@ -229,8 +188,8 @@
  void __init ath79_register_usb(void)
  {
        if (soc_is_ar71xx())
  void __init ath79_register_usb(void)
  {
        if (soc_is_ar71xx())

-@@ -288,6 +301,8 @@ void __init ath79_register_usb(void)
-               ar934x_usb_setup();
+@@ -314,6 +327,8 @@ void __init ath79_register_usb(void)
+               qca953x_usb_setup();

        else if (soc_is_qca955x())
                qca955x_usb_setup();
 +      else if (soc_is_qca9561())
        else if (soc_is_qca955x())
                qca955x_usb_setup();
 +      else if (soc_is_qca9561())


@@ -291,9 +250,9 @@
            soc_is_ar913x() ||
            soc_is_ar933x())
                reg = AR71XX_GPIO_REG_FUNC;
            soc_is_ar913x() ||
            soc_is_ar933x())
                reg = AR71XX_GPIO_REG_FUNC;

--      else if (soc_is_ar934x())
+-      else if (soc_is_ar934x() || soc_is_qca953x())

 +      else if (soc_is_ar934x() ||
 +      else if (soc_is_ar934x() ||

-+               soc_is_qca956x())
++               soc_is_qca953x() || soc_is_qca956x())

                reg = AR934X_GPIO_REG_FUNC;
        else
                BUG();
                reg = AR934X_GPIO_REG_FUNC;
        else
                BUG();


@@ -326,7 +285,7 @@
                ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
        else
                BUG();
                ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
        else
                BUG();

-@@ -236,6 +237,99 @@ static void qca955x_irq_init(void)
+@@ -268,6 +269,97 @@ static void qca955x_irq_init(void)

        irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
  }
  
        irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
  }
  


@@ -406,15 +365,13 @@
 +
 +      for (i = ATH79_IP2_IRQ_BASE;
 +           i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 +
 +      for (i = ATH79_IP2_IRQ_BASE;
 +           i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)

-+              irq_set_chip_and_handler(i, &dummy_irq_chip,
-+                                       handle_level_irq);
++              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);

 +
 +      irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
 +
 +      for (i = ATH79_IP3_IRQ_BASE;
 +           i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
 +
 +      irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
 +
 +      for (i = ATH79_IP3_IRQ_BASE;
 +           i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)

-+              irq_set_chip_and_handler(i, &dummy_irq_chip,
-+                                       handle_level_irq);
++              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);

 +
 +      irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
 +
 +
 +      irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
 +


@@ -426,7 +383,7 @@
  asmlinkage void plat_irq_dispatch(void)
  {
        unsigned long pending;
  asmlinkage void plat_irq_dispatch(void)
  {
        unsigned long pending;

-@@ -359,6 +453,9 @@ void __init arch_init_irq(void)
+@@ -397,6 +489,9 @@ void __init arch_init_irq(void)

        } else if (soc_is_qca955x()) {
                ath79_ip2_handler = ath79_default_ip2_handler;
                ath79_ip3_handler = ath79_default_ip3_handler;
        } else if (soc_is_qca955x()) {
                ath79_ip2_handler = ath79_default_ip2_handler;
                ath79_ip3_handler = ath79_default_ip3_handler;


@@ -436,37 +393,13 @@
        } else {
                BUG();
        }
        } else {
                BUG();
        }

-@@ -371,4 +468,6 @@ void __init arch_init_irq(void)
-               ar934x_ip2_irq_init();
+@@ -411,4 +506,6 @@ void __init arch_init_irq(void)
+               qca953x_irq_init();

        else if (soc_is_qca955x())
                qca955x_irq_init();
 +      else if (soc_is_qca956x())
 +              qca956x_irq_init();
  }
        else if (soc_is_qca955x())
                qca955x_irq_init();
 +      else if (soc_is_qca956x())
 +              qca956x_irq_init();
  }

---- a/arch/mips/ath79/Kconfig
-+++ b/arch/mips/ath79/Kconfig
-@@ -1213,6 +1213,12 @@ config SOC_QCA955X
-       select PCI_AR724X if PCI
-       def_bool n
- 
-+config SOC_QCA956X
-+      select USB_ARCH_HAS_EHCI
-+      select HW_HAS_PCI
-+      select PCI_AR724X if PCI
-+      def_bool n
-+
- config ATH79_DEV_M25P80
-       select ATH79_DEV_SPI
-       def_bool n
-@@ -1250,7 +1256,7 @@ config ATH79_DEV_USB
-       def_bool n
- 
- config ATH79_DEV_WMAC
--      depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
-+      depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
-       def_bool n
- 
- config ATH79_NVRAM

 --- a/arch/mips/ath79/pci.c
 +++ b/arch/mips/ath79/pci.c
 @@ -68,6 +68,21 @@ static const struct ath79_pci_irq qca955
 --- a/arch/mips/ath79/pci.c
 +++ b/arch/mips/ath79/pci.c
 @@ -68,6 +68,21 @@ static const struct ath79_pci_irq qca955


@@ -519,7 +452,7 @@
                return -ENODEV;
 --- a/arch/mips/ath79/setup.c
 +++ b/arch/mips/ath79/setup.c
                return -ENODEV;
 --- a/arch/mips/ath79/setup.c
 +++ b/arch/mips/ath79/setup.c

-@@ -175,15 +175,30 @@ static void __init ath79_detect_sys_type
+@@ -175,14 +175,29 @@ static void __init ath79_detect_sys_type

                rev = id & QCA955X_REV_ID_REVISION_MASK;
                break;
  
                rev = id & QCA955X_REV_ID_REVISION_MASK;
                break;
  


@@ -542,18 +475,18 @@
        ath79_soc_rev = rev;
  
 -      if (soc_is_qca953x() || soc_is_qca955x())
        ath79_soc_rev = rev;
  
 -      if (soc_is_qca953x() || soc_is_qca955x())

+-              sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",

 +      if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561())
 +      if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561())

-               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
-                       chip, ver, rev);
++              sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
++                      chip, ver, rev);

 +      else if (soc_is_tp9343())
 +              sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
 +      else if (soc_is_tp9343())
 +              sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",

-+                      chip, rev);
+                       chip, rev);

        else
                sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
        else
                sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);

-       pr_info("SoC: %s\n", ath79_sys_type);

 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h

-@@ -131,6 +131,23 @@
+@@ -143,6 +143,23 @@

  #define QCA955X_NFC_BASE      0x1b800200
  #define QCA955X_NFC_SIZE      0xb8
  
  #define QCA955X_NFC_BASE      0x1b800200
  #define QCA955X_NFC_SIZE      0xb8
  


@@ -577,7 +510,7 @@
  #define AR9300_OTP_BASE               0x14000
  #define AR9300_OTP_STATUS     0x15f18
  #define AR9300_OTP_STATUS_TYPE                0x7
  #define AR9300_OTP_BASE               0x14000
  #define AR9300_OTP_STATUS     0x15f18
  #define AR9300_OTP_STATUS_TYPE                0x7

-@@ -356,6 +373,49 @@
+@@ -375,6 +392,49 @@

  #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL               BIT(21)
  #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL               BIT(24)
  
  #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL               BIT(21)
  #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL               BIT(24)
  


@@ -627,7 +560,7 @@
  /*
   * USB_CONFIG block
   */
  /*
   * USB_CONFIG block
   */

-@@ -403,6 +463,11 @@
+@@ -422,6 +482,11 @@

  #define QCA955X_RESET_REG_BOOTSTRAP           0xb0
  #define QCA955X_RESET_REG_EXT_INT_STATUS      0xac
  
  #define QCA955X_RESET_REG_BOOTSTRAP           0xb0
  #define QCA955X_RESET_REG_EXT_INT_STATUS      0xac
  


@@ -639,7 +572,7 @@
  #define MISC_INT_ETHSW                        BIT(12)
  #define MISC_INT_TIMER4                       BIT(10)
  #define MISC_INT_TIMER3                       BIT(9)
  #define MISC_INT_ETHSW                        BIT(12)
  #define MISC_INT_TIMER4                       BIT(10)
  #define MISC_INT_TIMER3                       BIT(9)

-@@ -551,6 +616,8 @@
+@@ -596,6 +661,8 @@

  
  #define QCA955X_BOOTSTRAP_REF_CLK_40  BIT(4)
  
  
  #define QCA955X_BOOTSTRAP_REF_CLK_40  BIT(4)
  


@@ -648,7 +581,7 @@
  #define AR934X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)
  #define AR934X_PCIE_WMAC_INT_WMAC_TX          BIT(1)
  #define AR934X_PCIE_WMAC_INT_WMAC_RXLP                BIT(2)
  #define AR934X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)
  #define AR934X_PCIE_WMAC_INT_WMAC_TX          BIT(1)
  #define AR934X_PCIE_WMAC_INT_WMAC_RXLP                BIT(2)

-@@ -600,6 +667,37 @@
+@@ -663,6 +730,37 @@

         QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
         QCA955X_EXT_INT_PCIE_RC2_INT3)
  
         QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
         QCA955X_EXT_INT_PCIE_RC2_INT3)
  


@@ -686,7 +619,7 @@
  #define REV_ID_MAJOR_MASK             0xfff0
  #define REV_ID_MAJOR_AR71XX           0x00a0
  #define REV_ID_MAJOR_AR913X           0x00b0
  #define REV_ID_MAJOR_MASK             0xfff0
  #define REV_ID_MAJOR_AR71XX           0x00a0
  #define REV_ID_MAJOR_AR913X           0x00b0

-@@ -615,6 +713,8 @@
+@@ -678,6 +776,8 @@

  #define REV_ID_MAJOR_QCA9533_V2               0x0160
  #define REV_ID_MAJOR_QCA9556          0x0130
  #define REV_ID_MAJOR_QCA9558          0x1130
  #define REV_ID_MAJOR_QCA9533_V2               0x0160
  #define REV_ID_MAJOR_QCA9556          0x0130
  #define REV_ID_MAJOR_QCA9558          0x1130


@@ -695,7 +628,7 @@
  
  #define AR71XX_REV_ID_MINOR_MASK      0x3
  #define AR71XX_REV_ID_MINOR_AR7130    0x0
  
  #define AR71XX_REV_ID_MINOR_MASK      0x3
  #define AR71XX_REV_ID_MINOR_AR7130    0x0

-@@ -639,6 +739,8 @@
+@@ -702,6 +802,8 @@

  
  #define QCA955X_REV_ID_REVISION_MASK  0xf
  
  
  #define QCA955X_REV_ID_REVISION_MASK  0xf
  


@@ -704,9 +637,9 @@
  /*
   * SPI block
   */
  /*
   * SPI block
   */

-@@ -684,6 +786,19 @@
- #define AR934X_GPIO_REG_OUT_FUNC5     0x40
- #define AR934X_GPIO_REG_FUNC          0x6c
+@@ -766,6 +868,19 @@
+ #define QCA953X_GPIO_OUT_MUX_LED_LINK4                44
+ #define QCA953X_GPIO_OUT_MUX_LED_LINK5                45

  
 +#define QCA956X_GPIO_REG_OUT_FUNC0    0x2c
 +#define QCA956X_GPIO_REG_OUT_FUNC1    0x30
  
 +#define QCA956X_GPIO_REG_OUT_FUNC0    0x2c
 +#define QCA956X_GPIO_REG_OUT_FUNC1    0x30


@@ -724,9 +657,9 @@
  #define AR71XX_GPIO_COUNT             16
  #define AR7240_GPIO_COUNT             18
  #define AR7241_GPIO_COUNT             20
  #define AR71XX_GPIO_COUNT             16
  #define AR7240_GPIO_COUNT             18
  #define AR7241_GPIO_COUNT             20

-@@ -692,6 +807,7 @@
+@@ -774,6 +889,7 @@

  #define AR934X_GPIO_COUNT             23
  #define AR934X_GPIO_COUNT             23

- #define QCA953X_GPIO_COUNT            24
+ #define QCA953X_GPIO_COUNT            18

  #define QCA955X_GPIO_COUNT            24
 +#define QCA956X_GPIO_COUNT            23
  
  #define QCA955X_GPIO_COUNT            24
 +#define QCA956X_GPIO_COUNT            23
  

diff --git a/target/linux/ar71xx/patches-3.18/736-MIPS-ath79-fix-chained-irq-disable.patch b/target/linux/ar71xx/patches-3.18/736-MIPS-ath79-fix-chained-irq-disable.patch
index 8cb38d3971678e3cf951d36e6ab2f4b170cd1f0c..8c0cc953842237c851132ae5529a1fd4a3ed98ca 100644 (file)
--- a/target/linux/ar71xx/patches-3.18/736-MIPS-ath79-fix-chained-irq-disable.patch
+++ b/target/linux/ar71xx/patches-3.18/736-MIPS-ath79-fix-chained-irq-disable.patch
@@ -19,7 +19,16 @@
  
        irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
  }
  
        irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
  }

-@@ -224,15 +225,13 @@ static void qca955x_irq_init(void)
+@@ -182,7 +183,7 @@ static void qca953x_irq_init(void)
+ 
+       for (i = ATH79_IP2_IRQ_BASE;
+            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
+-              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
++              irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
+ 
+       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
+ }
+@@ -256,15 +257,13 @@ static void qca955x_irq_init(void)

  
        for (i = ATH79_IP2_IRQ_BASE;
             i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  
        for (i = ATH79_IP2_IRQ_BASE;
             i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)


@@ -37,25 +46,23 @@
  
        irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
  }
  
        irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
  }

-@@ -313,15 +312,13 @@ static void qca956x_irq_init(void)
+@@ -345,13 +344,13 @@ static void qca956x_irq_init(void)

  
        for (i = ATH79_IP2_IRQ_BASE;
             i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
  
        for (i = ATH79_IP2_IRQ_BASE;
             i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)

--              irq_set_chip_and_handler(i, &dummy_irq_chip,
--                                       handle_level_irq);
+-              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);

 +              irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
  
        irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
  
        for (i = ATH79_IP3_IRQ_BASE;
             i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
 +              irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
  
        irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
  
        for (i = ATH79_IP3_IRQ_BASE;
             i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)

--              irq_set_chip_and_handler(i, &dummy_irq_chip,
--                                       handle_level_irq);
+-              irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);

 +              irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
  
        irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
  
 +              irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
  
        irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
  

-@@ -430,8 +427,35 @@ static void ar934x_ip3_handler(void)
+@@ -466,8 +465,35 @@ static void qca953x_ip3_handler(void)

        do_IRQ(ATH79_CPU_IRQ(3));
  }
  
        do_IRQ(ATH79_CPU_IRQ(3));
  }