- {"PPE", DANUBE_DMA_RX, 0, DANUBE_DMA_CH0_INT, 0},
- {"PPE", DANUBE_DMA_TX, 0, DANUBE_DMA_CH1_INT, 0},
- {"PPE", DANUBE_DMA_RX, 1, DANUBE_DMA_CH2_INT, 1},
- {"PPE", DANUBE_DMA_TX, 1, DANUBE_DMA_CH3_INT, 1},
- {"PPE", DANUBE_DMA_RX, 2, DANUBE_DMA_CH4_INT, 2},
- {"PPE", DANUBE_DMA_TX, 2, DANUBE_DMA_CH5_INT, 2},
- {"PPE", DANUBE_DMA_RX, 3, DANUBE_DMA_CH6_INT, 3},
- {"PPE", DANUBE_DMA_TX, 3, DANUBE_DMA_CH7_INT, 3},
- {"DEU", DANUBE_DMA_RX, 0, DANUBE_DMA_CH8_INT, 0},
- {"DEU", DANUBE_DMA_TX, 0, DANUBE_DMA_CH9_INT, 0},
- {"DEU", DANUBE_DMA_RX, 1, DANUBE_DMA_CH10_INT, 1},
- {"DEU", DANUBE_DMA_TX, 1, DANUBE_DMA_CH11_INT, 1},
- {"SPI", DANUBE_DMA_RX, 0, DANUBE_DMA_CH12_INT, 0},
- {"SPI", DANUBE_DMA_TX, 0, DANUBE_DMA_CH13_INT, 0},
- {"SDIO", DANUBE_DMA_RX, 0, DANUBE_DMA_CH14_INT, 0},
- {"SDIO", DANUBE_DMA_TX, 0, DANUBE_DMA_CH15_INT, 0},
- {"MCTRL0", DANUBE_DMA_RX, 0, DANUBE_DMA_CH16_INT, 0},
- {"MCTRL0", DANUBE_DMA_TX, 0, DANUBE_DMA_CH17_INT, 0},
- {"MCTRL1", DANUBE_DMA_RX, 1, DANUBE_DMA_CH18_INT, 1},
- {"MCTRL1", DANUBE_DMA_TX, 1, DANUBE_DMA_CH19_INT, 1}
+ {"PPE", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH0_INT, 0},
+ {"PPE", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH1_INT, 0},
+ {"PPE", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH2_INT, 1},
+ {"PPE", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH3_INT, 1},
+ {"PPE", IFXMIPS_DMA_RX, 2, IFXMIPS_DMA_CH4_INT, 2},
+ {"PPE", IFXMIPS_DMA_TX, 2, IFXMIPS_DMA_CH5_INT, 2},
+ {"PPE", IFXMIPS_DMA_RX, 3, IFXMIPS_DMA_CH6_INT, 3},
+ {"PPE", IFXMIPS_DMA_TX, 3, IFXMIPS_DMA_CH7_INT, 3},
+ {"DEU", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH8_INT, 0},
+ {"DEU", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH9_INT, 0},
+ {"DEU", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH10_INT, 1},
+ {"DEU", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH11_INT, 1},
+ {"SPI", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH12_INT, 0},
+ {"SPI", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH13_INT, 0},
+ {"SDIO", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH14_INT, 0},
+ {"SDIO", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH15_INT, 0},
+ {"MCTRL0", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH16_INT, 0},
+ {"MCTRL0", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH17_INT, 0},
+ {"MCTRL1", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH18_INT, 1},
+ {"MCTRL1", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH19_INT, 1}