cns3xxx: update to linux 3.10
authorFelix Fietkau <nbd@openwrt.org>
Thu, 31 Jul 2014 23:40:49 +0000 (23:40 +0000)
committerFelix Fietkau <nbd@openwrt.org>
Thu, 31 Jul 2014 23:40:49 +0000 (23:40 +0000)
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 41917

60 files changed:
target/linux/cns3xxx/Makefile
target/linux/cns3xxx/config-3.10 [new file with mode: 0644]
target/linux/cns3xxx/config-3.8 [deleted file]
target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S
target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c
target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/platform.h [deleted file]
target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c
target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c
target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c
target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c
target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c
target/linux/cns3xxx/files/drivers/usb/dwc/otg_attr.c
target/linux/cns3xxx/files/drivers/usb/dwc/otg_driver.c
target/linux/cns3xxx/files/drivers/usb/dwc/otg_hcd.c
target/linux/cns3xxx/files/drivers/usb/dwc/otg_hcd_queue.c
target/linux/cns3xxx/files/drivers/usb/dwc/otg_pcd.c
target/linux/cns3xxx/files/include/linux/platform_data/cns3xxx.h [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/000-cns3xxx_arch_include.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/001-cns3xxx_section_fix.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/010-arm_introduce-dma-fiq-irq-broadcast.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/020-watchdog_support.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/025-smp_support.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/030-pcie_clock.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/040-fiq_support.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/045-twd_base.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/055-pcie_io.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/060-pcie_abort.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/065-pcie_early_init.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/070-i2c_support.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/075-spi_support.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/080-sata_support.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/085-ethernet_support.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/090-timers.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/095-gpio_support.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/097-l2x0_cmdline_disable.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/200-dwc_otg_support.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/300-laguna_support.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.10/305-laguna_sdhci_card_detect.patch [new file with mode: 0644]
target/linux/cns3xxx/patches-3.8/010-move_virtual_io_space.patch [deleted file]
target/linux/cns3xxx/patches-3.8/015-clkdev_support.patch [deleted file]
target/linux/cns3xxx/patches-3.8/020-watchdog_support.patch [deleted file]
target/linux/cns3xxx/patches-3.8/021-cache_force_multi.patch [deleted file]
target/linux/cns3xxx/patches-3.8/025-smp_support.patch [deleted file]
target/linux/cns3xxx/patches-3.8/030-pcie_clock.patch [deleted file]
target/linux/cns3xxx/patches-3.8/035-add_io_spaces.patch [deleted file]
target/linux/cns3xxx/patches-3.8/040-fiq_support.patch [deleted file]
target/linux/cns3xxx/patches-3.8/045-twd_base.patch [deleted file]
target/linux/cns3xxx/patches-3.8/055-pcie_io.patch [deleted file]
target/linux/cns3xxx/patches-3.8/060-pcie_abort.patch [deleted file]
target/linux/cns3xxx/patches-3.8/065-pcie_early_init.patch [deleted file]
target/linux/cns3xxx/patches-3.8/070-i2c_support.patch [deleted file]
target/linux/cns3xxx/patches-3.8/075-spi_support.patch [deleted file]
target/linux/cns3xxx/patches-3.8/080-sata_support.patch [deleted file]
target/linux/cns3xxx/patches-3.8/085-ethernet_support.patch [deleted file]
target/linux/cns3xxx/patches-3.8/090-timers.patch [deleted file]
target/linux/cns3xxx/patches-3.8/095-gpio_support.patch [deleted file]
target/linux/cns3xxx/patches-3.8/097-l2x0_cmdline_disable.patch [deleted file]
target/linux/cns3xxx/patches-3.8/200-dwc_otg_support.patch [deleted file]
target/linux/cns3xxx/patches-3.8/300-laguna_support.patch [deleted file]
target/linux/cns3xxx/patches-3.8/305-laguna_sdhci_card_detect.patch [deleted file]

index 7105c45ea1bec23ffc182a85c206a214fee14d5e..5ae7a210b5d6d9fbfed9fada2ed90746ad87ea9c 100644 (file)
@@ -14,7 +14,7 @@ CPU_TYPE:=mpcore
 CPU_SUBTYPE:=vfp
 MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
 
-LINUX_VERSION:=3.8.13
+LINUX_VERSION:=3.10.49
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/cns3xxx/config-3.10 b/target/linux/cns3xxx/config-3.10
new file mode 100644 (file)
index 0000000..eda145b
--- /dev/null
@@ -0,0 +1,265 @@
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_CNS3XXX=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+CONFIG_ARCH_MULTI_V6=y
+CONFIG_ARCH_MULTI_V6_V7=y
+# CONFIG_ARCH_MULTI_V7 is not set
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+# CONFIG_ARCH_WM8750 is not set
+CONFIG_ARM=y
+# CONFIG_ARM_APPENDED_DTB is not set
+# CONFIG_ARM_CPU_SUSPEND is not set
+CONFIG_ARM_GIC=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_NR_BANKS=8
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+# CONFIG_ATA_SFF is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CNS3XXX_ETH=y
+CONFIG_COMMON_CLK=y
+CONFIG_CPU_32v6=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_ABRT_EV6=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_HAS_ASID=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_PABRT_V6=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_V6=y
+CONFIG_CPU_V6K=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_CNS3XXX=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_INCLUDE="debug/cns3xxx.S"
+CONFIG_DEBUG_UNCOMPRESS=y
+# CONFIG_DEBUG_USER is not set
+CONFIG_DMA_CACHE_FIQ_BROADCAST=y
+CONFIG_DTC=y
+# CONFIG_DWC_DEBUG is not set
+# CONFIG_DWC_DEVICE_ONLY is not set
+# CONFIG_DWC_HOST_ONLY is not set
+CONFIG_DWC_OTG_MODE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EEPROM_AT24=y
+CONFIG_FIQ=y
+CONFIG_FRAME_POINTER=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SMP=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=m
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_CNS3XXX=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_WORK=y
+CONFIG_KTIME_SCALAR=y
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_TRIGGER_NETDEV is not set
+CONFIG_LOCAL_TIMERS=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MACH_CNS3420VB is not set
+CONFIG_MACH_GW2388=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_CNS3XXX=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MPCORE_WATCHDOG=y
+CONFIG_MTD_M25P80=y
+# CONFIG_MTD_OF_PARTS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_OF is not set
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_VENDOR_CAVIUM=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=2
+CONFIG_NTP_PPS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_I2C=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PCI=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_PPS=y
+CONFIG_PPS_CLIENT_GPIO=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_PROC_STRIPPED is not set
+CONFIG_RAID_ATTRS=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1672=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SCHED_HRTICK=y
+CONFIG_SCSI=y
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SENSORS_AD7418=y
+CONFIG_SENSORS_GSC=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_CNS3XXX=y
+CONFIG_SPI_MASTER=y
+# CONFIG_STAGING is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+# CONFIG_TEGRA_HOST1X is not set
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TREE_RCU=y
+CONFIG_UID16=y
+CONFIG_UIDGID_CONVERTED=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_ARCH_HAS_XHCI=y
+CONFIG_USB_CNS3XXX_EHCI=y
+CONFIG_USB_CNS3XXX_OHCI=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_DWC_OTG=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_PCI=y
+# CONFIG_USB_ETH is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_USE_OF=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VFP=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/cns3xxx/config-3.8 b/target/linux/cns3xxx/config-3.8
deleted file mode 100644 (file)
index f308db0..0000000
+++ /dev/null
@@ -1,227 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_CNS3XXX=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ARCH_VT8500_SINGLE is not set
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_GIC=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-# CONFIG_ATA_SFF is not set
-CONFIG_ATA_VERBOSE_ERROR=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CNS3XXX_ETH=y
-CONFIG_CPU_32v6=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_ABRT_EV6=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V6=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V6=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_TLB_V6=y
-CONFIG_CPU_V6K=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_LL_UART_NONE=y
-# CONFIG_DEBUG_USER is not set
-CONFIG_DECOMPRESS_LZMA=y
-# CONFIG_DWC_DEBUG is not set
-# CONFIG_DWC_DEVICE_ONLY is not set
-# CONFIG_DWC_HOST_ONLY is not set
-CONFIG_DWC_OTG_MODE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EEPROM_AT24=y
-CONFIG_FIQ=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_PCA953X=y
-CONFIG_GPIO_PCA953X_IRQ=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_AOUT=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_TWD=y
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=m
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_CNS3XXX=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQ_DOMAIN=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEDS_TRIGGER_NETDEV is not set
-CONFIG_LOCAL_TIMERS=y
-CONFIG_M25PXX_USE_FAST_READ=y
-# CONFIG_MACH_CNS3420VB is not set
-CONFIG_MACH_GW2388=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_CNS3XXX=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-# CONFIG_MMC_TIFM_SD is not set
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MPCORE_WATCHDOG=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_VENDOR_CAVIUM=y
-CONFIG_NLS=y
-CONFIG_NR_CPUS=2
-CONFIG_NTP_PPS=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERCPU_RWSEM=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-CONFIG_PL310_ERRATA_588369=y
-CONFIG_PL310_ERRATA_727915=y
-CONFIG_PL310_ERRATA_769419=y
-CONFIG_PPS=y
-CONFIG_PPS_CLIENT_GPIO=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_PROC_STRIPPED is not set
-CONFIG_RAID_ATTRS=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1672=y
-CONFIG_SATA_AHCI=y
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SENSORS_AD7418=y
-CONFIG_SENSORS_GSC=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_CNS3XXX=y
-CONFIG_SPI_MASTER=y
-# CONFIG_STAGING is not set
-CONFIG_STOP_MACHINE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TREE_RCU=y
-CONFIG_UID16=y
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_USB=y
-# CONFIG_USB_AMD5536UDC is not set
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_CNS3XXX_EHCI=y
-CONFIG_USB_CNS3XXX_OHCI=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_DWC_OTG=y
-# CONFIG_USB_EG20T is not set
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_EHCI_PCI=y
-# CONFIG_USB_ETH is not set
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GOKU is not set
-# CONFIG_USB_NET2280 is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USE_GENERIC_SMP_HELPERS=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFP=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZONE_DMA_FLAG=0
index c02a382a9b7b2cb3e8725a946867bf4df71f6079..b1155ef5708ec53914cc110d2e8c2d8c25b94134 100644 (file)
  * R10 - DMA Direction
  * R11 - DMA type
  * R12 - fiq_buffer Address
- * R13 - DMA type Address
 */
 
        .global cns3xxx_fiq_end
 ENTRY(cns3xxx_fiq_start)
-       mov r8, #0
-       str r8, [r13]
+       str     r8, [r13]
 
-       ldr r9, [r12]
-       ldr r8, [r9]
-       add r8, r8, #1
-       str r8, [r9]
-
-       ldmib r12, {r8, r9, r10}
-       and r11, r10, #0x3000000
-       and r10, r10, #0xff
-
-       teq r11, #0x1000000
-       beq cns3xxx_dma_map_area
-       teq r11, #0x2000000
-       beq cns3xxx_dma_unmap_area
-       b cns3xxx_dma_flush_range
-
-cns3xxx_fiq_exit:
-       mov r8, #0
-       str r8, [r12, #12]
-       mcr p15, 0, r8, c7, c10, 4    @ drain write buffer
-       subs pc, lr, #4
-
-cns3xxx_dma_map_area:
-       add r9, r9, r8
-       teq r10, #DMA_FROM_DEVICE
-       beq cns3xxx_dma_inv_range
-       b cns3xxx_dma_clean_range
-
-cns3xxx_dma_unmap_area:
-       add r9, r9, r8
-       teq r10, #DMA_TO_DEVICE
-       bne cns3xxx_dma_inv_range
-       b cns3xxx_fiq_exit
+       ldmia   r12, {r8, r9, r10}
+       and     r11, r10, #0x3000000
+       and     r10, r10, #0xff
 
+       teq     r11, #0x1000000
+       beq     cns3xxx_dma_map_area
+       teq     r11, #0x2000000
+       beq     cns3xxx_dma_unmap_area
+       /* fall through */
 cns3xxx_dma_flush_range:
-       bic r8, r8, #D_CACHE_LINE_SIZE - 1
+       bic     r8, r8, #D_CACHE_LINE_SIZE - 1
 1:
-       mcr p15, 0, r8, c7, c14, 1   @ clean & invalidate D line
-       add r8, r8, #D_CACHE_LINE_SIZE
-       cmp r8, r9
-       blo 1b
-       b cns3xxx_fiq_exit
+       mcr     p15, 0, r8, c7, c14, 1          @ clean & invalidate D line
+       add     r8, r8, #D_CACHE_LINE_SIZE
+       cmp     r8, r9
+       blo     1b
+       /* fall through */
+cns3xxx_fiq_exit:
+       mov     r8, #0
+       str     r8, [r12, #8]
+       mcr     p15, 0, r8, c7, c10, 4          @ drain write buffer
+       subs    pc, lr, #4
 
+cns3xxx_dma_map_area:
+       add     r9, r9, r8
+       teq     r10, #DMA_FROM_DEVICE
+       beq     cns3xxx_dma_inv_range
+       teq     r10, #DMA_TO_DEVICE
+       bne     cns3xxx_dma_flush_range
+       /* fall through */
 cns3xxx_dma_clean_range:
-       bic r8, r8, #D_CACHE_LINE_SIZE - 1
+       bic     r8, r8, #D_CACHE_LINE_SIZE - 1
 1:
-       mcr p15, 0, r8, c7, c10, 1    @ clean D line
-       add r8, r8, #D_CACHE_LINE_SIZE
-       cmp r8, r9
-       blo 1b
-       b cns3xxx_fiq_exit
+       mcr     p15, 0, r8, c7, c10, 1          @ clean D line
+       add     r8, r8, #D_CACHE_LINE_SIZE
+       cmp     r8, r9
+       blo     1b
+       b       cns3xxx_fiq_exit
 
+cns3xxx_dma_unmap_area:
+       add     r9, r9, r8
+       teq     r10, #DMA_TO_DEVICE
+       beq     cns3xxx_fiq_exit
+       /* fall through */
 cns3xxx_dma_inv_range:
-       tst r8, #D_CACHE_LINE_SIZE - 1
-       bic r8, r8, #D_CACHE_LINE_SIZE - 1
-       mcrne p15, 0, r8, c7, c10, 1    @ clean D line
-       tst r9, #D_CACHE_LINE_SIZE - 1
-       bic r9, r9, #D_CACHE_LINE_SIZE - 1
-       mcrne p15, 0, r9, c7, c14, 1    @ clean & invalidate D line
+       tst     r8, #D_CACHE_LINE_SIZE - 1
+       bic     r8, r8, #D_CACHE_LINE_SIZE - 1
+       mcrne   p15, 0, r8, c7, c10, 1          @ clean D line
+       tst     r9, #D_CACHE_LINE_SIZE - 1
+       bic     r9, r9, #D_CACHE_LINE_SIZE - 1
+       mcrne   p15, 0, r9, c7, c14, 1          @ clean & invalidate D line
 1:
-       mcr p15, 0, r8, c7, c6, 1   @ invalidate D line
-       add r8, r8, #D_CACHE_LINE_SIZE
-       cmp r8, r9
-       blo 1b
-       b cns3xxx_fiq_exit
+       mcr     p15, 0, r8, c7, c6, 1           @ invalidate D line
+       add     r8, r8, #D_CACHE_LINE_SIZE
+       cmp     r8, r9
+       blo     1b
+       b       cns3xxx_fiq_exit
 
 cns3xxx_fiq_end:
index 4f5d50054f1c8e4f6b79b51bf1ca8512899d5780..35434f8514f0d6d55d29007966bda95774b3e07b 100644 (file)
@@ -11,6 +11,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
@@ -141,8 +142,6 @@ static void cns3xxx_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
        struct cns3xxx_gpio_chip *cchip = irq_get_handler_data(irq);
        struct irq_chip *chip = irq_get_chip(irq);
-       struct irq_chip_generic *gc = irq_desc_get_chip_data(desc);
-       struct irq_chip_type *ct = gc->chip_types;
        u16 i;
        u32 reg;
 
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/platform.h b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/platform.h
deleted file mode 100644 (file)
index f286d0d..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-cns3xxx/include/mach/platform.h
- *
- * Copyright 2011 Gateworks Corporation
- *               Chris Lang <clang@gateworks.com
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __ASM_ARCH_PLATFORM_H
-#define __ASM_ARCH_PLATFORM_H
-
-#ifndef __ASSEMBLY__
-
-/* Information about built-in Ethernet MAC interfaces */
-struct cns3xxx_plat_info {
-       u8 ports; /* Bitmap of enabled Ports */
-       u8 hwaddr[4][6];
-       u32 phy[3];
-};
-
-#endif /* __ASM_ARCH_PLATFORM_H */
-#endif
index 4903749c93409c9de90e813f253091e21491a072..9021f3d65f7300acb88f30f59ee169ea1af5323f 100644 (file)
 #include <linux/pps-gpio.h>
 #include <linux/usb/ehci_pdriver.h>
 #include <linux/usb/ohci_pdriver.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/platform_data/cns3xxx.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <mach/cns3xxx.h>
-#include <mach/irqs.h>
-#include <mach/platform.h>
-#include <mach/pm.h>
 #include <mach/gpio.h>
-#include <asm/hardware/gic.h>
 #include "core.h"
 #include "devices.h"
+#include "cns3xxx.h"
+#include "pm.h"
 
 #define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
 
@@ -192,8 +192,16 @@ static struct spi_board_info __initdata laguna_spi_devices[] = {
        },
 };
 
+static struct resource laguna_spi_resource = {
+       .start    = CNS3XXX_SSP_BASE + 0x40,
+       .end      = CNS3XXX_SSP_BASE + 0x6f,
+       .flags    = IORESOURCE_MEM,
+};
+
 static struct platform_device laguna_spi_controller = {
        .name = "cns3xxx_spi",
+       .resource = &laguna_spi_resource,
+       .num_resources = 1,
 };
 
 /*
@@ -314,9 +322,30 @@ static struct cns3xxx_plat_info laguna_net_data = {
        },
 };
 
+static struct resource laguna_net_resource[] = {
+       {
+               .name = "eth0_mem",
+               .start = CNS3XXX_SWITCH_BASE,
+               .end = CNS3XXX_SWITCH_BASE + SZ_4K - 1,
+               .flags = IORESOURCE_MEM
+       }, {
+               .name = "eth_rx",
+               .start = IRQ_CNS3XXX_SW_R0RXC,
+               .end = IRQ_CNS3XXX_SW_R0RXC,
+               .flags = IORESOURCE_IRQ
+       }, {
+               .name = "eth_stat",
+               .start = IRQ_CNS3XXX_SW_STATUS,
+               .end = IRQ_CNS3XXX_SW_STATUS,
+               .flags = IORESOURCE_IRQ
+       }
+};
+
 static struct platform_device laguna_net_device = {
        .name = "cns3xxx_eth",
        .id = 0,
+       .resource = laguna_net_resource,
+       .num_resources = ARRAY_SIZE(laguna_net_resource),
        .dev.platform_data = &laguna_net_data,
 };
 
@@ -361,29 +390,26 @@ static struct resource laguna_uart_resources[] = {
 
 static struct plat_serial8250_port laguna_uart_data[] = {
        {
-               .membase        = (char*) (CNS3XXX_UART0_BASE_VIRT),
                .mapbase        = (CNS3XXX_UART0_BASE),
                .irq            = IRQ_CNS3XXX_UART0,
                .iotype         = UPIO_MEM,
-               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
                .regshift       = 2,
                .uartclk        = 24000000,
                .type           = PORT_16550A,
        },{
-               .membase        = (char*) (CNS3XXX_UART1_BASE_VIRT),
                .mapbase        = (CNS3XXX_UART1_BASE),
                .irq            = IRQ_CNS3XXX_UART1,
                .iotype         = UPIO_MEM,
-               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
                .regshift       = 2,
                .uartclk        = 24000000,
                .type           = PORT_16550A,
        },{
-               .membase        = (char*) (CNS3XXX_UART2_BASE_VIRT),
                .mapbase        = (CNS3XXX_UART2_BASE),
                .irq            = IRQ_CNS3XXX_UART2,
                .iotype         = UPIO_MEM,
-               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
                .regshift       = 2,
                .uartclk        = 24000000,
                .type           = PORT_16550A,
@@ -526,7 +552,7 @@ static struct platform_device cns3xxx_usb_otg_device = {
 static struct resource laguna_i2c_resource[] = {
        {
                .start    = CNS3XXX_SSP_BASE + 0x20,
-               .end      = 0x7100003f,
+               .end      = CNS3XXX_SSP_BASE + 0x3f,
                .flags    = IORESOURCE_MEM,
        },{
                .start    = IRQ_CNS3XXX_I2C,
@@ -771,10 +797,37 @@ static struct gpio laguna_gpio_gw2380[] = {
  */
 static void __init laguna_init(void)
 {
+       struct clk *clk;
+       u32 __iomem *reg;
+
+       clk = clk_register_fixed_rate(NULL, "cpu", NULL,
+                                     CLK_IS_ROOT | CLK_IGNORE_UNUSED,
+                                     cns3xxx_cpu_clock() * (1000000 / 8));
+       clk_register_clkdev(clk, "cpu", NULL);
+
        platform_device_register(&laguna_watchdog);
 
        platform_device_register(&laguna_i2c_controller);
 
+       /* Set ext_int 0-3 drive strength to 21 mA */
+       reg = MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B;
+       *reg |= 0x300;
+
+       /* Enable SCL/SDA for I2C */
+       reg = MISC_GPIOB_PIN_ENABLE_REG;
+       *reg |= BIT(12) | BIT(13);
+
+       /* Enable MMC/SD pins */
+       reg = MISC_GPIOA_PIN_ENABLE_REG;
+       *reg |= 0xf80;
+
+       cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
+       cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
+       cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
+
+       cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C));
+       cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C));
+
        i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
 
        pm_power_off = cns3xxx_power_off;
@@ -786,22 +839,12 @@ static struct map_desc laguna_io_desc[] __initdata = {
                .pfn            = __phys_to_pfn(CNS3XXX_UART0_BASE),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
-       },{
-               .virtual        = CNS3XXX_UART1_BASE_VIRT,
-               .pfn            = __phys_to_pfn(CNS3XXX_UART1_BASE),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-       },{
-               .virtual        = CNS3XXX_UART2_BASE_VIRT,
-               .pfn            = __phys_to_pfn(CNS3XXX_UART2_BASE),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
        },
 };
 
 static void __init laguna_map_io(void)
 {
-       cns3xxx_common_init();
+       cns3xxx_map_io();
        cns3xxx_pcie_iotable_init();
        iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
        laguna_early_serial_setup();
@@ -1022,11 +1065,11 @@ static int __init laguna_model_setup(void)
 late_initcall(laguna_model_setup);
 
 MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
+       .smp            = smp_ops(cns3xxx_smp_ops),
        .atag_offset    = 0x100,
        .map_io         = laguna_map_io,
        .init_irq       = cns3xxx_init_irq,
-       .timer          = &cns3xxx_timer,
-       .handle_irq     = gic_handle_irq,
+       .init_time      = cns3xxx_timer_init,
        .init_machine   = laguna_init,
        .restart        = cns3xxx_restart,
 MACHINE_END
index 77ac97a20c525fb9b1782d92b719e3da70f1aeb7..53598857fdcc58c4eae6d3bcdd8ae1493e2f84ad 100644 (file)
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
-#include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 #include <asm/unified.h>
 #include <asm/fiq.h>
 #include <mach/smp.h>
-#include <mach/cns3xxx.h>
+#include "cns3xxx.h"
 
 static struct fiq_handler fh = {
        .name = "cns3xxx-fiq"
 };
 
-static unsigned int fiq_buffer[8];
+struct fiq_req {
+       union {
+               struct {
+                       const void *addr;
+                       size_t size;
+               } map;
+               struct {
+                       const void *addr;
+                       size_t size;
+               } unmap;
+               struct {
+                       const void *start;
+                       const void *end;
+               } flush;
+       };
+       volatile uint flags;
+       void __iomem *reg;
+} ____cacheline_aligned;
+
+extern unsigned int fiq_number[2];
+
+DEFINE_PER_CPU(struct fiq_req, fiq_data);
 
 #define FIQ_ENABLED         0x80000000
-#define FIQ_GENERATE                           0x00010000
+#define FIQ_GENERATE        0x00010000
 #define CNS3XXX_MAP_AREA    0x01000000
 #define CNS3XXX_UNMAP_AREA  0x02000000
 #define CNS3XXX_FLUSH_RANGE 0x03000000
 
 extern void cns3xxx_secondary_startup(void);
 extern unsigned char cns3xxx_fiq_start, cns3xxx_fiq_end;
-extern unsigned int fiq_number[2];
-extern struct cpu_cache_fns cpu_cache;
-struct cpu_cache_fns cpu_cache_save;
 
 #define SCU_CPU_STATUS 0x08
 static void __iomem *scu_base;
 
-static void __init cns3xxx_set_fiq_regs(void)
+static inline void __cpuinit cns3xxx_set_fiq_regs(unsigned int cpu)
 {
        struct pt_regs FIQ_regs;
-       unsigned int cpu = smp_processor_id();
-
-       if (cpu) {
-               FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[4];
-               FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(0);
-       } else {
-               FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[0];
-               FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(1);
-       }
+       struct fiq_req *fiq_req = &per_cpu(fiq_data, !cpu);
+
+       FIQ_regs.ARM_r8 = 0;
+       FIQ_regs.ARM_ip = (unsigned int)fiq_req;
+       FIQ_regs.ARM_sp = (int) MISC_FIQ_CPU(!cpu);
+       fiq_req->reg = MISC_FIQ_CPU(!cpu);
+
        set_fiq_regs(&FIQ_regs);
 }
 
@@ -74,16 +89,10 @@ static void __init cns3xxx_init_fiq(void)
        fiqhandler_length = &cns3xxx_fiq_end - &cns3xxx_fiq_start;
 
        ret = claim_fiq(&fh);
-
-       if (ret) {
+       if (ret)
                return;
-       }
 
        set_fiq_handler(fiqhandler_start, fiqhandler_length);
-       fiq_buffer[0] = (unsigned int)&fiq_number[0];
-       fiq_buffer[3] = 0;
-       fiq_buffer[4] = (unsigned int)&fiq_number[1];
-       fiq_buffer[7] = 0;
 }
 
 
@@ -104,17 +113,10 @@ static DEFINE_SPINLOCK(boot_lock);
 
 static void __cpuinit cns3xxx_secondary_init(unsigned int cpu)
 {
-       /*
-        * if any interrupts are already enabled for the primary
-        * core (e.g. timer irq), then they will not have been enabled
-        * for us: do so
-        */
-       gic_secondary_init(0);
-
        /*
         * Setup Secondary Core FIQ regs
         */
-       cns3xxx_set_fiq_regs();
+       cns3xxx_set_fiq_regs(1);
 
        /*
         * let the primary processor know we're out of the
@@ -122,14 +124,6 @@ static void __cpuinit cns3xxx_secondary_init(unsigned int cpu)
         */
        write_pen_release(-1);
 
-       /*
-        * Fixup DMA Operations
-        *
-        */
-       cpu_cache.dma_map_area = (void *)smp_dma_map_area;
-       cpu_cache.dma_unmap_area = (void *)smp_dma_unmap_area;
-       cpu_cache.dma_flush_range = (void *)smp_dma_flush_range;
-
        /*
         * Synchronise with the boot thread.
         */
@@ -162,7 +156,7 @@ static int __cpuinit cns3xxx_boot_secondary(unsigned int cpu, struct task_struct
         * the boot monitor to read the system wide flags register,
         * and branch to the address found there.
         */
-       gic_raise_softirq(cpumask_of(cpu), 1);
+       arch_send_wakeup_ipi_mask(cpumask_of(cpu));;
 
        timeout = jiffies + (1 * HZ);
        while (time_before(jiffies, timeout)) {
@@ -204,8 +198,6 @@ static void __init cns3xxx_smp_init_cpus(void)
                        break;
        }
        ncores = i;
-
-       set_smp_cross_call(gic_raise_softirq);
 }
 
 static void __init cns3xxx_smp_prepare_cpus(unsigned int max_cpus)
@@ -238,111 +230,105 @@ static void __init cns3xxx_smp_prepare_cpus(unsigned int max_cpus)
         * Setup FIQ's for main cpu
         */
        cns3xxx_init_fiq();
-       cns3xxx_set_fiq_regs();
-       memcpy((void *)&cpu_cache_save, (void *)&cpu_cache, sizeof(struct cpu_cache_fns));
+       cns3xxx_set_fiq_regs(0);
 }
 
+extern void v6_dma_map_area(const void *, size_t, int);
+extern void v6_dma_unmap_area(const void *, size_t, int);
+extern void v6_dma_flush_range(const void *, const void *);
+extern void v6_flush_kern_dcache_area(void *, size_t);
 
-static inline unsigned long cns3xxx_cpu_id(void)
+void fiq_dma_map_area(const void *addr, size_t size, int dir)
 {
-       unsigned long cpu;
-
-       asm volatile(
-               " mrc p15, 0, %0, c0, c0, 5  @ cns3xxx_cpu_id\n"
-               : "=r" (cpu) : : "memory", "cc");
-       return (cpu & 0xf);
-}
-
-void smp_dma_map_area(const void *addr, size_t size, int dir)
-{
-       unsigned int cpu;
        unsigned long flags;
+       struct fiq_req *req;
+
        raw_local_irq_save(flags);
-       cpu = cns3xxx_cpu_id();
-       if (cpu) {
-               fiq_buffer[1] = (unsigned int)addr;
-               fiq_buffer[2] = size;
-               fiq_buffer[3] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
-               smp_mb();
-               __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
-
-               cpu_cache_save.dma_map_area(addr, size, dir);
-               while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
-       } else {
-
-               fiq_buffer[5] = (unsigned int)addr;
-               fiq_buffer[6] = size;
-               fiq_buffer[7] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
-               smp_mb();
-               __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
-
-               cpu_cache_save.dma_map_area(addr, size, dir);
-               while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
+       /* currently, not possible to take cpu0 down, so only check cpu1 */
+       if (!cpu_online(1)) {
+               raw_local_irq_restore(flags);
+               v6_dma_map_area(addr, size, dir);
+               return;
        }
+
+       req = this_cpu_ptr(&fiq_data);
+       req->map.addr = addr;
+       req->map.size = size;
+       req->flags = dir | CNS3XXX_MAP_AREA;
+       smp_mb();
+
+       writel_relaxed(FIQ_GENERATE, req->reg);
+
+       v6_dma_map_area(addr, size, dir);
+       while (req->flags)
+               barrier();
+
        raw_local_irq_restore(flags);
 }
 
-void smp_dma_unmap_area(const void *addr, size_t size, int dir)
+void fiq_dma_unmap_area(const void *addr, size_t size, int dir)
 {
-       unsigned int cpu;
        unsigned long flags;
+       struct fiq_req *req;
 
        raw_local_irq_save(flags);
-       cpu = cns3xxx_cpu_id();
-       if (cpu) {
-
-               fiq_buffer[1] = (unsigned int)addr;
-               fiq_buffer[2] = size;
-               fiq_buffer[3] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
-               smp_mb();
-               __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
-
-               cpu_cache_save.dma_unmap_area(addr, size, dir);
-               while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
-       } else {
-
-               fiq_buffer[5] = (unsigned int)addr;
-               fiq_buffer[6] = size;
-               fiq_buffer[7] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
-               smp_mb();
-               __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
-
-               cpu_cache_save.dma_unmap_area(addr, size, dir);
-               while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
+       /* currently, not possible to take cpu0 down, so only check cpu1 */
+       if (!cpu_online(1)) {
+               raw_local_irq_restore(flags);
+               v6_dma_unmap_area(addr, size, dir);
+               return;
        }
+
+       req = this_cpu_ptr(&fiq_data);
+       req->unmap.addr = addr;
+       req->unmap.size = size;
+       req->flags = dir | CNS3XXX_UNMAP_AREA;
+       smp_mb();
+
+       writel_relaxed(FIQ_GENERATE, req->reg);
+
+       v6_dma_unmap_area(addr, size, dir);
+       while (req->flags)
+               barrier();
+
        raw_local_irq_restore(flags);
 }
 
-void smp_dma_flush_range(const void *start, const void *end)
+void fiq_dma_flush_range(const void *start, const void *end)
 {
-       unsigned int cpu;
        unsigned long flags;
+       struct fiq_req *req;
+
        raw_local_irq_save(flags);
-       cpu = cns3xxx_cpu_id();
-       if (cpu) {
-
-               fiq_buffer[1] = (unsigned int)start;
-               fiq_buffer[2] = (unsigned int)end;
-               fiq_buffer[3] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
-               smp_mb();
-               __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
-
-               cpu_cache_save.dma_flush_range(start, end);
-               while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
-       } else {
-
-               fiq_buffer[5] = (unsigned int)start;
-               fiq_buffer[6] = (unsigned int)end;
-               fiq_buffer[7] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
-               smp_mb();
-               __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
-
-               cpu_cache_save.dma_flush_range(start, end);
-               while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
+       /* currently, not possible to take cpu0 down, so only check cpu1 */
+       if (!cpu_online(1)) {
+               raw_local_irq_restore(flags);
+               v6_dma_flush_range(start, end);
+               return;
        }
+
+       req = this_cpu_ptr(&fiq_data);
+
+       req->flush.start = start;
+       req->flush.end = end;
+       req->flags = CNS3XXX_FLUSH_RANGE;
+       smp_mb();
+
+       writel_relaxed(FIQ_GENERATE, req->reg);
+
+       v6_dma_flush_range(start, end);
+
+       while (req->flags)
+               barrier();
+
        raw_local_irq_restore(flags);
 }
 
+void fiq_flush_kern_dcache_area(void *addr, size_t size)
+{
+       fiq_dma_flush_range(addr, addr + size);
+}
+
 struct smp_operations cns3xxx_smp_ops __initdata = {
        .smp_init_cpus      = cns3xxx_smp_init_cpus,
        .smp_prepare_cpus   = cns3xxx_smp_prepare_cpus,
index c3fd7c8972f7a8af15c036f61fcefa7fc38f77f3..7acff37d26d183bb5006072e818c263fd44a973d 100644 (file)
 #include <linux/delay.h>
 #include <linux/i2c.h>
 #include <linux/slab.h>
-#include <mach/pm.h>
-#include <mach/cns3xxx.h>
+#include <linux/clk.h>
 
 /*
  * We need the memory map
  */
 
-
-#define MISC_MEM_MAP_VALUE(reg_offset) (*((uint32_t volatile *)(CNS3XXX_MISC_BASE_VIRT + reg_offset)))
-#define MISC_IOCDB_CTRL                                MISC_MEM_MAP_VALUE(0x020)
-
-#define I2C_MEM_MAP_ADDR(x)         (CNS3XXX_SSP_BASE_VIRT + x)
+#define I2C_MEM_MAP_ADDR(x)         (i2c->base + x)
 #define I2C_MEM_MAP_VALUE(x)        (*((unsigned int volatile*)I2C_MEM_MAP_ADDR(x)))
 
-#define I2C_CONTROLLER_REG                    I2C_MEM_MAP_VALUE(0x20)
-#define I2C_TIME_OUT_REG                      I2C_MEM_MAP_VALUE(0x24)
-#define I2C_SLAVE_ADDRESS_REG                 I2C_MEM_MAP_VALUE(0x28)
-#define I2C_WRITE_DATA_REG                    I2C_MEM_MAP_VALUE(0x2C)
-#define I2C_READ_DATA_REG                     I2C_MEM_MAP_VALUE(0x30)
-#define I2C_INTERRUPT_STATUS_REG              I2C_MEM_MAP_VALUE(0x34)
-#define I2C_INTERRUPT_ENABLE_REG              I2C_MEM_MAP_VALUE(0x38)
-#define I2C_TWI_OUT_DLY_REG                                                    I2C_MEM_MAP_VALUE(0x3C)
+#define I2C_CONTROLLER_REG                    I2C_MEM_MAP_VALUE(0x00)
+#define I2C_TIME_OUT_REG                      I2C_MEM_MAP_VALUE(0x04)
+#define I2C_SLAVE_ADDRESS_REG                 I2C_MEM_MAP_VALUE(0x08)
+#define I2C_WRITE_DATA_REG                    I2C_MEM_MAP_VALUE(0x0C)
+#define I2C_READ_DATA_REG                     I2C_MEM_MAP_VALUE(0x10)
+#define I2C_INTERRUPT_STATUS_REG              I2C_MEM_MAP_VALUE(0x14)
+#define I2C_INTERRUPT_ENABLE_REG              I2C_MEM_MAP_VALUE(0x18)
+#define I2C_TWI_OUT_DLY_REG                                                    I2C_MEM_MAP_VALUE(0x1C)
 
 #define I2C_BUS_ERROR_FLAG     (0x1)
 #define I2C_ACTION_DONE_FLAG   (0x2)
@@ -203,24 +198,18 @@ static struct i2c_adapter cns3xxx_i2c_adapter = {
 
 static void cns3xxx_i2c_adapter_init(struct cns3xxx_i2c *i2c)
 {
-        cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
-        cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
-        cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
+       struct clk *clk;
+
+       clk = devm_clk_get(i2c->dev, "cpu");
+       if (WARN_ON(!clk))
+               return;
 
        /* Disable the I2C */
        I2C_CONTROLLER_REG = 0; /* Disabled the I2C */
 
-       //enable SCL and SDA which share pin with GPIOB_PIN_EN(0x18)
-       //GPIOB[12]: SCL
-       //GPIOB[13]: SDA
-       (*(u32*)(CNS3XXX_MISC_BASE_VIRT+0x18)) |= ((1<<12)|(1<<13));
-
-       MISC_IOCDB_CTRL &= ~0x300;
-       MISC_IOCDB_CTRL |= 0x300; //21mA...
-
        /* Check the Reg Dump when testing */
        I2C_TIME_OUT_REG =
-           ((((((cns3xxx_cpu_clock()*(1000000/8)) / (2 * CNS3xxx_I2C_CLK)) -
+           (((((clk_get_rate(clk) / (2 * CNS3xxx_I2C_CLK)) -
                1) & 0x3FF) << 8) | (1 << 7) | 0x7F);
        I2C_TWI_OUT_DLY_REG |= 0x3;
 
@@ -358,20 +347,9 @@ static int cns3xxx_i2c_remove(struct platform_device *pdev)
        return 0;
 }
 
-#ifdef CONFIG_PM
-#warning "CONFIG_PM defined: suspend and resume not implemented"
-#define cns3xxx_i2c_suspend    NULL
-#define cns3xxx_i2c_resume     NULL
-#else
-#define cns3xxx_i2c_suspend    NULL
-#define cns3xxx_i2c_resume     NULL
-#endif
-
 static struct platform_driver cns3xxx_i2c_driver = {
        .probe = cns3xxx_i2c_probe,
        .remove = cns3xxx_i2c_remove,
-       .suspend = cns3xxx_i2c_suspend,
-       .resume = cns3xxx_i2c_resume,
        .driver = {
                .owner = THIS_MODULE,
                .name = "cns3xxx-i2c",
index bbbbf5c09160cbc63a9d65e14b75e1a8cba691e9..b7e3758ba642dae18b1ae4d424131d628537824a 100644 (file)
@@ -20,9 +20,8 @@
 #include <linux/kernel.h>
 #include <linux/phy.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/cns3xxx.h>
 #include <linux/skbuff.h>
-#include <mach/irqs.h>
-#include <mach/platform.h>
 
 #define DRV_NAME "cns3xxx_eth"
 
@@ -282,7 +281,6 @@ struct _rx_ring {
 };
 
 struct sw {
-       struct resource *mem_res;
        struct switch_regs __iomem *regs;
        struct napi_struct napi;
        struct cns3xxx_plat_info *plat;
@@ -290,6 +288,8 @@ struct sw {
        struct _rx_ring rx_ring;
        struct sk_buff *frag_first;
        struct sk_buff *frag_last;
+       int rx_irq;
+       int stat_irq;
 };
 
 struct port {
@@ -377,14 +377,14 @@ static int cns3xxx_mdio_write(struct mii_bus *bus, int phy_id, int location,
        return ret;
 }
 
-static int cns3xxx_mdio_register(void)
+static int cns3xxx_mdio_register(void __iomem *base)
 {
        int err;
 
        if (!(mdio_bus = mdiobus_alloc()))
                return -ENOMEM;
 
-       mdio_regs = (struct switch_regs __iomem *)CNS3XXX_SWITCH_BASE_VIRT;
+       mdio_regs = base;
 
        spin_lock_init(&mdio_lock);
        mdio_bus->name = "CNS3xxx MII Bus";
@@ -441,7 +441,7 @@ static void eth_schedule_poll(struct sw *sw)
        if (unlikely(!napi_schedule_prep(&sw->napi)))
                return;
 
-       disable_irq_nosync(IRQ_CNS3XXX_SW_R0RXC);
+       disable_irq_nosync(sw->rx_irq);
        __napi_schedule(&sw->napi);
 }
 
@@ -716,7 +716,7 @@ static int eth_poll(struct napi_struct *napi, int budget)
        rx_ring->cur_index = i;
        if (!received) {
                napi_complete(napi);
-               enable_irq(IRQ_CNS3XXX_SW_R0RXC);
+               enable_irq(sw->rx_irq);
 
                /* if rx descriptors are full schedule another poll */
                if (rx_ring->desc[(i-1) & (RX_DESCS-1)].cown)
@@ -1007,8 +1007,8 @@ static int eth_open(struct net_device *dev)
        netif_start_queue(dev);
 
        if (!ports_open) {
-               request_irq(IRQ_CNS3XXX_SW_R0RXC, eth_rx_irq, IRQF_SHARED, "gig_switch", napi_dev);
-               request_irq(IRQ_CNS3XXX_SW_STATUS, eth_stat_irq, IRQF_SHARED, "gig_stat", napi_dev);
+               request_irq(sw->rx_irq, eth_rx_irq, IRQF_SHARED, "gig_switch", napi_dev);
+               request_irq(sw->stat_irq, eth_stat_irq, IRQF_SHARED, "gig_stat", napi_dev);
                napi_enable(&sw->napi);
                netif_start_queue(napi_dev);
 
@@ -1052,10 +1052,10 @@ static int eth_close(struct net_device *dev)
        phy_stop(port->phydev);
 
        if (!ports_open) {
-               disable_irq(IRQ_CNS3XXX_SW_R0RXC);
-               free_irq(IRQ_CNS3XXX_SW_R0RXC, napi_dev);
-               disable_irq(IRQ_CNS3XXX_SW_STATUS);
-               free_irq(IRQ_CNS3XXX_SW_STATUS, napi_dev);
+               disable_irq(sw->rx_irq);
+               free_irq(sw->rx_irq, napi_dev);
+               disable_irq(sw->stat_irq);
+               free_irq(sw->stat_irq, napi_dev);
                napi_disable(&sw->napi);
                netif_stop_queue(napi_dev);
                temp = __raw_readl(&sw->regs->mac_cfg[2]);
@@ -1172,26 +1172,36 @@ static int eth_init_one(struct platform_device *pdev)
        struct sw *sw;
        struct net_device *dev;
        struct cns3xxx_plat_info *plat = pdev->dev.platform_data;
-       u32 regs_phys;
        char phy_id[MII_BUS_ID_SIZE + 3];
        int err;
        u32 temp;
+       struct resource *res;
+       void __iomem *regs;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       regs = devm_ioremap_resource(&pdev->dev, res);
+       if (IS_ERR(regs))
+               return PTR_ERR(regs);
+
+       err = cns3xxx_mdio_register(regs);
+       if (err)
+               return err;
+
+       if (!(napi_dev = alloc_etherdev(sizeof(struct sw)))) {
+               err = -ENOMEM;
+               goto err_remove_mdio;
+       }
 
-       if (!(napi_dev = alloc_etherdev(sizeof(struct sw))))
-               return -ENOMEM;
        strcpy(napi_dev->name, "switch%d");
        napi_dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST;
 
        SET_NETDEV_DEV(napi_dev, &pdev->dev);
        sw = netdev_priv(napi_dev);
        memset(sw, 0, sizeof(struct sw));
-       sw->regs = (struct switch_regs __iomem *)CNS3XXX_SWITCH_BASE_VIRT;
-       regs_phys = CNS3XXX_SWITCH_BASE;
-       sw->mem_res = request_mem_region(regs_phys, REGS_SIZE, napi_dev->name);
-       if (!sw->mem_res) {
-               err = -EBUSY;
-               goto err_free;
-       }
+       sw->regs = regs;
+
+       sw->rx_irq = platform_get_irq_byname(pdev, "eth_rx");
+       sw->stat_irq = platform_get_irq_byname(pdev, "eth_stat");
 
        temp = __raw_readl(&sw->regs->phy_auto_addr);
        temp |= (3 << 30); /* maximum frame length: 9600 bytes */
@@ -1252,7 +1262,7 @@ static int eth_init_one(struct platform_device *pdev)
                memcpy(dev->dev_addr, &plat->hwaddr[i], ETH_ALEN);
 
                snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, "0", plat->phy[i]);
-               port->phydev = phy_connect(dev, phy_id, &cns3xxx_adjust_link, 0,
+               port->phydev = phy_connect(dev, phy_id, &cns3xxx_adjust_link,
                        PHY_INTERFACE_MODE_RGMII);
                if ((err = IS_ERR(port->phydev))) {
                        switch_port_tab[port->id] = 0;
@@ -1290,6 +1300,8 @@ free_ports:
        }
 err_free:
        free_netdev(napi_dev);
+err_remove_mdio:
+       cns3xxx_mdio_remove();
        return err;
 }
 
@@ -1311,8 +1323,9 @@ static int eth_remove_one(struct platform_device *pdev)
                }
        }
 
-       release_resource(sw->mem_res);
        free_netdev(napi_dev);
+       cns3xxx_mdio_remove();
+
        return 0;
 }
 
@@ -1324,16 +1337,12 @@ static struct platform_driver cns3xxx_eth_driver = {
 
 static int __init eth_init_module(void)
 {
-       int err;
-       if ((err = cns3xxx_mdio_register()))
-               return err;
        return platform_driver_register(&cns3xxx_eth_driver);
 }
 
 static void __exit eth_cleanup_module(void)
 {
        platform_driver_unregister(&cns3xxx_eth_driver);
-       cns3xxx_mdio_remove();
 }
 
 module_init(eth_init_module);
index 2642639867cc6a9727b0d75a0badde21606710ae..63019862ee12da9492782149bf468d028728e6b5 100644 (file)
 #include <asm/memory.h>
 #include <asm/dma.h>
 #include <asm/delay.h>
-#include <mach/cns3xxx.h>
 #include <linux/module.h>
-#include <mach/pm.h>
 
 /*
  * define access macros
  */
-#define SPI_MEM_MAP_VALUE(reg_offset)          (*((u32 volatile *)(CNS3XXX_SSP_BASE_VIRT + reg_offset)))
-
-#define SPI_CONFIGURATION_REG                  SPI_MEM_MAP_VALUE(0x40)
-#define SPI_SERVICE_STATUS_REG                 SPI_MEM_MAP_VALUE(0x44)
-#define SPI_BIT_RATE_CONTROL_REG               SPI_MEM_MAP_VALUE(0x48)
-#define SPI_TRANSMIT_CONTROL_REG               SPI_MEM_MAP_VALUE(0x4C)
-#define SPI_TRANSMIT_BUFFER_REG                        SPI_MEM_MAP_VALUE(0x50)
-#define SPI_RECEIVE_CONTROL_REG                        SPI_MEM_MAP_VALUE(0x54)
-#define SPI_RECEIVE_BUFFER_REG                 SPI_MEM_MAP_VALUE(0x58)
-#define SPI_FIFO_TRANSMIT_CONFIG_REG           SPI_MEM_MAP_VALUE(0x5C)
-#define SPI_FIFO_TRANSMIT_CONTROL_REG          SPI_MEM_MAP_VALUE(0x60)
-#define SPI_FIFO_RECEIVE_CONFIG_REG            SPI_MEM_MAP_VALUE(0x64)
-#define SPI_INTERRUPT_STATUS_REG               SPI_MEM_MAP_VALUE(0x68)
-#define SPI_INTERRUPT_ENABLE_REG               SPI_MEM_MAP_VALUE(0x6C)
-
-#define SPI_TRANSMIT_BUFFER_REG_ADDR           (CNS3XXX_SSP_BASE +0x50)
-#define SPI_RECEIVE_BUFFER_REG_ADDR            (CNS3XXX_SSP_BASE +0x58)
+#define SPI_MEM_MAP_VALUE(reg_offset)          (*((u32 volatile *)(hw->base + reg_offset)))
+
+#define SPI_CONFIGURATION_REG                  SPI_MEM_MAP_VALUE(0x00)
+#define SPI_SERVICE_STATUS_REG                 SPI_MEM_MAP_VALUE(0x04)
+#define SPI_BIT_RATE_CONTROL_REG               SPI_MEM_MAP_VALUE(0x08)
+#define SPI_TRANSMIT_CONTROL_REG               SPI_MEM_MAP_VALUE(0x0C)
+#define SPI_TRANSMIT_BUFFER_REG                        SPI_MEM_MAP_VALUE(0x10)
+#define SPI_RECEIVE_CONTROL_REG                        SPI_MEM_MAP_VALUE(0x14)
+#define SPI_RECEIVE_BUFFER_REG                 SPI_MEM_MAP_VALUE(0x18)
+#define SPI_FIFO_TRANSMIT_CONFIG_REG           SPI_MEM_MAP_VALUE(0x1C)
+#define SPI_FIFO_TRANSMIT_CONTROL_REG          SPI_MEM_MAP_VALUE(0x20)
+#define SPI_FIFO_RECEIVE_CONFIG_REG            SPI_MEM_MAP_VALUE(0x24)
+#define SPI_INTERRUPT_STATUS_REG               SPI_MEM_MAP_VALUE(0x28)
+#define SPI_INTERRUPT_ENABLE_REG               SPI_MEM_MAP_VALUE(0x2C)
+
+#define SPI_TRANSMIT_BUFFER_REG_ADDR           (CNS3XXX_SSP_BASE +0x10)
+#define SPI_RECEIVE_BUFFER_REG_ADDR            (CNS3XXX_SSP_BASE +0x18)
 
 /* Structure for SPI controller of CNS3XXX SOCs */
 struct cns3xxx_spi {
@@ -85,42 +83,43 @@ struct cns3xxx_spi {
        const unsigned char *tx;
        unsigned char *rx;
 
+       void __iomem *base;
        struct spi_master *master;
        struct platform_device *pdev;
        struct device *dev;
 };
 
-static inline u8 cns3xxx_spi_bus_idle(void)
+static inline u8 cns3xxx_spi_bus_idle(struct cns3xxx_spi *hw)
 {
        return ((SPI_SERVICE_STATUS_REG & 0x1) ? 0 : 1);
 }
 
-static inline u8 cns3xxx_spi_tx_buffer_empty(void)
+static inline u8 cns3xxx_spi_tx_buffer_empty(struct cns3xxx_spi *hw)
 {
        return ((SPI_INTERRUPT_STATUS_REG & (0x1 << 3)) ? 1 : 0);
 }
 
-static inline u8 cns3xxx_spi_rx_buffer_full(void)
+static inline u8 cns3xxx_spi_rx_buffer_full(struct cns3xxx_spi *hw)
 {
        return ((SPI_INTERRUPT_STATUS_REG & (0x1 << 2)) ? 1 : 0);
 }
 
-u8 cns3xxx_spi_tx_rx(u8 tx_channel, u8 tx_eof, u32 tx_data,
-                           u32 * rx_data)
+u8 cns3xxx_spi_tx_rx(struct cns3xxx_spi *hw, u8 tx_channel, u8 tx_eof,
+                    u32 tx_data, u32 * rx_data)
 {
        u8 rx_channel;
        u8 rx_eof;
 
-       while (!cns3xxx_spi_bus_idle()) ;       // do nothing
+       while (!cns3xxx_spi_bus_idle(hw)) ;     // do nothing
 
-       while (!cns3xxx_spi_tx_buffer_empty()) ;        // do nothing
+       while (!cns3xxx_spi_tx_buffer_empty(hw)) ;      // do nothing
 
        SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
        SPI_TRANSMIT_CONTROL_REG |= (tx_channel & 0x3) | ((tx_eof & 0x1) << 2);
 
        SPI_TRANSMIT_BUFFER_REG = tx_data;
 
-       while (!cns3xxx_spi_rx_buffer_full()) ; // do nothing
+       while (!cns3xxx_spi_rx_buffer_full(hw)) ;       // do nothing
 
        rx_channel = SPI_RECEIVE_CONTROL_REG & 0x3;
        rx_eof = (SPI_RECEIVE_CONTROL_REG & (0x1 << 2)) ? 1 : 0;
@@ -134,12 +133,12 @@ u8 cns3xxx_spi_tx_rx(u8 tx_channel, u8 tx_eof, u32 tx_data,
        }
 }
 
-u8 cns3xxx_spi_tx(u8 tx_channel, u8 tx_eof, u32 tx_data)
+u8 cns3xxx_spi_tx(struct cns3xxx_spi *hw, u8 tx_channel, u8 tx_eof, u32 tx_data)
 {
 
-        while (!cns3xxx_spi_bus_idle()) ;       // do nothing
+        while (!cns3xxx_spi_bus_idle(hw)) ;       // do nothing
 
-        while (!cns3xxx_spi_tx_buffer_empty()) ;        // do nothing
+        while (!cns3xxx_spi_tx_buffer_empty(hw)) ;        // do nothing
 
         SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
         SPI_TRANSMIT_CONTROL_REG |= (tx_channel & 0x3) | ((tx_eof & 0x1) << 2);
@@ -162,6 +161,7 @@ static int cns3xxx_spi_setup_transfer(struct spi_device *spi,
 
 static void cns3xxx_spi_chipselect(struct spi_device *spi, int value)
 {
+       struct cns3xxx_spi *hw = to_hw(spi);
        unsigned int spi_config;
 
        switch (value) {
@@ -221,7 +221,7 @@ static int cns3xxx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
                        dev_dbg(&spi->dev,
                                "[SPI_CNS3XXX_DEBUG] hw->tx[%02d]: 0x%02x\n", i,
                                hw->tx[i]);
-                       cns3xxx_spi_tx_rx(spi->chip_select, 0, hw->tx[i],
+                       cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, hw->tx[i],
                                          &rx_data);
                        if (hw->rx) {
                                hw->rx[i] = rx_data;
@@ -232,7 +232,7 @@ static int cns3xxx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
                }
 
                if (t->last_in_message_list) {
-                       cns3xxx_spi_tx_rx(spi->chip_select, 1, hw->tx[i],
+                       cns3xxx_spi_tx_rx(hw, spi->chip_select, 1, hw->tx[i],
                                          &rx_data);
                        if (hw->rx) {
                                hw->rx[i] = rx_data;
@@ -241,7 +241,7 @@ static int cns3xxx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
                                        i, hw->rx[i]);
                        }
                } else {
-                       cns3xxx_spi_tx_rx(spi->chip_select, 0, hw->tx[i],
+                       cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, hw->tx[i],
                                          &rx_data);
                }
                goto done;
@@ -251,7 +251,7 @@ static int cns3xxx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
                int i;
                u32 rx_data;
                for (i = 0; i < (hw->len - 1); i++) {
-                       cns3xxx_spi_tx_rx(spi->chip_select, 0, 0xff, &rx_data);
+                       cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, 0xff, &rx_data);
                        hw->rx[i] = rx_data;
                        dev_dbg(&spi->dev,
                                "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n", i,
@@ -259,9 +259,9 @@ static int cns3xxx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
                }
 
                if (t->last_in_message_list) {
-                       cns3xxx_spi_tx_rx(spi->chip_select, 1, 0xff, &rx_data);
+                       cns3xxx_spi_tx_rx(hw, spi->chip_select, 1, 0xff, &rx_data);
                } else {
-                       cns3xxx_spi_tx_rx(spi->chip_select, 0, 0xff, &rx_data);
+                       cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, 0xff, &rx_data);
                }
                hw->rx[i] = rx_data;
                dev_dbg(&spi->dev, "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n",
@@ -271,21 +271,8 @@ done:
        return hw->len;
 }
 
-static void __init cns3xxx_spi_initial(void)
+static void __init cns3xxx_spi_initial(struct cns3xxx_spi *hw)
 {
-       u32 __iomem *gpiob = (void __iomem *) (CNS3XXX_MISC_BASE_VIRT + 0x0018);
-       u32 gpiob_pins = __raw_readl(gpiob);
-
-       /* MMC/SD pins share with GPIOA */
-       gpiob_pins |= 0xf80;
-       __raw_writel(gpiob_pins, gpiob);
-
-       /* share pin config. */
-       //PM_PLL_HM_PD_CTRL_REG &= ~(0x1 << 5);
-       //HAL_MISC_ENABLE_SPI_PINS();
-       cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C));
-       cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C));
-
        SPI_CONFIGURATION_REG = (((0x0 & 0x3) << 0) |   /* 8bits shift length */
                                 (0x0 << 9) |   /* SPI mode */
                                 (0x0 << 10) |  /* disable FIFO */
@@ -328,10 +315,15 @@ static int cns3xxx_spi_probe(struct platform_device *pdev)
 {
        struct spi_master *master;
        struct cns3xxx_spi *hw;
+       struct resource *res;
        int err = 0;
 
        printk("%s: setup CNS3XXX SPI Controller\n", __FUNCTION__);
 
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       if (!res)
+               return -ENODEV;
+
        /* Allocate master with space for cns3xxx_spi */
        master = spi_alloc_master(&pdev->dev, sizeof(struct cns3xxx_spi));
        if (master == NULL) {
@@ -346,6 +338,13 @@ static int cns3xxx_spi_probe(struct platform_device *pdev)
        hw->master = spi_master_get(master);
        hw->dev = &pdev->dev;
 
+       hw->base = devm_ioremap_resource(hw->dev, res);
+       if (IS_ERR(hw->base)) {
+               dev_err(hw->dev, "Unable to map registers\n");
+               err = PTR_ERR(hw->base);
+               goto err_register;
+       }
+
        platform_set_drvdata(pdev, hw);
        init_completion(&hw->done);
 
@@ -365,7 +364,7 @@ static int cns3xxx_spi_probe(struct platform_device *pdev)
        dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
 
        /* SPI controller initializations */
-       cns3xxx_spi_initial();
+       cns3xxx_spi_initial(hw);
 
        /* register SPI controller */
 
index 45d06788a2368f8afd85a3a79941bff5b0bbc4a2..3fb67b934790d3fb9c55788ae4acebac914bafc2 100644 (file)
@@ -694,7 +694,7 @@ static ssize_t regdump_show( struct device *_dev,
        return sprintf( buf, "Register Dump\n" );
 }
 
-DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0);
+DEVICE_ATTR(regdump, S_IRUGO, regdump_show, 0);
 
 /**
  * Dump global registers and either host or device registers (depending on the
@@ -711,7 +711,7 @@ static ssize_t spramdump_show( struct device *_dev,
         return sprintf( buf, "SPRAM Dump\n" );
 }
 
-DEVICE_ATTR(spramdump, S_IRUGO|S_IWUSR, spramdump_show, 0);
+DEVICE_ATTR(spramdump, S_IRUGO, spramdump_show, 0);
 
 /**
  * Dump the current hcd state.
@@ -729,7 +729,7 @@ static ssize_t hcddump_show( struct device *_dev,
        return sprintf( buf, "HCD Dump\n" );
 }
 
-DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0);
+DEVICE_ATTR(hcddump, S_IRUGO, hcddump_show, 0);
 
 /**
  * Dump the average frame remaining at SOF. This can be used to
@@ -748,7 +748,7 @@ static ssize_t hcd_frrem_show( struct device *_dev,
        return sprintf( buf, "HCD Dump Frame Remaining\n" );
 }
 
-DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0);
+DEVICE_ATTR(hcd_frrem, S_IRUGO, hcd_frrem_show, 0);
 
 /**
  * Displays the time required to read the GNPTXFSIZ register many times (the
@@ -777,7 +777,7 @@ static ssize_t rd_reg_test_show( struct device *_dev,
                        RW_REG_COUNT, time * MSEC_PER_JIFFIE, time );
 }
 
-DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0);
+DEVICE_ATTR(rd_reg_test, S_IRUGO, rd_reg_test_show, 0);
 
 /**
  * Displays the time required to write the GNPTXFSIZ register many times (the
@@ -806,7 +806,7 @@ static ssize_t wr_reg_test_show( struct device *_dev,
                        RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
 }
 
-DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0);
+DEVICE_ATTR(wr_reg_test, S_IRUGO, wr_reg_test_show, 0);
 /**@}*/
 
 /**
index f1fece8bf8f6c4a8815787b39f1e2311124b8a40..549c6ebdbd8b0ba302138d0b8809737390e88b6c 100644 (file)
@@ -63,7 +63,6 @@
 #include <asm/io.h>
 
 #include <asm/sizes.h>
-#include <mach/pm.h>
 
 #include "otg_plat.h"
 #include "otg_attr.h"
index 5f33fa530a5b0ec5d73f9ee681734b12c9b4d274..9c1d04f5f411888bab782d48f31ddcf899f5f80d 100644 (file)
@@ -51,8 +51,6 @@
 #include <linux/dma-mapping.h>
 #include <linux/version.h>
 
-#include <mach/irqs.h>
-
 #include "otg_driver.h"
 #include "otg_hcd.h"
 #include "otg_regs.h"
index 6e7b53c3929a5cb1f62ec7dfbb40295c0d2f8e68..aaed49dcd6019d4b049a85a953aa92896ecdeb98 100644 (file)
@@ -49,8 +49,6 @@
 #include <linux/string.h>
 #include <linux/version.h>
 
-#include <mach/irqs.h>
-
 #include "otg_driver.h"
 #include "otg_hcd.h"
 #include "otg_regs.h"
index 823989a6f5979bea99fb3605f0279665fb7ca77c..967997c88dfb15145540eb5ae54e36243270675c 100644 (file)
@@ -75,7 +75,6 @@
 #include <linux/dma-mapping.h>
 #include <linux/version.h>
 
-#include <mach/irqs.h>
 #include <linux/usb/ch9.h>
 
 //#include <linux/usb_gadget.h>
diff --git a/target/linux/cns3xxx/files/include/linux/platform_data/cns3xxx.h b/target/linux/cns3xxx/files/include/linux/platform_data/cns3xxx.h
new file mode 100644 (file)
index 0000000..f286d0d
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-cns3xxx/include/mach/platform.h
+ *
+ * Copyright 2011 Gateworks Corporation
+ *               Chris Lang <clang@gateworks.com
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_PLATFORM_H
+#define __ASM_ARCH_PLATFORM_H
+
+#ifndef __ASSEMBLY__
+
+/* Information about built-in Ethernet MAC interfaces */
+struct cns3xxx_plat_info {
+       u8 ports; /* Bitmap of enabled Ports */
+       u8 hwaddr[4][6];
+       u32 phy[3];
+};
+
+#endif /* __ASM_ARCH_PLATFORM_H */
+#endif
diff --git a/target/linux/cns3xxx/patches-3.10/000-cns3xxx_arch_include.patch b/target/linux/cns3xxx/patches-3.10/000-cns3xxx_arch_include.patch
new file mode 100644 (file)
index 0000000..f98fe0c
--- /dev/null
@@ -0,0 +1,8 @@
+--- a/arch/arm/mach-cns3xxx/Makefile
++++ b/arch/arm/mach-cns3xxx/Makefile
+@@ -1,3 +1,5 @@
++ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
++
+ obj-$(CONFIG_ARCH_CNS3XXX)            += cns3xxx.o
+ cns3xxx-y                             += core.o pm.o
+ cns3xxx-$(CONFIG_ATAGS)                       += devices.o
diff --git a/target/linux/cns3xxx/patches-3.10/001-cns3xxx_section_fix.patch b/target/linux/cns3xxx/patches-3.10/001-cns3xxx_section_fix.patch
new file mode 100644 (file)
index 0000000..3191726
--- /dev/null
@@ -0,0 +1,11 @@
+--- a/arch/arm/mach-cns3xxx/core.c
++++ b/arch/arm/mach-cns3xxx/core.c
+@@ -307,7 +307,7 @@ static struct usb_ohci_pdata cns3xxx_usb
+       .power_off      = csn3xxx_usb_power_off,
+ };
+-static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
++static const struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
+       { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata },
+       { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata },
+       { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL },
diff --git a/target/linux/cns3xxx/patches-3.10/010-arm_introduce-dma-fiq-irq-broadcast.patch b/target/linux/cns3xxx/patches-3.10/010-arm_introduce-dma-fiq-irq-broadcast.patch
new file mode 100644 (file)
index 0000000..a666e17
--- /dev/null
@@ -0,0 +1,56 @@
+--- a/arch/arm/include/asm/glue-cache.h
++++ b/arch/arm/include/asm/glue-cache.h
+@@ -129,11 +129,19 @@
+ #define __cpuc_flush_user_range               __glue(_CACHE,_flush_user_cache_range)
+ #define __cpuc_coherent_kern_range    __glue(_CACHE,_coherent_kern_range)
+ #define __cpuc_coherent_user_range    __glue(_CACHE,_coherent_user_range)
++#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
+ #define __cpuc_flush_dcache_area      __glue(_CACHE,_flush_kern_dcache_area)
+ #define dmac_map_area                 __glue(_CACHE,_dma_map_area)
+ #define dmac_unmap_area                       __glue(_CACHE,_dma_unmap_area)
+ #define dmac_flush_range              __glue(_CACHE,_dma_flush_range)
++#else
++#define __cpuc_flush_dcache_area      __glue(fiq,_flush_kern_dcache_area)
++
++#define dmac_map_area                 __glue(fiq,_dma_map_area)
++#define dmac_unmap_area                       __glue(fiq,_dma_unmap_area)
++#define dmac_flush_range              __glue(fiq,_dma_flush_range)
++#endif /* CONFIG_DMA_CACHE_FIQ_BROADCAST */
+ #endif
+ #endif
+--- a/arch/arm/mm/Kconfig
++++ b/arch/arm/mm/Kconfig
+@@ -823,6 +823,17 @@ config DMA_CACHE_RWFO
+         in hardware, other workarounds are needed (e.g. cache
+         maintenance broadcasting in software via FIQ).
++config DMA_CACHE_FIQ_BROADCAST
++      bool "Enable fiq broadcast DMA cache maintenance"
++      depends on CPU_V6K && SMP
++      select FIQ
++      help
++        The Snoop Control Unit on ARM11MPCore does not detect the
++        cache maintenance operations and the dma_{map,unmap}_area()
++        functions may leave stale cache entries on other CPUs. By
++        enabling this option, fiq broadcast in the ARMv6
++        DMA cache maintenance functions is performed.
++
+ config OUTER_CACHE
+       bool
+--- a/arch/arm/mm/flush.c
++++ b/arch/arm/mm/flush.c
+@@ -286,7 +286,10 @@ void flush_dcache_page(struct page *page
+       mapping = page_mapping(page);
+-      if (!cache_ops_need_broadcast() &&
++      if (
++#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
++              !cache_ops_need_broadcast() &&
++#endif
+           mapping && !mapping_mapped(mapping))
+               clear_bit(PG_dcache_clean, &page->flags);
+       else {
diff --git a/target/linux/cns3xxx/patches-3.10/020-watchdog_support.patch b/target/linux/cns3xxx/patches-3.10/020-watchdog_support.patch
new file mode 100644 (file)
index 0000000..74ffcc3
--- /dev/null
@@ -0,0 +1,59 @@
+1. Made the connection between CNS3xxx SOCs(ARCH_CNS3xxx) and MPcore watchdog
+   since the CNS3xxx SOCs have ARM11 MPcore CPU.
+2. Enable mpcore_watchdog option as module to default configuration at
+   arch/arm/configs/cns3420vb_defconfig.
+
+Signed-off-by: Tommy Lin <tommy.lin@caviumnetworks.com>
+
+---
+arch/arm/Kconfig                     |    1 +
+ arch/arm/configs/cns3420vb_defconfig |    2 ++
+ arch/arm/mach-cns3xxx/cns3420vb.c    |   22 ++++++++++++++++++++++
+ 3 files changed, 25 insertions(+), 0 deletions(-)
+
+--- a/arch/arm/configs/cns3420vb_defconfig
++++ b/arch/arm/configs/cns3420vb_defconfig
+@@ -56,6 +56,8 @@ CONFIG_LEGACY_PTY_COUNT=16
+ # CONFIG_HW_RANDOM is not set
+ # CONFIG_HWMON is not set
+ # CONFIG_VGA_CONSOLE is not set
++CONFIG_WATCHDOG=y
++CONFIG_MPCORE_WATCHDOG=m
+ # CONFIG_HID_SUPPORT is not set
+ # CONFIG_USB_SUPPORT is not set
+ CONFIG_MMC=y
+--- a/arch/arm/mach-cns3xxx/cns3420vb.c
++++ b/arch/arm/mach-cns3xxx/cns3420vb.c
+@@ -206,10 +206,32 @@ static struct platform_device cns3xxx_us
+       },
+ };
++/* Watchdog */
++static struct resource cns3xxx_watchdog_resources[] = {
++      [0] = {
++              .start = CNS3XXX_TC11MP_TWD_BASE,
++              .end   = CNS3XXX_TC11MP_TWD_BASE + PAGE_SIZE - 1,
++              .flags = IORESOURCE_MEM,
++      },
++      [1] = {
++              .start = IRQ_LOCALWDOG,
++              .end   = IRQ_LOCALWDOG,
++              .flags = IORESOURCE_IRQ,
++      }
++};
++
++static struct platform_device cns3xxx_watchdog_device = {
++      .name           = "mpcore_wdt",
++      .id             = -1,
++      .num_resources  = ARRAY_SIZE(cns3xxx_watchdog_resources),
++      .resource       = cns3xxx_watchdog_resources,
++};
++
+ /*
+  * Initialization
+  */
+ static struct platform_device *cns3420_pdevs[] __initdata = {
++      &cns3xxx_watchdog_device,
+       &cns3420_nor_pdev,
+       &cns3xxx_usb_ehci_device,
+       &cns3xxx_usb_ohci_device,
diff --git a/target/linux/cns3xxx/patches-3.10/025-smp_support.patch b/target/linux/cns3xxx/patches-3.10/025-smp_support.patch
new file mode 100644 (file)
index 0000000..4d6e0cd
--- /dev/null
@@ -0,0 +1,30 @@
+--- a/arch/arm/mach-cns3xxx/Makefile
++++ b/arch/arm/mach-cns3xxx/Makefile
+@@ -5,3 +5,5 @@ cns3xxx-y                              += core.o pm.o
+ cns3xxx-$(CONFIG_ATAGS)                       += devices.o
+ cns3xxx-$(CONFIG_PCI)                 += pcie.o
+ cns3xxx-$(CONFIG_MACH_CNS3420VB)      += cns3420vb.o
++cns3xxx-$(CONFIG_SMP)                 += platsmp.o headsmp.o
++cns3xxx-$(CONFIG_HOTPLUG_CPU)         += hotplug.o
+--- a/arch/arm/mach-cns3xxx/Kconfig
++++ b/arch/arm/mach-cns3xxx/Kconfig
+@@ -6,6 +6,9 @@ config ARCH_CNS3XXX
+       select MIGHT_HAVE_CACHE_L2X0
+       select MIGHT_HAVE_PCI
+       select PCI_DOMAINS if PCI
++      select HAVE_ARM_SCU if SMP
++      select HAVE_ARM_TWD if LOCAL_TIMERS
++      select HAVE_SMP
+       help
+         Support for Cavium Networks CNS3XXX platform.
+--- a/arch/arm/mach-cns3xxx/core.h
++++ b/arch/arm/mach-cns3xxx/core.h
+@@ -11,6 +11,7 @@
+ #ifndef __CNS3XXX_CORE_H
+ #define __CNS3XXX_CORE_H
++extern struct smp_operations cns3xxx_smp_ops;
+ extern void cns3xxx_timer_init(void);
+ #ifdef CONFIG_CACHE_L2X0
diff --git a/target/linux/cns3xxx/patches-3.10/030-pcie_clock.patch b/target/linux/cns3xxx/patches-3.10/030-pcie_clock.patch
new file mode 100644 (file)
index 0000000..3734daf
--- /dev/null
@@ -0,0 +1,11 @@
+--- a/arch/arm/mach-cns3xxx/pcie.c
++++ b/arch/arm/mach-cns3xxx/pcie.c
+@@ -370,8 +370,6 @@ static int __init cns3xxx_pcie_init(void
+       for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
+               iotable_init(cns3xxx_pcie[i].cfg_bases,
+                            ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
+-              cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
+-              cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
+               cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
+               cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
+               pci_common_init(&cns3xxx_pcie[i].hw_pci);
diff --git a/target/linux/cns3xxx/patches-3.10/040-fiq_support.patch b/target/linux/cns3xxx/patches-3.10/040-fiq_support.patch
new file mode 100644 (file)
index 0000000..25a59c1
--- /dev/null
@@ -0,0 +1,40 @@
+--- a/arch/arm/mach-cns3xxx/Kconfig
++++ b/arch/arm/mach-cns3xxx/Kconfig
+@@ -9,6 +9,7 @@ config ARCH_CNS3XXX
+       select HAVE_ARM_SCU if SMP
+       select HAVE_ARM_TWD if LOCAL_TIMERS
+       select HAVE_SMP
++      select FIQ
+       help
+         Support for Cavium Networks CNS3XXX platform.
+--- a/arch/arm/mach-cns3xxx/Makefile
++++ b/arch/arm/mach-cns3xxx/Makefile
+@@ -5,5 +5,5 @@ cns3xxx-y                              += core.o pm.o
+ cns3xxx-$(CONFIG_ATAGS)                       += devices.o
+ cns3xxx-$(CONFIG_PCI)                 += pcie.o
+ cns3xxx-$(CONFIG_MACH_CNS3420VB)      += cns3420vb.o
+-cns3xxx-$(CONFIG_SMP)                 += platsmp.o headsmp.o
++cns3xxx-$(CONFIG_SMP)                 += platsmp.o headsmp.o cns3xxx_fiq.o
+ cns3xxx-$(CONFIG_HOTPLUG_CPU)         += hotplug.o
+--- a/arch/arm/mach-cns3xxx/cns3xxx.h
++++ b/arch/arm/mach-cns3xxx/cns3xxx.h
+@@ -267,6 +267,7 @@
+ #define MISC_PCIE_INT_MASK(x)                 MISC_MEM_MAP(0x978 + (x) * 0x100)
+ #define MISC_PCIE_INT_STATUS(x)                       MISC_MEM_MAP(0x97C + (x) * 0x100)
++#define MISC_FIQ_CPU(x)                               MISC_MEM_MAP(0xA58 - (x) * 0x4)
+ /*
+  * Power management and clock control
+  */
+--- a/arch/arm/mm/Kconfig
++++ b/arch/arm/mm/Kconfig
+@@ -806,7 +806,7 @@ config KUSER_HELPERS
+ config DMA_CACHE_RWFO
+       bool "Enable read/write for ownership DMA cache maintenance"
+-      depends on CPU_V6K && SMP
++      depends on CPU_V6K && SMP && !ARCH_CNS3XXX
+       default y
+       help
+         The Snoop Control Unit on ARM11MPCore does not detect the
diff --git a/target/linux/cns3xxx/patches-3.10/045-twd_base.patch b/target/linux/cns3xxx/patches-3.10/045-twd_base.patch
new file mode 100644 (file)
index 0000000..b93a7f1
--- /dev/null
@@ -0,0 +1,45 @@
+--- a/arch/arm/mach-cns3xxx/core.c
++++ b/arch/arm/mach-cns3xxx/core.c
+@@ -17,6 +17,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/usb/ehci_pdriver.h>
+ #include <linux/usb/ohci_pdriver.h>
++#include <asm/smp_twd.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/map.h>
+ #include <asm/mach/time.h>
+@@ -26,6 +27,8 @@
+ #include "core.h"
+ #include "pm.h"
++#define IRQ_LOCALTIMER 29
++
+ static struct map_desc cns3xxx_io_desc[] __initdata = {
+       {
+               .virtual        = CNS3XXX_TC11MP_SCU_BASE_VIRT,
+@@ -159,6 +162,17 @@ static struct irqaction cns3xxx_timer_ir
+       .handler        = cns3xxx_timer_interrupt,
+ };
++static void __init cns3xxx_init_twd(void)
++{
++#ifdef CONFIG_LOCAL_TIMERS
++      static DEFINE_TWD_LOCAL_TIMER(cns3xx_twd_local_timer,
++              CNS3XXX_TC11MP_TWD_BASE,
++              IRQ_LOCALTIMER);
++
++      twd_local_timer_register(&cns3xx_twd_local_timer);
++#endif
++}
++
+ /*
+  * Set up the clock source and clock events devices
+  */
+@@ -212,6 +226,7 @@ static void __init __cns3xxx_timer_init(
+       setup_irq(timer_irq, &cns3xxx_timer_irq);
+       cns3xxx_clockevents_init(timer_irq);
++      cns3xxx_init_twd();
+ }
+ void __init cns3xxx_timer_init(void)
diff --git a/target/linux/cns3xxx/patches-3.10/055-pcie_io.patch b/target/linux/cns3xxx/patches-3.10/055-pcie_io.patch
new file mode 100644 (file)
index 0000000..b4f2768
--- /dev/null
@@ -0,0 +1,19 @@
+--- a/arch/arm/mach-cns3xxx/core.c
++++ b/arch/arm/mach-cns3xxx/core.c
+@@ -50,6 +50,16 @@ static struct map_desc cns3xxx_io_desc[]
+               .pfn            = __phys_to_pfn(CNS3XXX_PM_BASE),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
++      }, {
++              .virtual        = CNS3XXX_PCIE0_IO_BASE_VIRT,
++              .pfn            = __phys_to_pfn(CNS3XXX_PCIE0_IO_BASE),
++              .length         = SZ_16M,
++              .type           = MT_DEVICE,
++      }, {
++              .virtual        = CNS3XXX_PCIE1_IO_BASE_VIRT,
++              .pfn            = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE),
++              .length         = SZ_16M,
++              .type           = MT_DEVICE,
+       },
+ };
diff --git a/target/linux/cns3xxx/patches-3.10/060-pcie_abort.patch b/target/linux/cns3xxx/patches-3.10/060-pcie_abort.patch
new file mode 100644 (file)
index 0000000..e1edf05
--- /dev/null
@@ -0,0 +1,129 @@
+--- a/arch/arm/mach-cns3xxx/pcie.c
++++ b/arch/arm/mach-cns3xxx/pcie.c
+@@ -92,6 +92,79 @@ static void __iomem *cns3xxx_pci_cfg_bas
+       return base + offset;
+ }
++static inline int check_master_abort(struct pci_bus *bus, unsigned int devfn, int where)
++{
++      struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
++
++  /* check PCI-compatible status register after access */
++      if (cnspci->linked) {
++              void __iomem *host_base;
++              u32 sreg, ereg;
++
++              host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual;
++              sreg = __raw_readw(host_base + 0x6) & 0xF900;
++              ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg
++
++              if (sreg | ereg) {
++                      /* SREG:
++                       *  BIT15 - Detected Parity Error
++                       *  BIT14 - Signaled System Error
++                       *  BIT13 - Received Master Abort
++                       *  BIT12 - Received Target Abort
++                       *  BIT11 - Signaled Target Abort
++                       *  BIT08 - Master Data Parity Error
++                       *
++                       * EREG:
++                       *  BIT20 - Unsupported Request
++                       *  BIT19 - ECRC
++                       *  BIT18 - Malformed TLP
++                       *  BIT17 - Receiver Overflow
++                       *  BIT16 - Unexpected Completion
++                       *  BIT15 - Completer Abort
++                       *  BIT14 - Completion Timeout
++                       *  BIT13 - Flow Control Protocol Error
++                       *  BIT12 - Poisoned TLP
++                       *  BIT04 - Data Link Protocol Error
++                       *
++                       * TODO: see Documentation/pci-error-recovery.txt
++                       *    implement error_detected handler
++                       */
++/*
++                      printk("pci error: %04d:%02x:%02x.%02x sreg=0x%04x ereg=0x%08x", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), sreg, ereg);
++                      if (sreg & BIT(15)) printk(" <PERR");
++                      if (sreg & BIT(14)) printk(" >SERR");
++                      if (sreg & BIT(13)) printk(" <MABRT");
++                      if (sreg & BIT(12)) printk(" <TABRT");
++                      if (sreg & BIT(11)) printk(" >TABRT");
++                      if (sreg & BIT( 8)) printk(" MPERR");
++
++                      if (ereg & BIT(20)) printk(" Unsup");
++                      if (ereg & BIT(19)) printk(" ECRC");
++                      if (ereg & BIT(18)) printk(" MTLP");
++                      if (ereg & BIT(17)) printk(" OFLOW");
++                      if (ereg & BIT(16)) printk(" Unex");
++                      if (ereg & BIT(15)) printk(" ABRT");
++                      if (ereg & BIT(14)) printk(" COMPTO");
++                      if (ereg & BIT(13)) printk(" FLOW");
++                      if (ereg & BIT(12)) printk(" PTLP");
++                      if (ereg & BIT( 4)) printk(" DLINK");
++                      printk("\n");
++*/
++                      pr_debug("%s failed port%d sreg=0x%04x\n", __func__,
++                              cnspci->hw_pci.domain, sreg);
++
++                      /* make sure the status bits are reset */
++                      __raw_writew(sreg, host_base + 6);
++                      __raw_writel(ereg, host_base + 0x104);
++                      return 1;
++              }
++      }
++      else
++              return 1;
++
++  return 0;
++}
++
+ static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+                                  int where, int size, u32 *val)
+ {
+@@ -108,6 +181,11 @@ static int cns3xxx_pci_read_config(struc
+       v = __raw_readl(base);
++      if (check_master_abort(bus, devfn, where)) {
++              printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)= master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
++              return PCIBIOS_DEVICE_NOT_FOUND;
++      }
++
+       if (bus->number == 0 && devfn == 0 &&
+                       (where & 0xffc) == PCI_CLASS_REVISION) {
+               /*
+@@ -137,11 +215,19 @@ static int cns3xxx_pci_write_config(stru
+               return PCIBIOS_SUCCESSFUL;
+       v = __raw_readl(base);
++      if (check_master_abort(bus, devfn, where)) {
++              printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)=0x%08x master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
++              return PCIBIOS_DEVICE_NOT_FOUND;
++      }
+       v &= ~(mask << shift);
+       v |= (val & mask) << shift;
+       __raw_writel(v, base);
++      if (check_master_abort(bus, devfn, where)) {
++              printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)=0x%08x master_abort on write\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
++              return PCIBIOS_DEVICE_NOT_FOUND;
++      }
+       return PCIBIOS_SUCCESSFUL;
+ }
+@@ -352,8 +438,14 @@ static void __init cns3xxx_pcie_hw_init(
+ static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
+                                     struct pt_regs *regs)
+ {
++#if 0
++/* R14_ABORT = PC+4 for XSCALE but not ARM11MPCORE
++ * ignore imprecise aborts and use PCI-compatible Status register to
++ * determine errors instead
++ */
+       if (fsr & (1 << 10))
+               regs->ARM_pc += 4;
++#endif
+       return 0;
+ }
diff --git a/target/linux/cns3xxx/patches-3.10/065-pcie_early_init.patch b/target/linux/cns3xxx/patches-3.10/065-pcie_early_init.patch
new file mode 100644 (file)
index 0000000..252c955
--- /dev/null
@@ -0,0 +1,84 @@
+--- a/arch/arm/mach-cns3xxx/cns3420vb.c
++++ b/arch/arm/mach-cns3xxx/cns3420vb.c
+@@ -261,11 +261,21 @@ static struct map_desc cns3420_io_desc[]
+ static void __init cns3420_map_io(void)
+ {
+       cns3xxx_map_io();
++      cns3xxx_pcie_iotable_init();
+       iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
+       cns3420_early_serial_setup();
+ }
++static int __init cns3420vb_pcie_init(void)
++{
++      if (!machine_is_cns3420vb())
++              return 0;
++
++      return cns3xxx_pcie_init();
++}
++subsys_initcall(cns3420vb_pcie_init);
++
+ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
+       .atag_offset    = 0x100,
+       .nr_irqs        = NR_IRQS_CNS3XXX,
+--- a/arch/arm/mach-cns3xxx/core.h
++++ b/arch/arm/mach-cns3xxx/core.h
+@@ -13,6 +13,7 @@
+ extern struct smp_operations cns3xxx_smp_ops;
+ extern void cns3xxx_timer_init(void);
++extern void cns3xxx_pcie_iotable_init(void);
+ #ifdef CONFIG_CACHE_L2X0
+ void __init cns3xxx_l2x0_init(void);
+@@ -22,6 +23,7 @@ static inline void cns3xxx_l2x0_init(voi
+ void __init cns3xxx_map_io(void);
+ void __init cns3xxx_init_irq(void);
++int  __init cns3xxx_pcie_init(void);
+ void cns3xxx_power_off(void);
+ void cns3xxx_restart(char, const char *);
+--- a/arch/arm/mach-cns3xxx/pcie.c
++++ b/arch/arm/mach-cns3xxx/pcie.c
+@@ -449,7 +449,18 @@ static int cns3xxx_pcie_abort_handler(un
+       return 0;
+ }
+-static int __init cns3xxx_pcie_init(void)
++
++void __init cns3xxx_pcie_iotable_init()
++{
++      int i;
++
++      for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
++              iotable_init(cns3xxx_pcie[i].cfg_bases,
++                           ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
++      }
++}
++
++int __init cns3xxx_pcie_init(void)
+ {
+       int i;
+@@ -460,15 +471,14 @@ static int __init cns3xxx_pcie_init(void
+                       "imprecise external abort");
+       for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
+-              iotable_init(cns3xxx_pcie[i].cfg_bases,
+-                           ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
+               cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
+-              cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
+-              pci_common_init(&cns3xxx_pcie[i].hw_pci);
++              if (cns3xxx_pcie[i].linked) {
++                      cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
++                      pci_common_init(&cns3xxx_pcie[i].hw_pci);
++              }
+       }
+       pci_assign_unassigned_resources();
+       return 0;
+ }
+-device_initcall(cns3xxx_pcie_init);
diff --git a/target/linux/cns3xxx/patches-3.10/070-i2c_support.patch b/target/linux/cns3xxx/patches-3.10/070-i2c_support.patch
new file mode 100644 (file)
index 0000000..adac218
--- /dev/null
@@ -0,0 +1,31 @@
+--- a/drivers/i2c/busses/Kconfig
++++ b/drivers/i2c/busses/Kconfig
+@@ -375,6 +375,18 @@ config I2C_CBUS_GPIO
+         This driver can also be built as a module.  If so, the module
+         will be called i2c-cbus-gpio.
++config I2C_CNS3XXX
++      tristate "Cavium CNS3xxx I2C driver"
++      depends on ARCH_CNS3XXX
++      help
++        Support for Cavium CNS3xxx I2C controller driver.
++
++        This driver can also be built as a module.  If so, the module
++        will be called i2c-cns3xxx.
++
++        Please note that this driver might be needed to bring up other
++        devices such as Cavium CNS3xxx Ethernet.
++
+ config I2C_CPM
+       tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)"
+       depends on (CPM1 || CPM2) && OF_I2C
+--- a/drivers/i2c/busses/Makefile
++++ b/drivers/i2c/busses/Makefile
+@@ -89,6 +89,7 @@ obj-$(CONFIG_I2C_ACORN)              += i2c-acorn.o
+ obj-$(CONFIG_I2C_ELEKTOR)     += i2c-elektor.o
+ obj-$(CONFIG_I2C_PCA_ISA)     += i2c-pca-isa.o
+ obj-$(CONFIG_I2C_SIBYTE)      += i2c-sibyte.o
++obj-$(CONFIG_I2C_CNS3XXX)     += i2c-cns3xxx.o
+ obj-$(CONFIG_SCx200_ACB)      += scx200_acb.o
+ obj-$(CONFIG_SCx200_I2C)      += scx200_i2c.o
diff --git a/target/linux/cns3xxx/patches-3.10/075-spi_support.patch b/target/linux/cns3xxx/patches-3.10/075-spi_support.patch
new file mode 100644 (file)
index 0000000..6acb2cd
--- /dev/null
@@ -0,0 +1,57 @@
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -142,6 +142,13 @@ config SPI_CLPS711X
+         This enables dedicated general purpose SPI/Microwire1-compatible
+         master mode interface (SSI1) for CLPS711X-based CPUs.
++config SPI_CNS3XXX
++      tristate "CNS3XXX SPI controller"
++      depends on ARCH_CNS3XXX && SPI_MASTER
++      select SPI_BITBANG
++      help
++        This enables using the CNS3XXX SPI controller in master mode.
++
+ config SPI_COLDFIRE_QSPI
+       tristate "Freescale Coldfire QSPI controller"
+       depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x)
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -20,6 +20,7 @@ obj-$(CONFIG_SPI_BFIN5XX)            += spi-bfin5x
+ obj-$(CONFIG_SPI_BFIN_SPORT)          += spi-bfin-sport.o
+ obj-$(CONFIG_SPI_BITBANG)             += spi-bitbang.o
+ obj-$(CONFIG_SPI_BUTTERFLY)           += spi-butterfly.o
++obj-$(CONFIG_SPI_CNS3XXX)             += spi-cns3xxx.o
+ obj-$(CONFIG_SPI_CLPS711X)            += spi-clps711x.o
+ obj-$(CONFIG_SPI_COLDFIRE_QSPI)               += spi-coldfire-qspi.o
+ obj-$(CONFIG_SPI_DAVINCI)             += spi-davinci.o
+--- a/drivers/spi/spi-bitbang.c
++++ b/drivers/spi/spi-bitbang.c
+@@ -328,6 +328,12 @@ static void bitbang_work(struct work_str
+                                */
+                               if (!m->is_dma_mapped)
+                                       t->rx_dma = t->tx_dma = 0;
++
++                              if (t->transfer_list.next == &m->transfers)
++                                      t->last_in_message_list = 1;
++                              else
++                                      t->last_in_message_list = 0;
++
+                               status = bitbang->txrx_bufs(spi, t);
+                       }
+                       if (status > 0)
+--- a/include/linux/spi/spi.h
++++ b/include/linux/spi/spi.h
+@@ -524,6 +524,13 @@ struct spi_transfer {
+       u32             speed_hz;
+       struct list_head transfer_list;
++
++#ifdef CONFIG_ARCH_CNS3XXX
++      unsigned        last_in_message_list;
++#ifdef CONFIG_SPI_CNS3XXX_2IOREAD
++      u8      dio_read;
++#endif
++#endif
+ };
+ /**
diff --git a/target/linux/cns3xxx/patches-3.10/080-sata_support.patch b/target/linux/cns3xxx/patches-3.10/080-sata_support.patch
new file mode 100644 (file)
index 0000000..93d29bf
--- /dev/null
@@ -0,0 +1,44 @@
+--- a/arch/arm/mach-cns3xxx/devices.c
++++ b/arch/arm/mach-cns3xxx/devices.c
+@@ -40,7 +40,7 @@ static struct resource cns3xxx_ahci_reso
+ static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
+ static struct platform_device cns3xxx_ahci_pdev = {
+-      .name           = "ahci",
++      .name           = "cns3xxx-ahci",
+       .id             = 0,
+       .resource       = cns3xxx_ahci_resource,
+       .num_resources  = ARRAY_SIZE(cns3xxx_ahci_resource),
+--- a/drivers/ata/ahci_platform.c
++++ b/drivers/ata/ahci_platform.c
+@@ -31,6 +31,7 @@ enum ahci_type {
+       AHCI,           /* standard platform ahci */
+       IMX53_AHCI,     /* ahci on i.mx53 */
+       STRICT_AHCI,    /* delayed DMA engine start */
++      CNS3XXX_AHCI,   /* AHCI on cns3xxx */
+ };
+ static struct platform_device_id ahci_devtype[] = {
+@@ -44,6 +45,9 @@ static struct platform_device_id ahci_de
+               .name = "strict-ahci",
+               .driver_data = STRICT_AHCI,
+       }, {
++              .name = "cns3xxx-ahci",
++              .driver_data = CNS3XXX_AHCI,
++      }, {
+               /* sentinel */
+       }
+ };
+@@ -80,6 +84,12 @@ static const struct ata_port_info ahci_p
+               .udma_mask      = ATA_UDMA6,
+               .port_ops       = &ahci_platform_ops,
+       },
++      [CNS3XXX_AHCI] = {
++              .flags          = AHCI_FLAG_COMMON,
++              .pio_mask       = ATA_PIO4,
++              .udma_mask      = ATA_UDMA6,
++              .port_ops       = &ahci_platform_retry_srst_ops,
++      }
+ };
+ static struct scsi_host_template ahci_platform_sht = {
diff --git a/target/linux/cns3xxx/patches-3.10/085-ethernet_support.patch b/target/linux/cns3xxx/patches-3.10/085-ethernet_support.patch
new file mode 100644 (file)
index 0000000..84548a3
--- /dev/null
@@ -0,0 +1,20 @@
+--- a/drivers/net/ethernet/Kconfig
++++ b/drivers/net/ethernet/Kconfig
+@@ -32,6 +32,7 @@ source "drivers/net/ethernet/calxeda/Kco
+ source "drivers/net/ethernet/chelsio/Kconfig"
+ source "drivers/net/ethernet/cirrus/Kconfig"
+ source "drivers/net/ethernet/cisco/Kconfig"
++source "drivers/net/ethernet/cavium/Kconfig"
+ source "drivers/net/ethernet/davicom/Kconfig"
+ config DNET
+--- a/drivers/net/ethernet/Makefile
++++ b/drivers/net/ethernet/Makefile
+@@ -15,6 +15,7 @@ obj-$(CONFIG_NET_BFIN) += adi/
+ obj-$(CONFIG_NET_VENDOR_BROADCOM) += broadcom/
+ obj-$(CONFIG_NET_VENDOR_BROCADE) += brocade/
+ obj-$(CONFIG_NET_CALXEDA_XGMAC) += calxeda/
++obj-$(CONFIG_NET_VENDOR_CAVIUM) += cavium/
+ obj-$(CONFIG_NET_VENDOR_CHELSIO) += chelsio/
+ obj-$(CONFIG_NET_VENDOR_CIRRUS) += cirrus/
+ obj-$(CONFIG_NET_VENDOR_CISCO) += cisco/
diff --git a/target/linux/cns3xxx/patches-3.10/090-timers.patch b/target/linux/cns3xxx/patches-3.10/090-timers.patch
new file mode 100644 (file)
index 0000000..46635e1
--- /dev/null
@@ -0,0 +1,104 @@
+--- a/arch/arm/mach-cns3xxx/core.c
++++ b/arch/arm/mach-cns3xxx/core.c
+@@ -103,12 +103,13 @@ static void cns3xxx_timer_set_mode(enum 
+       switch (mode) {
+       case CLOCK_EVT_MODE_PERIODIC:
+-              reload = pclk * 20 / (3 * HZ) * 0x25000;
++              reload = pclk * 1000000 / HZ;
+               writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
+               ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
+               break;
+       case CLOCK_EVT_MODE_ONESHOT:
+               /* period set, and timer enabled in 'next_event' hook */
++              writel(0, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
+               ctrl |= (1 << 2) | (1 << 9);
+               break;
+       case CLOCK_EVT_MODE_UNUSED:
+@@ -136,7 +137,7 @@ static struct clock_event_device cns3xxx
+       .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+       .set_mode       = cns3xxx_timer_set_mode,
+       .set_next_event = cns3xxx_timer_set_next_event,
+-      .rating         = 350,
++      .rating         = 300,
+       .cpumask        = cpu_all_mask,
+ };
+@@ -183,6 +184,35 @@ static void __init cns3xxx_init_twd(void
+ #endif
+ }
++static cycle_t cns3xxx_get_cycles(struct clocksource *cs)
++{
++  u64 val;
++
++  val = readl(cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
++  val &= 0xffff;
++
++  return ((val << 32) | readl(cns3xxx_tmr1 + TIMER_FREERUN_OFFSET));
++}
++
++static struct clocksource clocksource_cns3xxx = {
++      .name = "freerun",
++      .rating = 200,
++      .read = cns3xxx_get_cycles,
++      .mask = CLOCKSOURCE_MASK(48),
++      .shift  = 16,
++      .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
++};
++
++static void __init cns3xxx_clocksource_init(void)
++{
++      /* Reset the FreeRunning counter */
++      writel((1 << 16), cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
++
++      clocksource_cns3xxx.mult =
++              clocksource_khz2mult(100, clocksource_cns3xxx.shift);
++      clocksource_register(&clocksource_cns3xxx);
++}
++
+ /*
+  * Set up the clock source and clock events devices
+  */
+@@ -200,13 +230,12 @@ static void __init __cns3xxx_timer_init(
+       /* stop free running timer3 */
+       writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
+-      /* timer1 */
+-      writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
+-      writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
+-
+       writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
+       writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
++      val = (cns3xxx_cpu_clock() >> 3) * 1000000 / HZ;
++      writel(val, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
++
+       /* mask irq, non-mask timer1 overflow */
+       irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
+       irq_mask &= ~(1 << 2);
+@@ -218,23 +247,9 @@ static void __init __cns3xxx_timer_init(
+       val |= (1 << 9);
+       writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+-      /* timer2 */
+-      writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
+-      writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
+-
+-      /* mask irq */
+-      irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
+-      irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
+-      writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
+-
+-      /* down counter */
+-      val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+-      val |= (1 << 10);
+-      writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+-
+-      /* Make irqs happen for the system timer */
+       setup_irq(timer_irq, &cns3xxx_timer_irq);
++      cns3xxx_clocksource_init();
+       cns3xxx_clockevents_init(timer_irq);
+       cns3xxx_init_twd();
+ }
diff --git a/target/linux/cns3xxx/patches-3.10/095-gpio_support.patch b/target/linux/cns3xxx/patches-3.10/095-gpio_support.patch
new file mode 100644 (file)
index 0000000..baa16cd
--- /dev/null
@@ -0,0 +1,82 @@
+--- a/arch/arm/mach-cns3xxx/cns3420vb.c
++++ b/arch/arm/mach-cns3xxx/cns3420vb.c
+@@ -245,6 +245,10 @@ static void __init cns3420_init(void)
+       cns3xxx_ahci_init();
+       cns3xxx_sdhci_init();
++      cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
++              NR_IRQS_CNS3XXX);
++      cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
++              NR_IRQS_CNS3XXX + 32);
+       pm_power_off = cns3xxx_power_off;
+ }
+--- a/arch/arm/mach-cns3xxx/core.h
++++ b/arch/arm/mach-cns3xxx/core.h
+@@ -15,12 +15,6 @@ extern struct smp_operations cns3xxx_smp
+ extern void cns3xxx_timer_init(void);
+ extern void cns3xxx_pcie_iotable_init(void);
+-#ifdef CONFIG_CACHE_L2X0
+-void __init cns3xxx_l2x0_init(void);
+-#else
+-static inline void cns3xxx_l2x0_init(void) {}
+-#endif /* CONFIG_CACHE_L2X0 */
+-
+ void __init cns3xxx_map_io(void);
+ void __init cns3xxx_init_irq(void);
+ int  __init cns3xxx_pcie_init(void);
+--- a/arch/arm/mach-cns3xxx/Kconfig
++++ b/arch/arm/mach-cns3xxx/Kconfig
+@@ -2,6 +2,8 @@ config ARCH_CNS3XXX
+       bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
+       select ARM_GIC
+       select CPU_V6K
++      select ARCH_REQUIRE_GPIOLIB
++      select GENERIC_IRQ_CHIP
+       select GENERIC_CLOCKEVENTS
+       select MIGHT_HAVE_CACHE_L2X0
+       select MIGHT_HAVE_PCI
+--- a/arch/arm/mach-cns3xxx/Makefile
++++ b/arch/arm/mach-cns3xxx/Makefile
+@@ -1,7 +1,7 @@
+ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+ obj-$(CONFIG_ARCH_CNS3XXX)            += cns3xxx.o
+-cns3xxx-y                             += core.o pm.o
++cns3xxx-y                             += core.o pm.o gpio.o
+ cns3xxx-$(CONFIG_ATAGS)                       += devices.o
+ cns3xxx-$(CONFIG_PCI)                 += pcie.o
+ cns3xxx-$(CONFIG_MACH_CNS3420VB)      += cns3420vb.o
+--- a/arch/arm/mach-cns3xxx/cns3xxx.h
++++ b/arch/arm/mach-cns3xxx/cns3xxx.h
+@@ -68,8 +68,10 @@
+ #define SMC_PCELL_ID_3_OFFSET                 0xFFC
+ #define CNS3XXX_GPIOA_BASE                    0x74000000      /* GPIO port A */
++#define CNS3XXX_GPIOA_BASE_VIRT                       0xFB006000
+ #define CNS3XXX_GPIOB_BASE                    0x74800000      /* GPIO port B */
++#define CNS3XXX_GPIOB_BASE_VIRT                       0xFB007000
+ #define CNS3XXX_RTC_BASE                      0x75000000      /* Real Time Clock */
+--- a/arch/arm/mach-cns3xxx/core.c
++++ b/arch/arm/mach-cns3xxx/core.c
+@@ -60,6 +60,16 @@ static struct map_desc cns3xxx_io_desc[]
+               .pfn            = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE),
+               .length         = SZ_16M,
+               .type           = MT_DEVICE,
++      }, {
++              .virtual        = CNS3XXX_GPIOA_BASE_VIRT,
++              .pfn            = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
++              .length         = SZ_4K,
++              .type           = MT_DEVICE,
++      }, {
++              .virtual        = CNS3XXX_GPIOB_BASE_VIRT,
++              .pfn            = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
++              .length         = SZ_4K,
++              .type           = MT_DEVICE,
+       },
+ };
diff --git a/target/linux/cns3xxx/patches-3.10/097-l2x0_cmdline_disable.patch b/target/linux/cns3xxx/patches-3.10/097-l2x0_cmdline_disable.patch
new file mode 100644 (file)
index 0000000..73619ba
--- /dev/null
@@ -0,0 +1,54 @@
+--- a/arch/arm/mach-cns3xxx/core.c
++++ b/arch/arm/mach-cns3xxx/core.c
+@@ -273,13 +273,26 @@ void __init cns3xxx_timer_init(void)
+ #ifdef CONFIG_CACHE_L2X0
+-void __init cns3xxx_l2x0_init(void)
++static int cns3xxx_l2x0_enable = 1;
++
++static int __init cns3xxx_l2x0_disable(char *s)
++{
++      cns3xxx_l2x0_enable = 0;
++      return 1;
++}
++__setup("nol2x0", cns3xxx_l2x0_disable);
++
++static int __init cns3xxx_l2x0_init(void)
+ {
+-      void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
++      void __iomem *base;
+       u32 val;
++      if (!cns3xxx_l2x0_enable)
++              return 0;
++
++      base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
+       if (WARN_ON(!base))
+-              return;
++              return 0;
+       /*
+        * Tag RAM Control register
+@@ -309,7 +322,10 @@ void __init cns3xxx_l2x0_init(void)
+       /* 32 KiB, 8-way, parity disable */
+       l2x0_init(base, 0x00540000, 0xfe000fff);
++
++      return 0;
+ }
++arch_initcall(cns3xxx_l2x0_init);
+ #endif /* CONFIG_CACHE_L2X0 */
+--- a/arch/arm/mach-cns3xxx/cns3420vb.c
++++ b/arch/arm/mach-cns3xxx/cns3420vb.c
+@@ -239,8 +239,6 @@ static struct platform_device *cns3420_p
+ static void __init cns3420_init(void)
+ {
+-      cns3xxx_l2x0_init();
+-
+       platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
+       cns3xxx_ahci_init();
diff --git a/target/linux/cns3xxx/patches-3.10/200-dwc_otg_support.patch b/target/linux/cns3xxx/patches-3.10/200-dwc_otg_support.patch
new file mode 100644 (file)
index 0000000..b8c06c9
--- /dev/null
@@ -0,0 +1,48 @@
+--- a/drivers/usb/Kconfig
++++ b/drivers/usb/Kconfig
+@@ -136,6 +136,8 @@ source "drivers/usb/musb/Kconfig"
+ source "drivers/usb/renesas_usbhs/Kconfig"
++source "drivers/usb/dwc/Kconfig"
++
+ source "drivers/usb/class/Kconfig"
+ source "drivers/usb/storage/Kconfig"
+--- a/drivers/usb/core/urb.c
++++ b/drivers/usb/core/urb.c
+@@ -17,7 +17,11 @@ static void urb_destroy(struct kref *kre
+       if (urb->transfer_flags & URB_FREE_BUFFER)
+               kfree(urb->transfer_buffer);
+-
++      if (urb->aligned_transfer_buffer) {
++              kfree(urb->aligned_transfer_buffer);
++              urb->aligned_transfer_buffer = 0;
++              urb->aligned_transfer_dma = 0;
++      }
+       kfree(urb);
+ }
+--- a/include/linux/usb.h
++++ b/include/linux/usb.h
+@@ -1404,6 +1404,9 @@ struct urb {
+       unsigned int transfer_flags;    /* (in) URB_SHORT_NOT_OK | ...*/
+       void *transfer_buffer;          /* (in) associated data buffer */
+       dma_addr_t transfer_dma;        /* (in) dma addr for transfer_buffer */
++      void *aligned_transfer_buffer;  /* (in) associeated data buffer */
++      dma_addr_t aligned_transfer_dma;/* (in) dma addr for transfer_buffer */
++      u32 aligned_transfer_buffer_length; /* (in) data buffer length */
+       struct scatterlist *sg;         /* (in) scatter gather buffer list */
+       int num_mapped_sgs;             /* (internal) mapped sg entries */
+       int num_sgs;                    /* (in) number of entries in the sg list */
+--- a/drivers/usb/Makefile
++++ b/drivers/usb/Makefile
+@@ -7,6 +7,7 @@
+ obj-$(CONFIG_USB)             += core/
+ obj-$(CONFIG_USB_DWC3)                += dwc3/
++obj-$(CONFIG_USB_DWC_OTG)     += dwc/
+ obj-$(CONFIG_USB_MON)         += mon/
diff --git a/target/linux/cns3xxx/patches-3.10/300-laguna_support.patch b/target/linux/cns3xxx/patches-3.10/300-laguna_support.patch
new file mode 100644 (file)
index 0000000..d2338e2
--- /dev/null
@@ -0,0 +1,46 @@
+--- a/arch/arm/mach-cns3xxx/Kconfig
++++ b/arch/arm/mach-cns3xxx/Kconfig
+@@ -27,4 +27,12 @@ config MACH_CNS3420VB
+         This is a platform with an on-board ARM11 MPCore and has support
+         for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
++config MACH_GW2388
++      bool "Support for Gateworks Laguna Platform"
++      help
++        Include support for the Gateworks Laguna Platform
++
++        This is a platform with an on-board ARM11 MPCore and has support
++        for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc.
++
+ endmenu
+--- a/arch/arm/mach-cns3xxx/Makefile
++++ b/arch/arm/mach-cns3xxx/Makefile
+@@ -7,3 +7,5 @@ cns3xxx-$(CONFIG_PCI)                  += pcie.o
+ cns3xxx-$(CONFIG_MACH_CNS3420VB)      += cns3420vb.o
+ cns3xxx-$(CONFIG_SMP)                 += platsmp.o headsmp.o cns3xxx_fiq.o
+ cns3xxx-$(CONFIG_HOTPLUG_CPU)         += hotplug.o
++cns3xxx-$(CONFIG_MACH_GW2388)         += laguna.o
++
+--- a/arch/arm/mach-cns3xxx/devices.c
++++ b/arch/arm/mach-cns3xxx/devices.c
+@@ -16,6 +16,7 @@
+ #include <linux/compiler.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/platform_device.h>
++#include <asm/mach-types.h>
+ #include "cns3xxx.h"
+ #include "pm.h"
+ #include "core.h"
+@@ -101,7 +102,11 @@ void __init cns3xxx_sdhci_init(void)
+       u32 gpioa_pins = __raw_readl(gpioa);
+       /* MMC/SD pins share with GPIOA */
+-      gpioa_pins |= 0x1fff0004;
++      if (machine_is_gw2388()) {
++              gpioa_pins |= 0x1fff0000;
++      } else {
++              gpioa_pins |= 0x1fff0004;
++      }
+       __raw_writel(gpioa_pins, gpioa);
+       cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
diff --git a/target/linux/cns3xxx/patches-3.10/305-laguna_sdhci_card_detect.patch b/target/linux/cns3xxx/patches-3.10/305-laguna_sdhci_card_detect.patch
new file mode 100644 (file)
index 0000000..2d28785
--- /dev/null
@@ -0,0 +1,16 @@
+--- a/drivers/mmc/host/sdhci-cns3xxx.c
++++ b/drivers/mmc/host/sdhci-cns3xxx.c
+@@ -88,10 +88,11 @@ static const struct sdhci_pltfm_data sdh
+       .ops = &sdhci_cns3xxx_ops,
+       .quirks = SDHCI_QUIRK_BROKEN_DMA |
+                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
+-                SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
++                //SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
+                 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+                 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
+-                SDHCI_QUIRK_NONSTANDARD_CLOCK,
++                SDHCI_QUIRK_NONSTANDARD_CLOCK |
++                SDHCI_QUIRK_BROKEN_CARD_DETECTION,
+ };
+ static int sdhci_cns3xxx_probe(struct platform_device *pdev)
diff --git a/target/linux/cns3xxx/patches-3.8/010-move_virtual_io_space.patch b/target/linux/cns3xxx/patches-3.8/010-move_virtual_io_space.patch
deleted file mode 100644 (file)
index 0d45076..0000000
+++ /dev/null
@@ -1,170 +0,0 @@
---- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
-+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
-@@ -20,22 +20,22 @@
- #define CNS3XXX_SPI_FLASH_BASE                        0x60000000      /* SPI Serial Flash Memory */
- #define CNS3XXX_SWITCH_BASE                   0x70000000      /* Switch and HNAT Control */
--#define CNS3XXX_SWITCH_BASE_VIRT              0xFFF00000
-+#define CNS3XXX_SWITCH_BASE_VIRT              0xFEF00000
- #define CNS3XXX_PPE_BASE                      0x70001000      /* HANT */
--#define CNS3XXX_PPE_BASE_VIRT                 0xFFF50000
-+#define CNS3XXX_PPE_BASE_VIRT                 0xFEF50000
- #define CNS3XXX_EMBEDDED_SRAM_BASE            0x70002000      /* HANT Embedded SRAM */
--#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT               0xFFF60000
-+#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT               0xFEF60000
- #define CNS3XXX_SSP_BASE                      0x71000000      /* Synchronous Serial Port - SPI/PCM/I2C */
--#define CNS3XXX_SSP_BASE_VIRT                 0xFFF01000
-+#define CNS3XXX_SSP_BASE_VIRT                 0xFEF01000
- #define CNS3XXX_DMC_BASE                      0x72000000      /* DMC Control (DDR2 SDRAM) */
--#define CNS3XXX_DMC_BASE_VIRT                 0xFFF02000
-+#define CNS3XXX_DMC_BASE_VIRT                 0xFEF02000
- #define CNS3XXX_SMC_BASE                      0x73000000      /* SMC Control */
--#define CNS3XXX_SMC_BASE_VIRT                 0xFFF03000
-+#define CNS3XXX_SMC_BASE_VIRT                 0xFEF03000
- #define SMC_MEMC_STATUS_OFFSET                        0x000
- #define SMC_MEMIF_CFG_OFFSET                  0x004
-@@ -74,13 +74,13 @@
- #define SMC_PCELL_ID_3_OFFSET                 0xFFC
- #define CNS3XXX_GPIOA_BASE                    0x74000000      /* GPIO port A */
--#define CNS3XXX_GPIOA_BASE_VIRT                       0xFFF04000
-+#define CNS3XXX_GPIOA_BASE_VIRT                       0xFEF04000
- #define CNS3XXX_GPIOB_BASE                    0x74800000      /* GPIO port B */
--#define CNS3XXX_GPIOB_BASE_VIRT                       0xFFF05000
-+#define CNS3XXX_GPIOB_BASE_VIRT                       0xFEF05000
- #define CNS3XXX_RTC_BASE                      0x75000000      /* Real Time Clock */
--#define CNS3XXX_RTC_BASE_VIRT                 0xFFF06000
-+#define CNS3XXX_RTC_BASE_VIRT                 0xFEF06000
- #define RTC_SEC_OFFSET                                0x00
- #define RTC_MIN_OFFSET                                0x04
-@@ -94,10 +94,10 @@
- #define RTC_INTR_STS_OFFSET                   0x34
- #define CNS3XXX_MISC_BASE                     0x76000000      /* Misc Control */
--#define CNS3XXX_MISC_BASE_VIRT                        0xFB000000      /* Misc Control */
-+#define CNS3XXX_MISC_BASE_VIRT                        0xFEF07000      /* Misc Control */
- #define CNS3XXX_PM_BASE                               0x77000000      /* Power Management Control */
--#define CNS3XXX_PM_BASE_VIRT                  0xFB001000
-+#define CNS3XXX_PM_BASE_VIRT                  0xFEF08000
- #define PM_CLK_GATE_OFFSET                    0x00
- #define PM_SOFT_RST_OFFSET                    0x04
-@@ -109,28 +109,28 @@
- #define PM_PLL_HM_PD_OFFSET                   0x1C
- #define CNS3XXX_UART0_BASE                    0x78000000      /* UART 0 */
--#define CNS3XXX_UART0_BASE_VIRT                       0xFB002000
-+#define CNS3XXX_UART0_BASE_VIRT                       0xFEF09000
- #define CNS3XXX_UART1_BASE                    0x78400000      /* UART 1 */
--#define CNS3XXX_UART1_BASE_VIRT                       0xFFF0A000
-+#define CNS3XXX_UART1_BASE_VIRT                       0xFEF0A000
- #define CNS3XXX_UART2_BASE                    0x78800000      /* UART 2 */
--#define CNS3XXX_UART2_BASE_VIRT                       0xFFF0B000
-+#define CNS3XXX_UART2_BASE_VIRT                       0xFEF0B000
- #define CNS3XXX_DMAC_BASE                     0x79000000      /* Generic DMA Control */
--#define CNS3XXX_DMAC_BASE_VIRT                        0xFFF0D000
-+#define CNS3XXX_DMAC_BASE_VIRT                        0xFEF0D000
- #define CNS3XXX_CORESIGHT_BASE                        0x7A000000      /* CoreSight */
--#define CNS3XXX_CORESIGHT_BASE_VIRT           0xFFF0E000
-+#define CNS3XXX_CORESIGHT_BASE_VIRT           0xFEF0E000
- #define CNS3XXX_CRYPTO_BASE                   0x7B000000      /* Crypto */
--#define CNS3XXX_CRYPTO_BASE_VIRT              0xFFF0F000
-+#define CNS3XXX_CRYPTO_BASE_VIRT              0xFEF0F000
- #define CNS3XXX_I2S_BASE                      0x7C000000      /* I2S */
--#define CNS3XXX_I2S_BASE_VIRT                 0xFFF10000
-+#define CNS3XXX_I2S_BASE_VIRT                 0xFEF10000
- #define CNS3XXX_TIMER1_2_3_BASE                       0x7C800000      /* Timer */
--#define CNS3XXX_TIMER1_2_3_BASE_VIRT          0xFB003000
-+#define CNS3XXX_TIMER1_2_3_BASE_VIRT          0xFEF10800
- #define TIMER1_COUNTER_OFFSET                 0x00
- #define TIMER1_AUTO_RELOAD_OFFSET             0x04
-@@ -150,42 +150,42 @@
- #define TIMER_FREERUN_CONTROL_OFFSET          0x44
- #define CNS3XXX_HCIE_BASE                     0x7D000000      /* HCIE Control */
--#define CNS3XXX_HCIE_BASE_VIRT                        0xFFF30000
-+#define CNS3XXX_HCIE_BASE_VIRT                        0xFEF30000
- #define CNS3XXX_RAID_BASE                     0x7E000000      /* RAID Control */
--#define CNS3XXX_RAID_BASE_VIRT                        0xFFF12000
-+#define CNS3XXX_RAID_BASE_VIRT                        0xFEF12000
- #define CNS3XXX_AXI_IXC_BASE                  0x7F000000      /* AXI IXC */
--#define CNS3XXX_AXI_IXC_BASE_VIRT             0xFFF13000
-+#define CNS3XXX_AXI_IXC_BASE_VIRT             0xFEF13000
- #define CNS3XXX_CLCD_BASE                     0x80000000      /* LCD Control */
--#define CNS3XXX_CLCD_BASE_VIRT                        0xFFF14000
-+#define CNS3XXX_CLCD_BASE_VIRT                        0xFEF14000
- #define CNS3XXX_USBOTG_BASE                   0x81000000      /* USB OTG Control */
--#define CNS3XXX_USBOTG_BASE_VIRT              0xFFF15000
-+#define CNS3XXX_USBOTG_BASE_VIRT              0xFEF15000
- #define CNS3XXX_USB_BASE                      0x82000000      /* USB Host Control */
- #define CNS3XXX_SATA2_BASE                    0x83000000      /* SATA */
- #define CNS3XXX_SATA2_SIZE                    SZ_16M
--#define CNS3XXX_SATA2_BASE_VIRT                       0xFFF17000
-+#define CNS3XXX_SATA2_BASE_VIRT                       0xFEF17000
- #define CNS3XXX_CAMERA_BASE                   0x84000000      /* Camera Interface */
--#define CNS3XXX_CAMERA_BASE_VIRT              0xFFF18000
-+#define CNS3XXX_CAMERA_BASE_VIRT              0xFEF18000
- #define CNS3XXX_SDIO_BASE                     0x85000000      /* SDIO */
--#define CNS3XXX_SDIO_BASE_VIRT                        0xFFF19000
-+#define CNS3XXX_SDIO_BASE_VIRT                        0xFEF19000
- #define CNS3XXX_I2S_TDM_BASE                  0x86000000      /* I2S TDM */
--#define CNS3XXX_I2S_TDM_BASE_VIRT             0xFFF1A000
-+#define CNS3XXX_I2S_TDM_BASE_VIRT             0xFEF1A000
- #define CNS3XXX_2DG_BASE                      0x87000000      /* 2D Graphic Control */
--#define CNS3XXX_2DG_BASE_VIRT                 0xFFF1B000
-+#define CNS3XXX_2DG_BASE_VIRT                 0xFEF1B000
- #define CNS3XXX_USB_OHCI_BASE                 0x88000000      /* USB OHCI */
- #define CNS3XXX_L2C_BASE                      0x92000000      /* L2 Cache Control */
--#define CNS3XXX_L2C_BASE_VIRT                 0xFFF27000
-+#define CNS3XXX_L2C_BASE_VIRT                 0xFEF27000
- #define CNS3XXX_PCIE0_MEM_BASE                        0xA0000000      /* PCIe Port 0 IO/Memory Space */
- #define CNS3XXX_PCIE0_MEM_BASE_VIRT           0xE0000000
-@@ -227,7 +227,7 @@
-  * Testchip peripheral and fpga gic regions
-  */
- #define CNS3XXX_TC11MP_SCU_BASE                       0x90000000      /* IRQ, Test chip */
--#define CNS3XXX_TC11MP_SCU_BASE_VIRT          0xFB004000
-+#define CNS3XXX_TC11MP_SCU_BASE_VIRT          0xFEE00000
- #define CNS3XXX_TC11MP_GIC_CPU_BASE           0x90000100      /* Test chip interrupt controller CPU interface */
- #define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT      (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
-@@ -239,7 +239,7 @@
- #define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT     (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
- #define CNS3XXX_TC11MP_L220_BASE              0x92002000      /* L220 registers */
--#define CNS3XXX_TC11MP_L220_BASE_VIRT         0xFF002000
-+#define CNS3XXX_TC11MP_L220_BASE_VIRT         0xFEE02000
- /*
-  * Misc block
diff --git a/target/linux/cns3xxx/patches-3.8/015-clkdev_support.patch b/target/linux/cns3xxx/patches-3.8/015-clkdev_support.patch
deleted file mode 100644 (file)
index 5ffa4cb..0000000
+++ /dev/null
@@ -1,69 +0,0 @@
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -365,6 +365,7 @@ config ARCH_CNS3XXX
-       select MIGHT_HAVE_CACHE_L2X0
-       select MIGHT_HAVE_PCI
-       select PCI_DOMAINS if PCI
-+      select CLKDEV_LOOKUP
-       help
-         Support for Cavium Networks CNS3XXX platform.
---- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -9,8 +9,11 @@
-  */
- #include <linux/init.h>
-+#include <linux/export.h>
- #include <linux/interrupt.h>
- #include <linux/clockchips.h>
-+#include <linux/clk.h>
-+#include <linux/clkdev.h>
- #include <linux/io.h>
- #include <asm/mach/map.h>
- #include <asm/mach/time.h>
-@@ -20,6 +23,10 @@
- #include <mach/cns3xxx.h>
- #include "core.h"
-+struct clk {
-+      unsigned long   rate;
-+};
-+
- static struct map_desc cns3xxx_io_desc[] __initdata = {
-       {
-               .virtual        = CNS3XXX_TC11MP_SCU_BASE_VIRT,
-@@ -277,3 +284,33 @@ void __init cns3xxx_l2x0_init(void)
- }
- #endif /* CONFIG_CACHE_L2X0 */
-+
-+int clk_enable(struct clk *clk)
-+{
-+      return 0;
-+}
-+EXPORT_SYMBOL(clk_enable);
-+
-+void clk_disable(struct clk *clk)
-+{
-+}
-+EXPORT_SYMBOL(clk_disable);
-+
-+unsigned long clk_get_rate(struct clk *clk)
-+{
-+      return clk->rate;
-+}
-+EXPORT_SYMBOL(clk_get_rate);
-+
-+static struct clk_lookup cns3xxx_clocks[] = {
-+      {
-+              /* TODO */
-+      },
-+};
-+
-+int __init cns3xxx_clocks_init(void)
-+{
-+      clkdev_add_table(cns3xxx_clocks, ARRAY_SIZE(cns3xxx_clocks));
-+      return 0;
-+}
-+postcore_initcall(cns3xxx_clocks_init);
diff --git a/target/linux/cns3xxx/patches-3.8/020-watchdog_support.patch b/target/linux/cns3xxx/patches-3.8/020-watchdog_support.patch
deleted file mode 100644 (file)
index 171e1f6..0000000
+++ /dev/null
@@ -1,59 +0,0 @@
-1. Made the connection between CNS3xxx SOCs(ARCH_CNS3xxx) and MPcore watchdog
-   since the CNS3xxx SOCs have ARM11 MPcore CPU.
-2. Enable mpcore_watchdog option as module to default configuration at
-   arch/arm/configs/cns3420vb_defconfig.
-
-Signed-off-by: Tommy Lin <tommy.lin@caviumnetworks.com>
-
----
-arch/arm/Kconfig                     |    1 +
- arch/arm/configs/cns3420vb_defconfig |    2 ++
- arch/arm/mach-cns3xxx/cns3420vb.c    |   22 ++++++++++++++++++++++
- 3 files changed, 25 insertions(+), 0 deletions(-)
-
---- a/arch/arm/configs/cns3420vb_defconfig
-+++ b/arch/arm/configs/cns3420vb_defconfig
-@@ -53,6 +53,8 @@ CONFIG_LEGACY_PTY_COUNT=16
- # CONFIG_HW_RANDOM is not set
- # CONFIG_HWMON is not set
- # CONFIG_VGA_CONSOLE is not set
-+CONFIG_WATCHDOG=y
-+CONFIG_MPCORE_WATCHDOG=m
- # CONFIG_HID_SUPPORT is not set
- # CONFIG_USB_SUPPORT is not set
- CONFIG_MMC=y
---- a/arch/arm/mach-cns3xxx/cns3420vb.c
-+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
-@@ -208,10 +208,32 @@ static struct platform_device cns3xxx_us
-       },
- };
-+/* Watchdog */
-+static struct resource cns3xxx_watchdog_resources[] = {
-+      [0] = {
-+              .start = CNS3XXX_TC11MP_TWD_BASE,
-+              .end   = CNS3XXX_TC11MP_TWD_BASE + PAGE_SIZE - 1,
-+              .flags = IORESOURCE_MEM,
-+      },
-+      [1] = {
-+              .start = IRQ_LOCALWDOG,
-+              .end   = IRQ_LOCALWDOG,
-+              .flags = IORESOURCE_IRQ,
-+      }
-+};
-+
-+static struct platform_device cns3xxx_watchdog_device = {
-+      .name           = "mpcore_wdt",
-+      .id             = -1,
-+      .num_resources  = ARRAY_SIZE(cns3xxx_watchdog_resources),
-+      .resource       = cns3xxx_watchdog_resources,
-+};
-+
- /*
-  * Initialization
-  */
- static struct platform_device *cns3420_pdevs[] __initdata = {
-+      &cns3xxx_watchdog_device,
-       &cns3420_nor_pdev,
-       &cns3xxx_usb_ehci_device,
-       &cns3xxx_usb_ohci_device,
diff --git a/target/linux/cns3xxx/patches-3.8/021-cache_force_multi.patch b/target/linux/cns3xxx/patches-3.8/021-cache_force_multi.patch
deleted file mode 100644 (file)
index 536d9ca..0000000
+++ /dev/null
@@ -1,35 +0,0 @@
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -366,6 +366,7 @@ config ARCH_CNS3XXX
-       select MIGHT_HAVE_PCI
-       select PCI_DOMAINS if PCI
-       select CLKDEV_LOOKUP
-+      select CPU_CACHE_FORCE_MULTI
-       help
-         Support for Cavium Networks CNS3XXX platform.
---- a/arch/arm/mm/Kconfig
-+++ b/arch/arm/mm/Kconfig
-@@ -496,6 +496,9 @@ config CPU_CACHE_VIPT
- config CPU_CACHE_FA
-       bool
-+config CPU_CACHE_FORCE_MULTI
-+      bool
-+
- if MMU
- # The copy-page model
- config CPU_COPY_V4WT
---- a/arch/arm/include/asm/glue-cache.h
-+++ b/arch/arm/include/asm/glue-cache.h
-@@ -129,6 +129,10 @@
- #error Unknown cache maintenance model
- #endif
-+#if defined(CONFIG_CPU_CACHE_FORCE_MULTI) && !defined(MULTI_CACHE)
-+#define MULTI_CACHE 1
-+#endif
-+
- #ifndef MULTI_CACHE
- #define __cpuc_flush_icache_all               __glue(_CACHE,_flush_icache_all)
- #define __cpuc_flush_kern_all         __glue(_CACHE,_flush_kern_cache_all)
diff --git a/target/linux/cns3xxx/patches-3.8/025-smp_support.patch b/target/linux/cns3xxx/patches-3.8/025-smp_support.patch
deleted file mode 100644 (file)
index 82b1ce6..0000000
+++ /dev/null
@@ -1,38 +0,0 @@
---- a/arch/arm/mach-cns3xxx/Makefile
-+++ b/arch/arm/mach-cns3xxx/Makefile
-@@ -1,3 +1,5 @@
- obj-$(CONFIG_ARCH_CNS3XXX)            += core.o pm.o devices.o
- obj-$(CONFIG_PCI)                     += pcie.o
- obj-$(CONFIG_MACH_CNS3420VB)          += cns3420vb.o
-+obj-$(CONFIG_SMP)                     += platsmp.o headsmp.o
-+obj-$(CONFIG_HOTPLUG_CPU)             += hotplug.o
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -367,6 +367,7 @@ config ARCH_CNS3XXX
-       select PCI_DOMAINS if PCI
-       select CLKDEV_LOOKUP
-       select CPU_CACHE_FORCE_MULTI
-+      select HAVE_SMP
-       help
-         Support for Cavium Networks CNS3XXX platform.
---- a/arch/arm/mach-cns3xxx/core.h
-+++ b/arch/arm/mach-cns3xxx/core.h
-@@ -11,6 +11,7 @@
- #ifndef __CNS3XXX_CORE_H
- #define __CNS3XXX_CORE_H
-+extern struct smp_operations cns3xxx_smp_ops;
- extern struct sys_timer cns3xxx_timer;
- #ifdef CONFIG_CACHE_L2X0
---- a/arch/arm/mach-cns3xxx/laguna.c
-+++ b/arch/arm/mach-cns3xxx/laguna.c
-@@ -989,6 +989,7 @@ static int __init laguna_model_setup(voi
- late_initcall(laguna_model_setup);
- MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
-+      .smp            = smp_ops(cns3xxx_smp_ops),
-       .atag_offset    = 0x100,
-       .map_io         = laguna_map_io,
-       .init_irq       = cns3xxx_init_irq,
diff --git a/target/linux/cns3xxx/patches-3.8/030-pcie_clock.patch b/target/linux/cns3xxx/patches-3.8/030-pcie_clock.patch
deleted file mode 100644 (file)
index 3734daf..0000000
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm/mach-cns3xxx/pcie.c
-+++ b/arch/arm/mach-cns3xxx/pcie.c
-@@ -370,8 +370,6 @@ static int __init cns3xxx_pcie_init(void
-       for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
-               iotable_init(cns3xxx_pcie[i].cfg_bases,
-                            ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
--              cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
--              cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
-               cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
-               cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
-               pci_common_init(&cns3xxx_pcie[i].hw_pci);
diff --git a/target/linux/cns3xxx/patches-3.8/035-add_io_spaces.patch b/target/linux/cns3xxx/patches-3.8/035-add_io_spaces.patch
deleted file mode 100644 (file)
index b4b018b..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
---- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -58,6 +58,16 @@ static struct map_desc cns3xxx_io_desc[]
-               .pfn            = __phys_to_pfn(CNS3XXX_PM_BASE),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-+      }, {
-+              .virtual        = CNS3XXX_SWITCH_BASE_VIRT,
-+              .pfn            = __phys_to_pfn(CNS3XXX_SWITCH_BASE),
-+              .length         = SZ_4K,
-+              .type           = MT_DEVICE,
-+      }, {
-+              .virtual        = CNS3XXX_SSP_BASE_VIRT,
-+              .pfn            = __phys_to_pfn(CNS3XXX_SSP_BASE),
-+              .length         = SZ_4K,
-+              .type           = MT_DEVICE,
-       },
- };
diff --git a/target/linux/cns3xxx/patches-3.8/040-fiq_support.patch b/target/linux/cns3xxx/patches-3.8/040-fiq_support.patch
deleted file mode 100644 (file)
index 9c662a5..0000000
+++ /dev/null
@@ -1,77 +0,0 @@
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -368,6 +368,7 @@ config ARCH_CNS3XXX
-       select CLKDEV_LOOKUP
-       select CPU_CACHE_FORCE_MULTI
-       select HAVE_SMP
-+      select FIQ
-       help
-         Support for Cavium Networks CNS3XXX platform.
---- a/arch/arm/kernel/fiq.c
-+++ b/arch/arm/kernel/fiq.c
-@@ -49,6 +49,8 @@
- static unsigned long no_fiq_insn;
-+unsigned int fiq_number[2] = {0, 0};
-+
- /* Default reacquire function
-  * - we always relinquish FIQ control
-  * - we always reacquire FIQ control
-@@ -70,9 +72,12 @@ static struct fiq_handler *current_fiq =
- int show_fiq_list(struct seq_file *p, int prec)
- {
--      if (current_fiq != &default_owner)
--              seq_printf(p, "%*s:              %s\n", prec, "FIQ",
--                      current_fiq->name);
-+      if (current_fiq != &default_owner) {
-+              seq_printf(p, "%*s: ", prec, "FIQ");
-+              seq_printf(p, "%10u ", fiq_number[0]);
-+              seq_printf(p, "%10u ", fiq_number[1]);
-+              seq_printf(p, "      %s\n", current_fiq->name);
-+      }
-       return 0;
- }
---- a/arch/arm/mach-cns3xxx/Makefile
-+++ b/arch/arm/mach-cns3xxx/Makefile
-@@ -1,5 +1,5 @@
- obj-$(CONFIG_ARCH_CNS3XXX)            += core.o pm.o devices.o
- obj-$(CONFIG_PCI)                     += pcie.o
- obj-$(CONFIG_MACH_CNS3420VB)          += cns3420vb.o
--obj-$(CONFIG_SMP)                     += platsmp.o headsmp.o
-+obj-$(CONFIG_SMP)                     += platsmp.o headsmp.o cns3xxx_fiq.o
- obj-$(CONFIG_HOTPLUG_CPU)             += hotplug.o
---- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
-+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
-@@ -294,6 +294,7 @@
- #define MISC_PCIE_INT_MASK(x)                 MISC_MEM_MAP(0x978 + (x) * 0x100)
- #define MISC_PCIE_INT_STATUS(x)                       MISC_MEM_MAP(0x97C + (x) * 0x100)
-+#define MISC_FIQ_CPU(x)                               MISC_MEM_MAP(0xA58 - (x) * 0x4)
- /*
-  * Power management and clock control
-  */
---- a/arch/arm/mach-cns3xxx/include/mach/irqs.h
-+++ b/arch/arm/mach-cns3xxx/include/mach/irqs.h
-@@ -14,6 +14,7 @@
- #define IRQ_LOCALTIMER                29
- #define IRQ_LOCALWDOG         30
- #define IRQ_TC11MP_GIC_START  32
-+#define FIQ_START 0
- #include <mach/cns3xxx.h>
---- a/arch/arm/mm/Kconfig
-+++ b/arch/arm/mm/Kconfig
-@@ -773,7 +773,7 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
- config DMA_CACHE_RWFO
-       bool "Enable read/write for ownership DMA cache maintenance"
--      depends on CPU_V6K && SMP
-+      depends on CPU_V6K && SMP && !ARCH_CNS3XXX
-       default y
-       help
-         The Snoop Control Unit on ARM11MPCore does not detect the
diff --git a/target/linux/cns3xxx/patches-3.8/045-twd_base.patch b/target/linux/cns3xxx/patches-3.8/045-twd_base.patch
deleted file mode 100644 (file)
index a9ad3ec..0000000
+++ /dev/null
@@ -1,36 +0,0 @@
---- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -19,6 +19,7 @@
- #include <asm/mach/time.h>
- #include <asm/mach/irq.h>
- #include <asm/hardware/gic.h>
-+#include <asm/smp_twd.h>
- #include <asm/hardware/cache-l2x0.h>
- #include <mach/cns3xxx.h>
- #include "core.h"
-@@ -187,6 +188,17 @@ static struct irqaction cns3xxx_timer_ir
-       .handler        = cns3xxx_timer_interrupt,
- };
-+static void __init cns3xxx_init_twd(void)
-+{
-+#ifdef CONFIG_LOCAL_TIMERS
-+      static DEFINE_TWD_LOCAL_TIMER(cns3xx_twd_local_timer,
-+              CNS3XXX_TC11MP_TWD_BASE,
-+              IRQ_LOCALTIMER);
-+
-+      twd_local_timer_register(&cns3xx_twd_local_timer);
-+#endif
-+}
-+
- /*
-  * Set up the clock source and clock events devices
-  */
-@@ -240,6 +252,7 @@ static void __init __cns3xxx_timer_init(
-       setup_irq(timer_irq, &cns3xxx_timer_irq);
-       cns3xxx_clockevents_init(timer_irq);
-+      cns3xxx_init_twd();
- }
- static void __init cns3xxx_timer_init(void)
diff --git a/target/linux/cns3xxx/patches-3.8/055-pcie_io.patch b/target/linux/cns3xxx/patches-3.8/055-pcie_io.patch
deleted file mode 100644 (file)
index 08a68f9..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
---- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -69,6 +69,16 @@ static struct map_desc cns3xxx_io_desc[]
-               .pfn            = __phys_to_pfn(CNS3XXX_SSP_BASE),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-+      }, {
-+              .virtual        = CNS3XXX_PCIE0_IO_BASE_VIRT,
-+              .pfn            = __phys_to_pfn(CNS3XXX_PCIE0_IO_BASE),
-+              .length         = SZ_16M,
-+              .type           = MT_DEVICE,
-+      }, {
-+              .virtual        = CNS3XXX_PCIE1_IO_BASE_VIRT,
-+              .pfn            = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE),
-+              .length         = SZ_16M,
-+              .type           = MT_DEVICE,
-       },
- };
diff --git a/target/linux/cns3xxx/patches-3.8/060-pcie_abort.patch b/target/linux/cns3xxx/patches-3.8/060-pcie_abort.patch
deleted file mode 100644 (file)
index e1edf05..0000000
+++ /dev/null
@@ -1,129 +0,0 @@
---- a/arch/arm/mach-cns3xxx/pcie.c
-+++ b/arch/arm/mach-cns3xxx/pcie.c
-@@ -92,6 +92,79 @@ static void __iomem *cns3xxx_pci_cfg_bas
-       return base + offset;
- }
-+static inline int check_master_abort(struct pci_bus *bus, unsigned int devfn, int where)
-+{
-+      struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
-+
-+  /* check PCI-compatible status register after access */
-+      if (cnspci->linked) {
-+              void __iomem *host_base;
-+              u32 sreg, ereg;
-+
-+              host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual;
-+              sreg = __raw_readw(host_base + 0x6) & 0xF900;
-+              ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg
-+
-+              if (sreg | ereg) {
-+                      /* SREG:
-+                       *  BIT15 - Detected Parity Error
-+                       *  BIT14 - Signaled System Error
-+                       *  BIT13 - Received Master Abort
-+                       *  BIT12 - Received Target Abort
-+                       *  BIT11 - Signaled Target Abort
-+                       *  BIT08 - Master Data Parity Error
-+                       *
-+                       * EREG:
-+                       *  BIT20 - Unsupported Request
-+                       *  BIT19 - ECRC
-+                       *  BIT18 - Malformed TLP
-+                       *  BIT17 - Receiver Overflow
-+                       *  BIT16 - Unexpected Completion
-+                       *  BIT15 - Completer Abort
-+                       *  BIT14 - Completion Timeout
-+                       *  BIT13 - Flow Control Protocol Error
-+                       *  BIT12 - Poisoned TLP
-+                       *  BIT04 - Data Link Protocol Error
-+                       *
-+                       * TODO: see Documentation/pci-error-recovery.txt
-+                       *    implement error_detected handler
-+                       */
-+/*
-+                      printk("pci error: %04d:%02x:%02x.%02x sreg=0x%04x ereg=0x%08x", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), sreg, ereg);
-+                      if (sreg & BIT(15)) printk(" <PERR");
-+                      if (sreg & BIT(14)) printk(" >SERR");
-+                      if (sreg & BIT(13)) printk(" <MABRT");
-+                      if (sreg & BIT(12)) printk(" <TABRT");
-+                      if (sreg & BIT(11)) printk(" >TABRT");
-+                      if (sreg & BIT( 8)) printk(" MPERR");
-+
-+                      if (ereg & BIT(20)) printk(" Unsup");
-+                      if (ereg & BIT(19)) printk(" ECRC");
-+                      if (ereg & BIT(18)) printk(" MTLP");
-+                      if (ereg & BIT(17)) printk(" OFLOW");
-+                      if (ereg & BIT(16)) printk(" Unex");
-+                      if (ereg & BIT(15)) printk(" ABRT");
-+                      if (ereg & BIT(14)) printk(" COMPTO");
-+                      if (ereg & BIT(13)) printk(" FLOW");
-+                      if (ereg & BIT(12)) printk(" PTLP");
-+                      if (ereg & BIT( 4)) printk(" DLINK");
-+                      printk("\n");
-+*/
-+                      pr_debug("%s failed port%d sreg=0x%04x\n", __func__,
-+                              cnspci->hw_pci.domain, sreg);
-+
-+                      /* make sure the status bits are reset */
-+                      __raw_writew(sreg, host_base + 6);
-+                      __raw_writel(ereg, host_base + 0x104);
-+                      return 1;
-+              }
-+      }
-+      else
-+              return 1;
-+
-+  return 0;
-+}
-+
- static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
-                                  int where, int size, u32 *val)
- {
-@@ -108,6 +181,11 @@ static int cns3xxx_pci_read_config(struc
-       v = __raw_readl(base);
-+      if (check_master_abort(bus, devfn, where)) {
-+              printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)= master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
-+              return PCIBIOS_DEVICE_NOT_FOUND;
-+      }
-+
-       if (bus->number == 0 && devfn == 0 &&
-                       (where & 0xffc) == PCI_CLASS_REVISION) {
-               /*
-@@ -137,11 +215,19 @@ static int cns3xxx_pci_write_config(stru
-               return PCIBIOS_SUCCESSFUL;
-       v = __raw_readl(base);
-+      if (check_master_abort(bus, devfn, where)) {
-+              printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)=0x%08x master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
-+              return PCIBIOS_DEVICE_NOT_FOUND;
-+      }
-       v &= ~(mask << shift);
-       v |= (val & mask) << shift;
-       __raw_writel(v, base);
-+      if (check_master_abort(bus, devfn, where)) {
-+              printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)=0x%08x master_abort on write\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
-+              return PCIBIOS_DEVICE_NOT_FOUND;
-+      }
-       return PCIBIOS_SUCCESSFUL;
- }
-@@ -352,8 +438,14 @@ static void __init cns3xxx_pcie_hw_init(
- static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
-                                     struct pt_regs *regs)
- {
-+#if 0
-+/* R14_ABORT = PC+4 for XSCALE but not ARM11MPCORE
-+ * ignore imprecise aborts and use PCI-compatible Status register to
-+ * determine errors instead
-+ */
-       if (fsr & (1 << 10))
-               regs->ARM_pc += 4;
-+#endif
-       return 0;
- }
diff --git a/target/linux/cns3xxx/patches-3.8/065-pcie_early_init.patch b/target/linux/cns3xxx/patches-3.8/065-pcie_early_init.patch
deleted file mode 100644 (file)
index 36e4981..0000000
+++ /dev/null
@@ -1,85 +0,0 @@
---- a/arch/arm/mach-cns3xxx/cns3420vb.c
-+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
-@@ -263,11 +263,21 @@ static struct map_desc cns3420_io_desc[]
- static void __init cns3420_map_io(void)
- {
-       cns3xxx_map_io();
-+      cns3xxx_pcie_iotable_init();
-       iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
-       cns3420_early_serial_setup();
- }
-+static int __init cns3420vb_pcie_init(void)
-+{
-+      if (!machine_is_cns3420vb())
-+              return 0;
-+
-+      return cns3xxx_pcie_init();
-+}
-+subsys_initcall(cns3420vb_pcie_init);
-+
- MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
-       .atag_offset    = 0x100,
-       .map_io         = cns3420_map_io,
---- a/arch/arm/mach-cns3xxx/core.h
-+++ b/arch/arm/mach-cns3xxx/core.h
-@@ -13,6 +13,8 @@
- extern struct smp_operations cns3xxx_smp_ops;
- extern struct sys_timer cns3xxx_timer;
-+extern void cns3xxx_pcie_iotable_init(void);
-+
- #ifdef CONFIG_CACHE_L2X0
- void __init cns3xxx_l2x0_init(void);
-@@ -22,6 +24,7 @@ static inline void cns3xxx_l2x0_init(voi
- void __init cns3xxx_map_io(void);
- void __init cns3xxx_init_irq(void);
-+int  __init cns3xxx_pcie_init(void);
- void cns3xxx_power_off(void);
- void cns3xxx_restart(char, const char *);
---- a/arch/arm/mach-cns3xxx/pcie.c
-+++ b/arch/arm/mach-cns3xxx/pcie.c
-@@ -449,7 +449,18 @@ static int cns3xxx_pcie_abort_handler(un
-       return 0;
- }
--static int __init cns3xxx_pcie_init(void)
-+
-+void __init cns3xxx_pcie_iotable_init()
-+{
-+      int i;
-+
-+      for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
-+              iotable_init(cns3xxx_pcie[i].cfg_bases,
-+                           ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
-+      }
-+}
-+
-+int __init cns3xxx_pcie_init(void)
- {
-       int i;
-@@ -460,15 +471,14 @@ static int __init cns3xxx_pcie_init(void
-                       "imprecise external abort");
-       for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
--              iotable_init(cns3xxx_pcie[i].cfg_bases,
--                           ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
-               cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
--              cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
--              pci_common_init(&cns3xxx_pcie[i].hw_pci);
-+              if (cns3xxx_pcie[i].linked) {
-+                      cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
-+                      pci_common_init(&cns3xxx_pcie[i].hw_pci);
-+              }
-       }
-       pci_assign_unassigned_resources();
-       return 0;
- }
--device_initcall(cns3xxx_pcie_init);
diff --git a/target/linux/cns3xxx/patches-3.8/070-i2c_support.patch b/target/linux/cns3xxx/patches-3.8/070-i2c_support.patch
deleted file mode 100644 (file)
index bdb19d6..0000000
+++ /dev/null
@@ -1,31 +0,0 @@
---- a/drivers/i2c/busses/Kconfig
-+++ b/drivers/i2c/busses/Kconfig
-@@ -347,6 +347,18 @@ config I2C_CBUS_GPIO
-         This driver can also be built as a module.  If so, the module
-         will be called i2c-cbus-gpio.
-+config I2C_CNS3XXX
-+      tristate "Cavium CNS3xxx I2C driver"
-+      depends on ARCH_CNS3XXX
-+      help
-+        Support for Cavium CNS3xxx I2C controller driver.
-+
-+        This driver can also be built as a module.  If so, the module
-+        will be called i2c-cns3xxx.
-+
-+        Please note that this driver might be needed to bring up other
-+        devices such as Cavium CNS3xxx Ethernet.
-+
- config I2C_CPM
-       tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)"
-       depends on (CPM1 || CPM2) && OF_I2C
---- a/drivers/i2c/busses/Makefile
-+++ b/drivers/i2c/busses/Makefile
-@@ -87,6 +87,7 @@ obj-$(CONFIG_I2C_ACORN)              += i2c-acorn.o
- obj-$(CONFIG_I2C_ELEKTOR)     += i2c-elektor.o
- obj-$(CONFIG_I2C_PCA_ISA)     += i2c-pca-isa.o
- obj-$(CONFIG_I2C_SIBYTE)      += i2c-sibyte.o
-+obj-$(CONFIG_I2C_CNS3XXX)     += i2c-cns3xxx.o
- obj-$(CONFIG_SCx200_ACB)      += scx200_acb.o
- obj-$(CONFIG_SCx200_I2C)      += scx200_i2c.o
diff --git a/target/linux/cns3xxx/patches-3.8/075-spi_support.patch b/target/linux/cns3xxx/patches-3.8/075-spi_support.patch
deleted file mode 100644 (file)
index 1106472..0000000
+++ /dev/null
@@ -1,57 +0,0 @@
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -130,6 +130,13 @@ config SPI_CLPS711X
-         This enables dedicated general purpose SPI/Microwire1-compatible
-         master mode interface (SSI1) for CLPS711X-based CPUs.
-+config SPI_CNS3XXX
-+      tristate "CNS3XXX SPI controller"
-+      depends on ARCH_CNS3XXX && SPI_MASTER
-+      select SPI_BITBANG
-+      help
-+        This enables using the CNS3XXX SPI controller in master mode.
-+
- config SPI_COLDFIRE_QSPI
-       tristate "Freescale Coldfire QSPI controller"
-       depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x)
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -19,6 +19,7 @@ obj-$(CONFIG_SPI_BFIN5XX)            += spi-bfin5x
- obj-$(CONFIG_SPI_BFIN_SPORT)          += spi-bfin-sport.o
- obj-$(CONFIG_SPI_BITBANG)             += spi-bitbang.o
- obj-$(CONFIG_SPI_BUTTERFLY)           += spi-butterfly.o
-+obj-$(CONFIG_SPI_CNS3XXX)             += spi-cns3xxx.o
- obj-$(CONFIG_SPI_CLPS711X)            += spi-clps711x.o
- obj-$(CONFIG_SPI_COLDFIRE_QSPI)               += spi-coldfire-qspi.o
- obj-$(CONFIG_SPI_DAVINCI)             += spi-davinci.o
---- a/drivers/spi/spi-bitbang.c
-+++ b/drivers/spi/spi-bitbang.c
-@@ -328,6 +328,12 @@ static void bitbang_work(struct work_str
-                                */
-                               if (!m->is_dma_mapped)
-                                       t->rx_dma = t->tx_dma = 0;
-+
-+                              if (t->transfer_list.next == &m->transfers)
-+                                      t->last_in_message_list = 1;
-+                              else
-+                                      t->last_in_message_list = 0;
-+
-                               status = bitbang->txrx_bufs(spi, t);
-                       }
-                       if (status > 0)
---- a/include/linux/spi/spi.h
-+++ b/include/linux/spi/spi.h
-@@ -511,6 +511,13 @@ struct spi_transfer {
-       u32             speed_hz;
-       struct list_head transfer_list;
-+
-+#ifdef CONFIG_ARCH_CNS3XXX
-+      unsigned        last_in_message_list;
-+#ifdef CONFIG_SPI_CNS3XXX_2IOREAD
-+      u8      dio_read;
-+#endif
-+#endif
- };
- /**
diff --git a/target/linux/cns3xxx/patches-3.8/080-sata_support.patch b/target/linux/cns3xxx/patches-3.8/080-sata_support.patch
deleted file mode 100644 (file)
index a4feb2c..0000000
+++ /dev/null
@@ -1,44 +0,0 @@
---- a/arch/arm/mach-cns3xxx/devices.c
-+++ b/arch/arm/mach-cns3xxx/devices.c
-@@ -41,7 +41,7 @@ static struct resource cns3xxx_ahci_reso
- static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
- static struct platform_device cns3xxx_ahci_pdev = {
--      .name           = "ahci",
-+      .name           = "cns3xxx-ahci",
-       .id             = 0,
-       .resource       = cns3xxx_ahci_resource,
-       .num_resources  = ARRAY_SIZE(cns3xxx_ahci_resource),
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -31,6 +31,7 @@ enum ahci_type {
-       AHCI,           /* standard platform ahci */
-       IMX53_AHCI,     /* ahci on i.mx53 */
-       STRICT_AHCI,    /* delayed DMA engine start */
-+      CNS3XXX_AHCI,   /* AHCI on cns3xxx */
- };
- static struct platform_device_id ahci_devtype[] = {
-@@ -44,6 +45,9 @@ static struct platform_device_id ahci_de
-               .name = "strict-ahci",
-               .driver_data = STRICT_AHCI,
-       }, {
-+              .name = "cns3xxx-ahci",
-+              .driver_data = CNS3XXX_AHCI,
-+      }, {
-               /* sentinel */
-       }
- };
-@@ -80,6 +84,12 @@ static const struct ata_port_info ahci_p
-               .udma_mask      = ATA_UDMA6,
-               .port_ops       = &ahci_platform_ops,
-       },
-+      [CNS3XXX_AHCI] = {
-+              .flags          = AHCI_FLAG_COMMON,
-+              .pio_mask       = ATA_PIO4,
-+              .udma_mask      = ATA_UDMA6,
-+              .port_ops       = &ahci_platform_retry_srst_ops,
-+      }
- };
- static struct scsi_host_template ahci_platform_sht = {
diff --git a/target/linux/cns3xxx/patches-3.8/085-ethernet_support.patch b/target/linux/cns3xxx/patches-3.8/085-ethernet_support.patch
deleted file mode 100644 (file)
index 84548a3..0000000
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/drivers/net/ethernet/Kconfig
-+++ b/drivers/net/ethernet/Kconfig
-@@ -32,6 +32,7 @@ source "drivers/net/ethernet/calxeda/Kco
- source "drivers/net/ethernet/chelsio/Kconfig"
- source "drivers/net/ethernet/cirrus/Kconfig"
- source "drivers/net/ethernet/cisco/Kconfig"
-+source "drivers/net/ethernet/cavium/Kconfig"
- source "drivers/net/ethernet/davicom/Kconfig"
- config DNET
---- a/drivers/net/ethernet/Makefile
-+++ b/drivers/net/ethernet/Makefile
-@@ -15,6 +15,7 @@ obj-$(CONFIG_NET_BFIN) += adi/
- obj-$(CONFIG_NET_VENDOR_BROADCOM) += broadcom/
- obj-$(CONFIG_NET_VENDOR_BROCADE) += brocade/
- obj-$(CONFIG_NET_CALXEDA_XGMAC) += calxeda/
-+obj-$(CONFIG_NET_VENDOR_CAVIUM) += cavium/
- obj-$(CONFIG_NET_VENDOR_CHELSIO) += chelsio/
- obj-$(CONFIG_NET_VENDOR_CIRRUS) += cirrus/
- obj-$(CONFIG_NET_VENDOR_CISCO) += cisco/
diff --git a/target/linux/cns3xxx/patches-3.8/090-timers.patch b/target/linux/cns3xxx/patches-3.8/090-timers.patch
deleted file mode 100644 (file)
index 1750e80..0000000
+++ /dev/null
@@ -1,109 +0,0 @@
---- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -122,12 +122,13 @@ static void cns3xxx_timer_set_mode(enum
-       switch (mode) {
-       case CLOCK_EVT_MODE_PERIODIC:
--              reload = pclk * 20 / (3 * HZ) * 0x25000;
-+              reload = pclk * 1000000 / HZ;
-               writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
-               ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
-               break;
-       case CLOCK_EVT_MODE_ONESHOT:
-               /* period set, and timer enabled in 'next_event' hook */
-+              writel(0, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
-               ctrl |= (1 << 2) | (1 << 9);
-               break;
-       case CLOCK_EVT_MODE_UNUSED:
-@@ -152,11 +153,11 @@ static int cns3xxx_timer_set_next_event(
- static struct clock_event_device cns3xxx_tmr1_clockevent = {
-       .name           = "cns3xxx timer1",
--      .shift          = 8,
-+      .shift          = 32,
-       .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-       .set_mode       = cns3xxx_timer_set_mode,
-       .set_next_event = cns3xxx_timer_set_next_event,
--      .rating         = 350,
-+      .rating         = 300,
-       .cpumask        = cpu_all_mask,
- };
-@@ -209,6 +210,35 @@ static void __init cns3xxx_init_twd(void
- #endif
- }
-+static cycle_t cns3xxx_get_cycles(struct clocksource *cs)
-+{
-+  u64 val;
-+
-+  val = readl(cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
-+  val &= 0xffff;
-+
-+  return ((val << 32) | readl(cns3xxx_tmr1 + TIMER_FREERUN_OFFSET));
-+}
-+
-+static struct clocksource clocksource_cns3xxx = {
-+      .name = "freerun",
-+      .rating = 200,
-+      .read = cns3xxx_get_cycles,
-+      .mask = CLOCKSOURCE_MASK(48),
-+      .shift  = 16,
-+      .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
-+};
-+
-+static void __init cns3xxx_clocksource_init(void)
-+{
-+      /* Reset the FreeRunning counter */
-+      writel((1 << 16), cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
-+
-+      clocksource_cns3xxx.mult =
-+              clocksource_khz2mult(100, clocksource_cns3xxx.shift);
-+      clocksource_register(&clocksource_cns3xxx);
-+}
-+
- /*
-  * Set up the clock source and clock events devices
-  */
-@@ -226,13 +256,12 @@ static void __init __cns3xxx_timer_init(
-       /* stop free running timer3 */
-       writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
--      /* timer1 */
--      writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
--      writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
--
-       writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
-       writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
-+      val = (cns3xxx_cpu_clock() >> 3) * 1000000 / HZ;
-+      writel(val, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
-+
-       /* mask irq, non-mask timer1 overflow */
-       irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
-       irq_mask &= ~(1 << 2);
-@@ -244,23 +273,9 @@ static void __init __cns3xxx_timer_init(
-       val |= (1 << 9);
-       writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
--      /* timer2 */
--      writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
--      writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
--
--      /* mask irq */
--      irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
--      irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
--      writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
--
--      /* down counter */
--      val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
--      val |= (1 << 10);
--      writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
--
--      /* Make irqs happen for the system timer */
-       setup_irq(timer_irq, &cns3xxx_timer_irq);
-+      cns3xxx_clocksource_init();
-       cns3xxx_clockevents_init(timer_irq);
-       cns3xxx_init_twd();
- }
diff --git a/target/linux/cns3xxx/patches-3.8/095-gpio_support.patch b/target/linux/cns3xxx/patches-3.8/095-gpio_support.patch
deleted file mode 100644 (file)
index 8f8f261..0000000
+++ /dev/null
@@ -1,74 +0,0 @@
---- a/arch/arm/mach-cns3xxx/cns3420vb.c
-+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
-@@ -247,6 +247,10 @@ static void __init cns3420_init(void)
-       cns3xxx_ahci_init();
-       cns3xxx_sdhci_init();
-+      cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
-+              NR_IRQS_CNS3XXX);
-+      cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
-+              NR_IRQS_CNS3XXX + 32);
-       pm_power_off = cns3xxx_power_off;
- }
-@@ -262,7 +266,7 @@ static struct map_desc cns3420_io_desc[]
- static void __init cns3420_map_io(void)
- {
--      cns3xxx_map_io();
-+      cns3xxx_common_init();
-       cns3xxx_pcie_iotable_init();
-       iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
---- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -82,7 +82,7 @@ static struct map_desc cns3xxx_io_desc[]
-       },
- };
--void __init cns3xxx_map_io(void)
-+void __init cns3xxx_common_init(void)
- {
-       iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
- }
---- a/arch/arm/mach-cns3xxx/core.h
-+++ b/arch/arm/mach-cns3xxx/core.h
-@@ -22,7 +22,7 @@ void __init cns3xxx_l2x0_init(void);
- static inline void cns3xxx_l2x0_init(void) {}
- #endif /* CONFIG_CACHE_L2X0 */
--void __init cns3xxx_map_io(void);
-+void __init cns3xxx_common_init(void);
- void __init cns3xxx_init_irq(void);
- int  __init cns3xxx_pcie_init(void);
- void cns3xxx_power_off(void);
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -361,6 +361,8 @@ config ARCH_CNS3XXX
-       bool "Cavium Networks CNS3XXX family"
-       select ARM_GIC
-       select CPU_V6K
-+      select ARCH_REQUIRE_GPIOLIB
-+      select GENERIC_IRQ_CHIP
-       select GENERIC_CLOCKEVENTS
-       select MIGHT_HAVE_CACHE_L2X0
-       select MIGHT_HAVE_PCI
---- a/arch/arm/mach-cns3xxx/Makefile
-+++ b/arch/arm/mach-cns3xxx/Makefile
-@@ -1,4 +1,4 @@
--obj-$(CONFIG_ARCH_CNS3XXX)            += core.o pm.o devices.o
-+obj-$(CONFIG_ARCH_CNS3XXX)            += core.o gpio.o pm.o devices.o
- obj-$(CONFIG_PCI)                     += pcie.o
- obj-$(CONFIG_MACH_CNS3420VB)          += cns3420vb.o
- obj-$(CONFIG_SMP)                     += platsmp.o headsmp.o cns3xxx_fiq.o
---- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
-+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
-@@ -627,7 +627,7 @@ int cns3xxx_cpu_clock(void);
- #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
- #undef NR_IRQS
--#define NR_IRQS                               NR_IRQS_CNS3XXX
-+#define NR_IRQS                               (NR_IRQS_CNS3XXX + 64)
- #endif
- #endif        /* __MACH_BOARD_CNS3XXX_H */
diff --git a/target/linux/cns3xxx/patches-3.8/097-l2x0_cmdline_disable.patch b/target/linux/cns3xxx/patches-3.8/097-l2x0_cmdline_disable.patch
deleted file mode 100644 (file)
index eb5c811..0000000
+++ /dev/null
@@ -1,70 +0,0 @@
---- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -293,13 +293,26 @@ struct sys_timer cns3xxx_timer = {
- #ifdef CONFIG_CACHE_L2X0
--void __init cns3xxx_l2x0_init(void)
-+static int cns3xxx_l2x0_enable = 1;
-+
-+static int __init cns3xxx_l2x0_disable(char *s)
-+{
-+      cns3xxx_l2x0_enable = 0;
-+      return 1;
-+}
-+__setup("nol2x0", cns3xxx_l2x0_disable);
-+
-+static int __init cns3xxx_l2x0_init(void)
- {
--      void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
-+      void __iomem *base;
-       u32 val;
-+      if (!cns3xxx_l2x0_enable)
-+              return 0;
-+
-+      base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
-       if (WARN_ON(!base))
--              return;
-+              return 0;
-       /*
-        * Tag RAM Control register
-@@ -329,7 +342,10 @@ void __init cns3xxx_l2x0_init(void)
-       /* 32 KiB, 8-way, parity disable */
-       l2x0_init(base, 0x00540000, 0xfe000fff);
-+
-+      return 0;
- }
-+arch_initcall(cns3xxx_l2x0_init);
- #endif /* CONFIG_CACHE_L2X0 */
---- a/arch/arm/mach-cns3xxx/cns3420vb.c
-+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
-@@ -241,8 +241,6 @@ static struct platform_device *cns3420_p
- static void __init cns3420_init(void)
- {
--      cns3xxx_l2x0_init();
--
-       platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
-       cns3xxx_ahci_init();
---- a/arch/arm/mach-cns3xxx/core.h
-+++ b/arch/arm/mach-cns3xxx/core.h
-@@ -15,13 +15,6 @@ extern struct smp_operations cns3xxx_smp
- extern struct sys_timer cns3xxx_timer;
- extern void cns3xxx_pcie_iotable_init(void);
--
--#ifdef CONFIG_CACHE_L2X0
--void __init cns3xxx_l2x0_init(void);
--#else
--static inline void cns3xxx_l2x0_init(void) {}
--#endif /* CONFIG_CACHE_L2X0 */
--
- void __init cns3xxx_common_init(void);
- void __init cns3xxx_init_irq(void);
- int  __init cns3xxx_pcie_init(void);
diff --git a/target/linux/cns3xxx/patches-3.8/200-dwc_otg_support.patch b/target/linux/cns3xxx/patches-3.8/200-dwc_otg_support.patch
deleted file mode 100644 (file)
index 8d4d79e..0000000
+++ /dev/null
@@ -1,48 +0,0 @@
---- a/drivers/Makefile
-+++ b/drivers/Makefile
-@@ -81,6 +81,7 @@ obj-$(CONFIG_PARIDE)                 += block/paride/
- obj-$(CONFIG_TC)              += tc/
- obj-$(CONFIG_UWB)             += uwb/
- obj-$(CONFIG_USB_OTG_UTILS)   += usb/
-+obj-$(CONFIG_USB_DWC_OTG)     += usb/dwc/
- obj-$(CONFIG_USB)             += usb/
- obj-$(CONFIG_PCI)             += usb/
- obj-$(CONFIG_USB_GADGET)      += usb/
---- a/drivers/usb/Kconfig
-+++ b/drivers/usb/Kconfig
-@@ -138,6 +138,8 @@ source "drivers/usb/chipidea/Kconfig"
- source "drivers/usb/renesas_usbhs/Kconfig"
-+source "drivers/usb/dwc/Kconfig"
-+
- source "drivers/usb/class/Kconfig"
- source "drivers/usb/storage/Kconfig"
---- a/drivers/usb/core/urb.c
-+++ b/drivers/usb/core/urb.c
-@@ -17,7 +17,11 @@ static void urb_destroy(struct kref *kre
-       if (urb->transfer_flags & URB_FREE_BUFFER)
-               kfree(urb->transfer_buffer);
--
-+      if (urb->aligned_transfer_buffer) {
-+              kfree(urb->aligned_transfer_buffer);
-+              urb->aligned_transfer_buffer = 0;
-+              urb->aligned_transfer_dma = 0;
-+      }
-       kfree(urb);
- }
---- a/include/linux/usb.h
-+++ b/include/linux/usb.h
-@@ -1401,6 +1401,9 @@ struct urb {
-       unsigned int transfer_flags;    /* (in) URB_SHORT_NOT_OK | ...*/
-       void *transfer_buffer;          /* (in) associated data buffer */
-       dma_addr_t transfer_dma;        /* (in) dma addr for transfer_buffer */
-+      void *aligned_transfer_buffer;  /* (in) associeated data buffer */
-+      dma_addr_t aligned_transfer_dma;/* (in) dma addr for transfer_buffer */
-+      u32 aligned_transfer_buffer_length; /* (in) data buffer length */
-       struct scatterlist *sg;         /* (in) scatter gather buffer list */
-       int num_mapped_sgs;             /* (internal) mapped sg entries */
-       int num_sgs;                    /* (in) number of entries in the sg list */
diff --git a/target/linux/cns3xxx/patches-3.8/300-laguna_support.patch b/target/linux/cns3xxx/patches-3.8/300-laguna_support.patch
deleted file mode 100644 (file)
index 210ab02..0000000
+++ /dev/null
@@ -1,47 +0,0 @@
---- a/arch/arm/mach-cns3xxx/Kconfig
-+++ b/arch/arm/mach-cns3xxx/Kconfig
-@@ -9,4 +9,12 @@ config MACH_CNS3420VB
-         This is a platform with an on-board ARM11 MPCore and has support
-         for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
-+config MACH_GW2388
-+      bool "Support for Gateworks Laguna Platform"
-+      help
-+        Include support for the Gateworks Laguna Platform
-+
-+        This is a platform with an on-board ARM11 MPCore and has support
-+        for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc.
-+
- endmenu
---- a/arch/arm/mach-cns3xxx/Makefile
-+++ b/arch/arm/mach-cns3xxx/Makefile
-@@ -1,5 +1,6 @@
- obj-$(CONFIG_ARCH_CNS3XXX)            += core.o gpio.o pm.o devices.o
- obj-$(CONFIG_PCI)                     += pcie.o
- obj-$(CONFIG_MACH_CNS3420VB)          += cns3420vb.o
-+obj-$(CONFIG_MACH_GW2388)             += laguna.o
- obj-$(CONFIG_SMP)                     += platsmp.o headsmp.o cns3xxx_fiq.o
- obj-$(CONFIG_HOTPLUG_CPU)             += hotplug.o
---- a/arch/arm/mach-cns3xxx/devices.c
-+++ b/arch/arm/mach-cns3xxx/devices.c
-@@ -19,6 +19,7 @@
- #include <mach/cns3xxx.h>
- #include <mach/irqs.h>
- #include <mach/pm.h>
-+#include <asm/mach-types.h>
- #include "core.h"
- #include "devices.h"
-@@ -102,7 +103,11 @@ void __init cns3xxx_sdhci_init(void)
-       u32 gpioa_pins = __raw_readl(gpioa);
-       /* MMC/SD pins share with GPIOA */
--      gpioa_pins |= 0x1fff0004;
-+      if (machine_is_gw2388()) {
-+              gpioa_pins |= 0x1fff0000;
-+      } else {
-+              gpioa_pins |= 0x1fff0004;
-+      }
-       __raw_writel(gpioa_pins, gpioa);
-       cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
diff --git a/target/linux/cns3xxx/patches-3.8/305-laguna_sdhci_card_detect.patch b/target/linux/cns3xxx/patches-3.8/305-laguna_sdhci_card_detect.patch
deleted file mode 100644 (file)
index 03b2bb7..0000000
+++ /dev/null
@@ -1,16 +0,0 @@
---- a/drivers/mmc/host/sdhci-cns3xxx.c
-+++ b/drivers/mmc/host/sdhci-cns3xxx.c
-@@ -89,10 +89,11 @@ static struct sdhci_pltfm_data sdhci_cns
-       .ops = &sdhci_cns3xxx_ops,
-       .quirks = SDHCI_QUIRK_BROKEN_DMA |
-                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
--                SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
-+                //SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
-                 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
-                 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
--                SDHCI_QUIRK_NONSTANDARD_CLOCK,
-+                SDHCI_QUIRK_NONSTANDARD_CLOCK |
-+                SDHCI_QUIRK_BROKEN_CARD_DETECTION,
- };
- static int sdhci_cns3xxx_probe(struct platform_device *pdev)