bit = (pos << 1) % 32;
if (priv->family_id == RTL8380_FAMILY_ID) {
- cmd = 1 << 15 /* Execute cmd */
- | 1 << 14 /* Read */
+ cmd = BIT(15) /* Execute cmd */
+ | BIT(14) /* Read */
| 2 << 12 /* Table type 0b10 */
| (msti & 0xfff);
} else {
- cmd = 1 << 16 /* Execute cmd */
+ cmd = BIT(16) /* Execute cmd */
| 0 << 15 /* Read */
| 5 << 12 /* Table type 0b101 */
| (msti & 0xfff);
/* Enable PHY control via SoC */
if (priv->family_id == RTL8380_FAMILY_ID) {
/* Enable PHY control via SoC */
- sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL);
+ sw_w32_mask(0, BIT(15), RTL838X_SMI_GLB_CTRL);
} else {
/* Disable PHY polling via SoC */
- sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL);
+ sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);
}
/* Power on fibre ports and reset them if necessary */
static void rtl83xx_write_cam(int idx, u32 *r)
{
- u32 cmd = 1 << 16 /* Execute cmd */
- | 1 << 15 /* Read */
- | 1 << 13 /* Table type 0b01 */
+ u32 cmd = BIT(16) /* Execute cmd */
+ | BIT(15) /* Read */
+ | BIT(13) /* Table type 0b01 */
| (idx & 0x3f);
sw_w32(r[0], RTL838X_TBL_ACCESS_L2_DATA(0));
sw_w32(r[2], RTL838X_TBL_ACCESS_L2_DATA(2));
sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
- do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16));
+ do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
}
static u64 rtl83xx_hash_key(struct rtl838x_switch_priv *priv, u64 mac, u32 vid)
static void rtl83xx_write_hash(int idx, u32 *r)
{
- u32 cmd = 1 << 16 /* Execute cmd */
+ u32 cmd = BIT(16) /* Execute cmd */
| 0 << 15 /* Write */
| 0 << 13 /* Table type 0b00 */
| (idx & 0x1fff);
sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(1));
sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(2));
sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
- do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16));
+ do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
}
static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
/* Enable all ports with a PHY, including the SFP-ports */
for (i = 0; i < priv->cpu_port; i++) {
if (priv->ports[i].phy)
- v |= 1 << i;
+ v |= BIT(i);
}
pr_info("%s: %16llx\n", __func__, v);
/* PHY update complete */
if (priv->family_id == RTL8390_FAMILY_ID)
- sw_w32_mask(0, 1 << 7, RTL839X_SMI_GLB_CTRL);
+ sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
else
sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
}
{
int i;
struct rtl838x_switch_priv *priv = ds->priv;
- u64 port_bitmap = 1ULL << priv->cpu_port;
+ u64 port_bitmap = BIT_ULL(priv->cpu_port);
pr_info("%s called\n", __func__);
*/
for (i = 0; i < priv->cpu_port; i++) {
if (priv->ports[i].phy) {
- priv->r->set_port_reg_be(1ULL << priv->cpu_port | 1ULL << i,
+ priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT(i),
priv->r->port_iso_ctrl(i));
- port_bitmap |= 1ULL << i;
+ port_bitmap |= BIT_ULL(i);
}
}
priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
return -EINVAL;
state->link = 0;
- if (priv->r->get_port_reg_le(priv->r->mac_link_sts) & (1ULL << port))
+ if (priv->r->get_port_reg_le(priv->r->mac_link_sts) & BIT_ULL(port))
state->link = 1;
state->duplex = 0;
- if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & (1ULL << port))
+ if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
state->duplex = 1;
speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
}
state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
- if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & (1ULL << port))
+ if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
state->pause |= MLO_PAUSE_RX;
- if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & (1ULL << port))
+ if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
state->pause |= MLO_PAUSE_TX;
return 1;
}
if (priv->family_id == RTL8380_FAMILY_ID) {
if (mode == MLO_AN_PHY) {
pr_info("PHY autonegotiates\n");
- reg |= 1 << 2;
+ reg |= BIT(2);
sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
return;
}
// Disable AN
if (priv->family_id == RTL8380_FAMILY_ID)
- reg &= ~(1 << 2);
+ reg &= ~BIT(2);
sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
}
return 0;
/* add port to switch mask of CPU_PORT */
- priv->r->mask_port_reg_be(0ULL, 1ULL << port, priv->r->port_iso_ctrl(priv->cpu_port));
+ priv->r->mask_port_reg_be(0ULL, BIT_ULL(port), priv->r->port_iso_ctrl(priv->cpu_port));
/* add all other ports in the same bridge to switch mask of port */
priv->r->mask_port_reg_be(0ULL, priv->ports[port].pm, priv->r->port_iso_ctrl(port));
return;
/* remove port from switch mask of CPU_PORT */
- priv->r->mask_port_reg_be(1ULL << port, 0, priv->r->port_iso_ctrl(priv->cpu_port));
+ priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->port_iso_ctrl(priv->cpu_port));
/* remove all other ports in the same bridge from switch mask of port */
priv->r->mask_port_reg_be(priv->ports[port].pm, 0LL, priv->r->port_iso_ctrl(port));
pr_info("%s: port %d", __func__, port);
e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
- if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & (1 << 9))
+ if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & BIT(9))
e->advertised |= ADVERTISED_100baseT_Full;
- if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & (1 << 10))
+ if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & BIT(10))
e->advertised |= ADVERTISED_1000baseT_Full;
e->eee_enabled = priv->ports[port].eee_enabled;
pr_info("enabled: %d, active %x\n", e->eee_enabled, e->advertised);
- if (sw_r32(RTL838X_MAC_EEE_ABLTY) & (1 << port)) {
+ if (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) {
e->lp_advertised = ADVERTISED_100baseT_Full;
e->lp_advertised |= ADVERTISED_1000baseT_Full;
}
if (e->eee_enabled) {
pr_info("Enabling EEE for MAC %d\n", port);
sw_w32_mask(0, 3 << 9, priv->r->mac_force_mode_ctrl(port));
- sw_w32_mask(0, 1 << port, RTL838X_EEE_PORT_TX_EN);
- sw_w32_mask(0, 1 << port, RTL838X_EEE_PORT_RX_EN);
+ sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN);
+ sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN);
priv->ports[port].eee_enabled = true;
e->eee_enabled = true;
} else {
pr_info("Disabling EEE for MAC %d\n", port);
sw_w32_mask(3 << 9, 0, priv->r->mac_force_mode_ctrl(port));
- sw_w32_mask(1 << port, 0, RTL838X_EEE_PORT_TX_EN);
- sw_w32_mask(1 << port, 0, RTL838X_EEE_PORT_RX_EN);
+ sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN);
+ sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN);
priv->ports[port].eee_enabled = false;
e->eee_enabled = false;
}
struct net_device *bridge)
{
struct rtl838x_switch_priv *priv = ds->priv;
- u64 port_bitmap = 1ULL << priv->cpu_port;
+ u64 port_bitmap = BIT_ULL(priv->cpu_port);
int i;
pr_info("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
if (dsa_to_port(ds, i)->bridge_dev != bridge)
continue;
if (priv->ports[i].enable)
- priv->r->mask_port_reg_be(0, 1ULL << port,
+ priv->r->mask_port_reg_be(0, BIT_ULL(port),
priv->r->port_iso_ctrl(i));
- priv->ports[i].pm |= 1ULL << port;
+ priv->ports[i].pm |= BIT_ULL(port);
- port_bitmap |= 1ULL << i;
+ port_bitmap |= BIT_ULL(i);
}
}
/* Add all other ports to this port matrix. */
if (priv->ports[port].enable) {
- priv->r->mask_port_reg_be(0, 1ULL << port,
+ priv->r->mask_port_reg_be(0, BIT_ULL(port),
priv->r->port_iso_ctrl(priv->cpu_port));
priv->r->mask_port_reg_be(0, port_bitmap,
priv->r->port_iso_ctrl(port));
struct net_device *bridge)
{
struct rtl838x_switch_priv *priv = ds->priv;
- u64 port_bitmap = 1ULL << priv->cpu_port;
+ u64 port_bitmap = BIT_ULL(priv->cpu_port);
int i;
pr_info("%s %x: %d", __func__, (u32)priv, port);
if (dsa_to_port(ds, i)->bridge_dev != bridge)
continue;
if (priv->ports[i].enable)
- priv->r->mask_port_reg_be(1ULL << port, 0,
+ priv->r->mask_port_reg_be(BIT_ULL(port), 0,
priv->r->port_iso_ctrl(i));
- priv->ports[i].pm &= ~(1ULL << port);
+ priv->ports[i].pm &= ~BIT_ULL(port);
- port_bitmap &= ~(1ULL << i);
+ port_bitmap &= ~BIT_ULL(i);
}
}
bit = (pos << 1) % 32;
if (priv->family_id == RTL8380_FAMILY_ID) {
- cmd = 1 << 15 /* Execute cmd */
- | 1 << 14 /* Read */
+ cmd = BIT(15) /* Execute cmd */
+ | BIT(14) /* Read */
| 2 << 12 /* Table type 0b10 */
| (msti & 0xfff);
} else {
- cmd = 1 << 16 /* Execute cmd */
+ cmd = BIT(16) /* Execute cmd */
| 0 << 15 /* Read */
| 5 << 12 /* Table type 0b101 */
| (msti & 0xfff);
}
if (priv->family_id == RTL8380_FAMILY_ID) {
- cmd = 1 << 15 /* Execute cmd */
+ cmd = BIT(15) /* Execute cmd */
| 0 << 14 /* Write */
| 2 << 12 /* Table type 0b10 */
| (msti & 0xfff);
} else {
cmd = 1 << 16 /* Execute cmd */
- | 1 << 15 /* Write */
+ | BIT(15) /* Write */
| 5 << 12 /* Table type 0b101 */
| (msti & 0xfff);
}
for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
/* Get untagged port memberships of this vlan */
priv->r->vlan_tables_read(v, &info);
- portmask = info.untagged_ports | (1 << port);
+ portmask = info.untagged_ports | BIT(port);
pr_debug("Untagged ports, VLAN %d: %llx\n", v, portmask);
priv->r->vlan_set_untagged(v, portmask);
}
for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
/* Get tagged port memberships of this vlan */
priv->r->vlan_tables_read(v, &info);
- info.tagged_ports |= (1 << port);
+ info.tagged_ports |= BIT(port);
pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
priv->r->vlan_set_tagged(v, &info);
}
read_phy(mac, 0, 0, &val);
if (on)
- write_phy(mac, 0, 0, val & ~(1 << 11));
+ write_phy(mac, 0, 0, val & ~BIT(11));
else
- write_phy(mac, 0, 0, val | (1 << 11));
+ write_phy(mac, 0, 0, val | BIT(11));
}
static void rtl8214fc_on_off(int mac, bool on)
write_phy(mac, 4095, 30, 3);
read_phy(mac, 0, 16, &val);
if (on)
- write_phy(mac, 0, 16, val & ~(1 << 11));
+ write_phy(mac, 0, 16, val & ~BIT(11));
else
- write_phy(mac, 0, 16, val | (1 << 11));
+ write_phy(mac, 0, 16, val | BIT(11));
/* copper ports */
write_phy(mac, 4095, 30, 1);
read_phy(mac, 0, 16, &val);
if (on)
- write_phy(mac, 0xa40, 16, val & ~(1 << 11));
+ write_phy(mac, 0xa40, 16, val & ~BIT(11));
else
- write_phy(mac, 0xa40, 16, val | (1 << 11));
+ write_phy(mac, 0xa40, 16, val | BIT(11));
}
static void phy_reset(int mac)
u32 val;
read_phy(mac, 0, 0, &val);
- write_phy(mac, 0, 0, val | (0x1 << 15));
+ write_phy(mac, 0, 0, val | BIT(15));
}
/* Read the link and speed status of the 2 internal SGMII/1000Base-X
* PHY registers
*/
v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
- if (!(v & (1 << 13)) && (v & (1 << 6)))
+ if (!(v & (BIT(13)) && (v & BIT(6)))
phydev->speed = SPEED_1000;
phydev->duplex = DUPLEX_FULL;
}
ipd_flag = 1;
read_phy(mac, 0, 0, &val);
- if (val & (1 << 11))
+ if (val & BIT(11))
int_phy_on_off(mac, true);
else
phy_reset(mac);
+ h->parts[2].start;
read_phy(mac, 0, 0, &val);
- if (val & (1 << 11))
+ if (val & BIT(11))
int_phy_on_off(mac, true);
else
phy_reset(mac);
if (rtl838x_smi_wait_op(10000))
goto timeout;
- sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
+ sw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0);
mdelay(10);
sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3);
/* mmd-access | read | cmd-start */
- v = 1 << 1 | 0 << 2 | 1;
+ v = BIT(1) | 0 << 2 | 1;
sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
if (rtl838x_smi_wait_op(10000))
if (rtl838x_smi_wait_op(10000))
goto timeout;
- sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
+ sw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0);
mdelay(10);
sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3);
sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3);
/* mmd-access | write | cmd-start */
- v = 1 << 1 | 1 << 2 | 1;
+ v = BIT(1) | BIT(2) | BIT(0);
sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
if (rtl838x_smi_wait_op(10000))
write_phy(base, 0xfff, 29, 1);
/* Ensure power is off */
read_phy(base, 0xa40, 16, &power);
- if (!(power & (1 << 11)))
- write_phy(base, 0xa40, 16, power | (1 << 11));
+ if (!(power & BIT(11)))
+ write_phy(base, 0xa40, 16, power | BIT(11));
} else {
pr_info("Powering off FIBRE");
write_phy(base, 0xfff, 29, 3);
/* Ensure power is off */
read_phy(base, 0xa40, 16, &power);
- if (!(power & (1 << 11)))
- write_phy(base, 0xa40, 16, power | (1 << 11));
+ if (!(power & BIT(11)))
+ write_phy(base, 0xa40, 16, power | BIT(11));
}
if (set_fibre) {
- val |= 1 << 10;
- val &= ~(1 << 11);
+ val |= BIT(10);
+ val &= ~BIT(11);
} else {
- val |= 1 << 10;
- val |= 1 << 11;
+ val |= BIT(10);
+ val |= BIT(11);
}
write_phy(base, 0xfff, 29, 8);
write_phy(base, 0x266, reg[mac % 4], val);
write_phy(base, 0xfff, 29, 3);
/* Ensure power is off */
read_phy(base, 0xa40, 16, &power);
- if (power & (1 << 11))
- write_phy(base, 0xa40, 16, power & ~(1 << 11));
+ if (power & BIT(11))
+ write_phy(base, 0xa40, 16, power & ~BIT(11));
} else {
pr_info("Powering on COPPER\n");
write_phy(base, 0xfff, 29, 1);
/* Ensure power is off */
read_phy(base, 0xa40, 16, &power);
- if (power & (1 << 11))
- write_phy(base, 0xa40, 16, power & ~(1 << 11));
+ if (power & BIT(11))
+ write_phy(base, 0xa40, 16, power & ~BIT(11));
}
write_phy(base, 0xfff, 29, 0);
write_phy(base, 0xfff, 29, 8);
read_phy(base, 0x266, reg[mac % 4], &val);
write_phy(base, 0xfff, 29, 0);
- if (val & (1 << 11))
+ if (val & BIT(11))
return false;
return true;
}
/* Set GPHY page to copper */
write_phy(port, 0, 30, 0x0001);
read_phy(port, 0, 0, &val);
- an_enabled = val & (1 << 12);
+ an_enabled = val & BIT(12);
if (enable) {
/* 100/1000M EEE Capability */
write_phy(port, 0, 14, 0x0006);
read_phy(port, 0x0A43, 25, &val);
- val |= 1 << 4;
+ val |= BIT(4);
write_phy(port, 0x0A43, 25, val);
} else {
/* 100/1000M EEE Capability */
write_phy(port, 0, 14, 0x0000);
read_phy(port, 0x0A43, 25, &val);
- val &= ~(1 << 4);
+ val &= ~BIT(4);
write_phy(port, 0x0A43, 25, val);
}
/* Restart AN if enabled */
if (an_enabled) {
read_phy(port, 0, 0, &val);
- val |= (1 << 12) | (1 << 9);
+ val |= BIT(12) | BIT(9);
write_phy(port, 0, 0, val);
}
write_phy(port, 0xa42, 29, 0x0001);
read_phy(port, 0, 0, &val);
- an_enabled = val & (1 << 12);
+ an_enabled = val & BIT(12);
/* MAC based EEE */
read_phy(port, 0xa43, 25, &val);
- val &= ~(1 << 5);
+ val &= ~BIT(5);
write_phy(port, 0xa43, 25, val);
/* 100M / 1000M EEE */
/* 500M EEE ability */
read_phy(port, 0xa42, 20, &val);
if (enable)
- val |= 1 << 7;
+ val |= BIT(7);
else
- val &= ~(1 << 7);
+ val &= ~BIT(7);
write_phy(port, 0xa42, 20, val);
/* Restart AN if enabled */
if (an_enabled) {
read_phy(port, 0, 0, &val);
- val |= (1 << 12) | (1 << 9);
+ val |= BIT(12) | BIT(9);
write_phy(port, 0, 0, val);
}
write_phy(addr, 0xa42, 29, 0x0001);
rtl83xx_read_mmd_phy(addr, 7, 60, &val);
- if (e->eee_enabled && (!!(val & (1 << 7))))
- e->eee_enabled = !!(val & (1 << 7));
+ if (e->eee_enabled && (!!(val & BIT(7))))
+ e->eee_enabled = !!(val & BIT(7));
else
e->eee_enabled = 0;
write_phy(mac, 0, 27, 0x8011);
read_phy(mac, 0, 28, &val);
if (enable) {
- val |= 1 << 9;
+ val |= BIT(9);
write_phy(mac, 0, 27, 0x8011);
write_phy(mac, 0, 28, val);
} else {
- val &= ~(1 << 9);
+ val &= ~BIT(9);
write_phy(mac, 0, 27, 0x8011);
write_phy(mac, 0, 28, val);
}
write_phy(addr, 0, 27, 0x8011);
read_phy(addr, 0, 28, &val);
- if (e->eee_enabled && (!!(val & (1 << 9))))
- e->eee_enabled = !!(val & (1 << 9));
+ if (e->eee_enabled && (!!(val & BIT(9))))
+ e->eee_enabled = !!(val & BIT(9));
else
e->eee_enabled = 0;
read_phy(mac, 0xfff, 28, &val);
read_phy(mac, 0, 16, &val);
- if (val & (1 << 11))
+ if (val & BIT(11))
rtl8214fc_on_off(mac, true);
else
phy_reset(mac);
sw_w32(3, RTL838X_INT_RW_CTRL);
/* SerDes ports 4 and 5 are FIBRE ports */
- sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
+ sw_w32_mask(0x7 | 0x38, 1 | BIT(3), RTL838X_INT_MODE_CTRL);
/* SerDes module settings, SerDes 0-3 are QSGMII */
v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
/* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
- sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
+ sw_w32_mask(0, BIT(18), RTL839X_SDS12_13_XSG0 + 0x0a);
/* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
* FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
static inline void rtl838x_exec_tbl0_cmd(u32 cmd)
{
sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0);
- do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & (1 << 15));
+ do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & BIT(15));
}
static inline void rtl838x_exec_tbl1_cmd(u32 cmd)
{
sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1);
- do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & (1 << 15));
+ do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & BIT(15));
}
static inline int rtl838x_tbl_access_data_0(int i)
{
u32 cmd, v;
- cmd = 1 << 15 /* Execute cmd */
- | 1 << 14 /* Read */
+ cmd = BIT(15) /* Execute cmd */
+ | BIT(14) /* Read */
| 0 << 12 /* Table type 0b00 */
| (vlan & 0xfff);
rtl838x_exec_tbl0_cmd(cmd);
info->fid = (v >> 5) & 0x3f;
- cmd = 1 << 15 /* Execute cmd */
- | 1 << 14 /* Read */
+ cmd = BIT(15) /* Execute cmd */
+ | BIT(14) /* Read */
| 0 << 12 /* Table type 0b00 */
| (vlan & 0xfff);
rtl838x_exec_tbl1_cmd(cmd);
static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
{
- u32 cmd = 1 << 15 /* Execute cmd */
+ u32 cmd = BIT(15) /* Execute cmd */
| 0 << 14 /* Write */
| 0 << 12 /* Table type 0b00 */
| (vlan & 0xfff);
static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask)
{
- u32 cmd = 1 << 15 /* Execute cmd */
+ u32 cmd = BIT(15) /* Execute cmd */
| 0 << 14 /* Write */
| 0 << 12 /* Table type 0b00 */
| (vlan & 0xfff);
/* Search in SRAM, with hash and at position in hash bucket (0-3) */
u32 idx = (0 << 14) | (hash << 2) | position;
- u32 cmd = 1 << 16 /* Execute cmd */
- | 1 << 15 /* Read */
+ u32 cmd = BIT(16) /* Execute cmd */
+ | BIT(15) /* Read */
| 0 << 13 /* Table type 0b00 */
| (idx & 0x1fff);
sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
- do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16));
+ do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
u64 entry;
u32 r[3];
- u32 cmd = 1 << 16 /* Execute cmd */
- | 1 << 15 /* Read */
- | 1 << 13 /* Table type 0b01 */
+ u32 cmd = BIT(16) /* Execute cmd */
+ | BIT(15) /* Read */
+ | BIT(13) /* Table type 0b01 */
| (idx & 0x3f);
sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
- do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16));
+ do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
pr_info("RTL8380 Link change: status: %x, ports %x\n", status, ports);
for (i = 0; i < 28; i++) {
- if (ports & (1 << i)) {
+ if (ports & BIT(i)) {
link = sw_r32(RTL838X_MAC_LINK_STS);
- if (link & (1 << i))
+ if (link & BIT(i))
dsa_port_phylink_mac_change(ds, i, true);
else
dsa_port_phylink_mac_change(ds, i, false);
if (rtl838x_smi_wait_op(10000))
goto timeout;
- sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
+ sw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0);
mdelay(10);
sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
static inline void rtl839x_exec_tbl0_cmd(u32 cmd)
{
sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
- do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & (1 << 16));
+ do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16));
}
static inline void rtl839x_exec_tbl1_cmd(u32 cmd)
{
sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
- do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & (1 << 16));
+ do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16));
}
static inline int rtl839x_tbl_access_data_0(int i)
u64 v;
u32 u, w;
- cmd = 1 << 16 /* Execute cmd */
+ cmd = BIT(16) /* Execute cmd */
| 0 << 15 /* Read */
| 0 << 12 /* Table type 0b000 */
| (vlan & 0xfff);
info->hash_uc = !!(u & 4);
info->fid = (u >> 3) & 0xff;
- cmd = 1 << 16 /* Execute cmd */
+ cmd = BIT(16) /* Execute cmd */
| 0 << 15 /* Read */
| 0 << 12 /* Table type 0b000 */
| (vlan & 0xfff);
static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
{
- u32 cmd = 1 << 16 /* Execute cmd */
- | 1 << 15 /* Write */
+ u32 cmd = BIT(16) /* Execute cmd */
+ | BIT(15) /* Write */
| 0 << 12 /* Table type 0b00 */
| (vlan & 0xfff);
u32 w;
static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
{
- u32 cmd = 1 << 16 /* Execute cmd */
- | 1 << 15 /* Write */
+ u32 cmd = BIT(16) /* Execute cmd */
+ | BIT(15) /* Write */
| 0 << 12 /* Table type 0b00 */
| (vlan & 0xfff);
rtl839x_set_port_reg_be(portmask << 11, RTL838X_TBL_ACCESS_DATA_1(0));
/* Search in SRAM, with hash and at position in hash bucket (0-3) */
u32 idx = (0 << 14) | (hash << 2) | position;
- u32 cmd = 1 << 17 /* Execute cmd */
+ u32 cmd = BIT(17) /* Execute cmd */
| 0 << 16 /* Read */
| 0 << 14 /* Table type 0b00 */
| (idx & 0x3fff);
sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
- do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17));
+ do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & BIT(17));
r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
/* Table contains different entry types, we need to identify the right one:
* Check for MC entries, first
*/
- e->is_ip_mc = !!(r[2] & (1 << 31));
- e->is_ipv6_mc = !!(r[2] & (1 << 30));
+ e->is_ip_mc = !!(r[2] & BIT(31));
+ e->is_ipv6_mc = !!(r[2] & BIT(30));
e->type = L2_INVALID;
if (!e->is_ip_mc) {
e->mac[0] = (r[0] >> 12);
e->vid = (r[2] >> 4) & 0xfff;
e->rvid = (r[0] >> 20) & 0xfff;
e->port = (r[2] >> 24) & 0x3f;
- e->block_da = !!(r[2] & (1 << 19));
- e->block_sa = !!(r[2] & (1 << 20));
- e->suspended = !!(r[2] & (1 << 17));
- e->next_hop = !!(r[2] & (1 << 16));
+ e->block_da = !!(r[2] & BIT(19));
+ e->block_sa = !!(r[2] & BIT(20));
+ e->suspended = !!(r[2] & BIT(17));
+ e->next_hop = !!(r[2] & BIT(16));
if (e->next_hop)
pr_info("Found next hop entry, need to read data\n");
e->age = (r[2] >> 21) & 3;
u64 entry;
u32 r[3];
- u32 cmd = 1 << 17 /* Execute cmd */
+ u32 cmd = BIT(17) /* Execute cmd */
| 0 << 16 /* Read */
- | 1 << 14 /* Table type 0b01 */
+ | BIT(14) /* Table type 0b01 */
| (idx & 0x3f);
sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
- do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17));
+ do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & BIT(17));
r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
}
// Set bit 1003. 1000 starts at 7c
- sw_w32_mask(1 << 11, mode << 11, RTL839X_SDS12_13_PWR0 + offset);
+ sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);
return 0;
}
/* Clear both port registers */
sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0));
sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0) + 4);
- sw_w32_mask(0, 1 << port, RTL839X_PHYREG_PORT_CTRL(port));
+ sw_w32_mask(0, BIT(port), RTL839X_PHYREG_PORT_CTRL(port));
sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
- v |= 1 << 3 | 1; /* Write operation and execute */
+ v |= BIT(3) | 1; /* Write operation and execute */
sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
do {
sw_w32(0x00200020, RTL838X_STORM_CTRL_BURST_PPS_1); // MC and BC
// Include IFG in storm control
- sw_w32_mask(0, 1 << 6, RTL838X_STORM_CTRL);
+ sw_w32_mask(0, BIT(6), RTL838X_STORM_CTRL);
// Rate control is based on bytes/s (0 = packets)
- sw_w32_mask(0, 1 << 5, RTL838X_STORM_CTRL);
+ sw_w32_mask(0, BIT(5), RTL838X_STORM_CTRL);
// Bandwidth control includes preamble and IFG (10 Bytes)
sw_w32_mask(0, 1, RTL838X_SCHED_CTRL);
* for UC and MC for both known and unknown addresses */
for (i = 0; i < priv->cpu_port; i++) {
if (priv->ports[i].phy) {
- sw_w32((1 << 18) | 0x8000, RTL838X_STORM_CTRL_PORT_UC(i));
- sw_w32((1 << 18) | 0x8000, RTL838X_STORM_CTRL_PORT_MC(i));
+ sw_w32(BIT(18) | 0x8000, RTL838X_STORM_CTRL_PORT_UC(i));
+ sw_w32(BIT(18) | 0x8000, RTL838X_STORM_CTRL_PORT_MC(i));
sw_w32(0x000, RTL838X_STORM_CTRL_PORT_BC(i));
rtl83xx_storm_enable(priv, i, true);
}
projects / openwrt / staging / blogic.git / commitdiff