This is required for linux-6.1 compatibility.
IRQs are not automatically mapped from HW to virtual IRQ numbers when
the IRQ domain is registered. This happens when the IRQ number is read
from the device tree based on the IRQ domain from the device tree now.
In kernel 5.15 it was done when the IRQ domain was registered.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
goto REGISTER_NETDEV_FAIL;
}
+ g_ptm_priv_data.irq = platform_get_irq(pdev, 0);
+ if (g_ptm_priv_data.irq < 0) {
+ err("platform_get_irq fail");
+ goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
+ }
+
/* register interrupt handler */
- ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data);
+ ret = request_irq(g_ptm_priv_data.irq, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data);
if ( ret ) {
if ( ret == -EBUSY ) {
err("IRQ may be occupied by other driver, please reconfig to disable it.");
}
goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
}
- disable_irq(PPE_MAILBOX_IGU1_INT);
+ disable_irq(g_ptm_priv_data.irq);
ret = ifx_pp32_start(0);
if ( ret ) {
IFX_REG_W32(0, MBOX_IGU1_IER);
IFX_REG_W32(~0, MBOX_IGU1_ISRC);
- enable_irq(PPE_MAILBOX_IGU1_INT);
+ enable_irq(g_ptm_priv_data.irq);
proc_file_create();
return 0;
PP32_START_FAIL:
- free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
+ free_irq(g_ptm_priv_data.irq, &g_ptm_priv_data);
REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
i = ARRAY_SIZE(g_net_dev);
REGISTER_NETDEV_FAIL:
ifx_pp32_stop(0);
- free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
+ free_irq(g_ptm_priv_data.irq, &g_ptm_priv_data);
for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )
unregister_netdev(g_net_dev[i]);
#include "ifxmips_ptm_fw_regs_adsl.h"
#define CONFIG_IFXMIPS_DSL_CPE_MEI
-#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24)
#define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r))
#define IFX_REG_R32(_r) __raw_readl((volatile unsigned int *)(_r))
struct ptm_priv_data {
struct ptm_itf itf[MAX_ITF_NUMBER];
+ int irq;
void *rx_desc_base;
void *tx_desc_base;
#define EMA_ALIGNMENT 4
-/*
- * Mailbox IGU1 Interrupt
- */
-#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL13
-
#endif // IFXMIPS_PTM_PPE_AMAZON_SE_H
#define SW_P2_CTL SW_REG(0x00C)
-/*
- * Mailbox IGU1 Interrupt
- */
-#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
-
-
#endif // IFXMIPS_PTM_PPE_AR9_H
#define EMA_ALIGNMENT 4
-/*
- * Mailbox IGU1 Interrupt
- */
-#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
-
#endif // IFXMIPS_PTM_PPE_DANUBE_H
#define PDMA_ALIGNMENT 32 // same as Central DMA because of descriptor swap
#define EMA_ALIGNMENT PDMA_ALIGNMENT
-/*
- * Mailbox IGU1 Interrupt
- */
-#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
-
#endif // IFXMIPS_PTM_PPE_VR9_H
goto REGISTER_NETDEV_FAIL;
}
+ g_ptm_priv_data.irq = platform_get_irq(pdev, 0);
+ if (g_ptm_priv_data.irq < 0) {
+ err("platform_get_irq fail");
+ goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
+ }
+
/* register interrupt handler */
- ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data);
+ ret = request_irq(g_ptm_priv_data.irq, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data);
if ( ret ) {
if ( ret == -EBUSY ) {
err("IRQ may be occupied by other driver, please reconfig to disable it.");
}
goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
}
- disable_irq(PPE_MAILBOX_IGU1_INT);
+ disable_irq(g_ptm_priv_data.irq);
ret = ifx_pp32_start(0);
if ( ret ) {
IFX_REG_W32(1 << 16, MBOX_IGU1_IER); // enable SWAP interrupt
IFX_REG_W32(~0, MBOX_IGU1_ISRC);
- enable_irq(PPE_MAILBOX_IGU1_INT);
+ enable_irq(g_ptm_priv_data.irq);
ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);
if ( g_showtime ) {
return 0;
PP32_START_FAIL:
- free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
+ free_irq(g_ptm_priv_data.irq, &g_ptm_priv_data);
REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
i = ARRAY_SIZE(g_net_dev);
REGISTER_NETDEV_FAIL:
ifx_pp32_stop(0);
- free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
+ free_irq(g_ptm_priv_data.irq, &g_ptm_priv_data);
for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )
unregister_netdev(g_net_dev[i]);
#include "ifxmips_ptm_ppe_common.h"
#include "ifxmips_ptm_fw_regs_vdsl.h"
-#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24)
-
#define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r))
#define IFX_REG_R32(_r) __raw_readl((volatile unsigned int *)(_r))
#define IFX_REG_W32_MASK(_clr, _set, _r) IFX_REG_W32((IFX_REG_R32((_r)) & ~(_clr)) | (_set), (_r))
struct ptm_priv_data {
struct ptm_itf itf[MAX_ITF_NUMBER];
+ int irq;
};