+++ /dev/null
-From 943ed75a2a5ab08582d3bc8025e8111903698763 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Thu, 19 Nov 2020 17:43:15 +0200
-Subject: [PATCH 109/247] clk: at91: sama7g5: do not allow cpu pll to go higher
- than 1GHz
-
-Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher
-than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at
-1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/1605800597-16720-10-git-send-email-claudiu.beznea@microchip.com
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/sama7g5.c | 61 +++++++++++++++++++++++++++++---------
- 1 file changed, 47 insertions(+), 14 deletions(-)
-
---- a/drivers/clk/at91/sama7g5.c
-+++ b/drivers/clk/at91/sama7g5.c
-@@ -89,11 +89,40 @@ static const struct clk_pll_layout pll_l
- .endiv_shift = 30,
- };
-
-+/*
-+ * CPU PLL output range.
-+ * Notice: The upper limit has been setup to 1000000002 due to hardware
-+ * block which cannot output exactly 1GHz.
-+ */
-+static const struct clk_range cpu_pll_outputs[] = {
-+ { .min = 2343750, .max = 1000000002 },
-+};
-+
-+/* PLL output range. */
-+static const struct clk_range pll_outputs[] = {
-+ { .min = 2343750, .max = 1200000000 },
-+};
-+
-+/* CPU PLL characteristics. */
-+static const struct clk_pll_characteristics cpu_pll_characteristics = {
-+ .input = { .min = 12000000, .max = 50000000 },
-+ .num_output = ARRAY_SIZE(cpu_pll_outputs),
-+ .output = cpu_pll_outputs,
-+};
-+
-+/* PLL characteristics. */
-+static const struct clk_pll_characteristics pll_characteristics = {
-+ .input = { .min = 12000000, .max = 50000000 },
-+ .num_output = ARRAY_SIZE(pll_outputs),
-+ .output = pll_outputs,
-+};
-+
- /**
- * PLL clocks description
- * @n: clock name
- * @p: clock parent
- * @l: clock layout
-+ * @c: clock characteristics
- * @t: clock type
- * @f: clock flags
- * @eid: export index in sama7g5->chws[] array
-@@ -102,6 +131,7 @@ static const struct {
- const char *n;
- const char *p;
- const struct clk_pll_layout *l;
-+ const struct clk_pll_characteristics *c;
- unsigned long f;
- u8 t;
- u8 eid;
-@@ -110,6 +140,7 @@ static const struct {
- { .n = "cpupll_fracck",
- .p = "mainck",
- .l = &pll_layout_frac,
-+ .c = &cpu_pll_characteristics,
- .t = PLL_TYPE_FRAC,
- /*
- * This feeds cpupll_divpmcck which feeds CPU. It should
-@@ -120,6 +151,7 @@ static const struct {
- { .n = "cpupll_divpmcck",
- .p = "cpupll_fracck",
- .l = &pll_layout_divpmc,
-+ .c = &cpu_pll_characteristics,
- .t = PLL_TYPE_DIV,
- /* This feeds CPU. It should not be disabled. */
- .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
-@@ -130,6 +162,7 @@ static const struct {
- { .n = "syspll_fracck",
- .p = "mainck",
- .l = &pll_layout_frac,
-+ .c = &pll_characteristics,
- .t = PLL_TYPE_FRAC,
- /*
- * This feeds syspll_divpmcck which may feed critial parts
-@@ -141,6 +174,7 @@ static const struct {
- { .n = "syspll_divpmcck",
- .p = "syspll_fracck",
- .l = &pll_layout_divpmc,
-+ .c = &pll_characteristics,
- .t = PLL_TYPE_DIV,
- /*
- * This may feed critial parts of the systems like timers.
-@@ -154,6 +188,7 @@ static const struct {
- { .n = "ddrpll_fracck",
- .p = "mainck",
- .l = &pll_layout_frac,
-+ .c = &pll_characteristics,
- .t = PLL_TYPE_FRAC,
- /*
- * This feeds ddrpll_divpmcck which feeds DDR. It should not
-@@ -164,6 +199,7 @@ static const struct {
- { .n = "ddrpll_divpmcck",
- .p = "ddrpll_fracck",
- .l = &pll_layout_divpmc,
-+ .c = &pll_characteristics,
- .t = PLL_TYPE_DIV,
- /* This feeds DDR. It should not be disabled. */
- .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
-@@ -173,12 +209,14 @@ static const struct {
- { .n = "imgpll_fracck",
- .p = "mainck",
- .l = &pll_layout_frac,
-+ .c = &pll_characteristics,
- .t = PLL_TYPE_FRAC,
- .f = CLK_SET_RATE_GATE, },
-
- { .n = "imgpll_divpmcck",
- .p = "imgpll_fracck",
- .l = &pll_layout_divpmc,
-+ .c = &pll_characteristics,
- .t = PLL_TYPE_DIV,
- .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
- CLK_SET_RATE_PARENT, },
-@@ -188,12 +226,14 @@ static const struct {
- { .n = "baudpll_fracck",
- .p = "mainck",
- .l = &pll_layout_frac,
-+ .c = &pll_characteristics,
- .t = PLL_TYPE_FRAC,
- .f = CLK_SET_RATE_GATE, },
-
- { .n = "baudpll_divpmcck",
- .p = "baudpll_fracck",
- .l = &pll_layout_divpmc,
-+ .c = &pll_characteristics,
- .t = PLL_TYPE_DIV,
- .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
- CLK_SET_RATE_PARENT, },
-@@ -203,12 +243,14 @@ static const struct {
- { .n = "audiopll_fracck",
- .p = "main_xtal",
- .l = &pll_layout_frac,
-+ .c = &pll_characteristics,
- .t = PLL_TYPE_FRAC,
- .f = CLK_SET_RATE_GATE, },
-
- { .n = "audiopll_divpmcck",
- .p = "audiopll_fracck",
- .l = &pll_layout_divpmc,
-+ .c = &pll_characteristics,
- .t = PLL_TYPE_DIV,
- .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
- CLK_SET_RATE_PARENT,
-@@ -217,6 +259,7 @@ static const struct {
- { .n = "audiopll_diviock",
- .p = "audiopll_fracck",
- .l = &pll_layout_divio,
-+ .c = &pll_characteristics,
- .t = PLL_TYPE_DIV,
- .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
- CLK_SET_RATE_PARENT,
-@@ -227,12 +270,14 @@ static const struct {
- { .n = "ethpll_fracck",
- .p = "main_xtal",
- .l = &pll_layout_frac,
-+ .c = &pll_characteristics,
- .t = PLL_TYPE_FRAC,
- .f = CLK_SET_RATE_GATE, },
-
- { .n = "ethpll_divpmcck",
- .p = "ethpll_fracck",
- .l = &pll_layout_divpmc,
-+ .c = &pll_characteristics,
- .t = PLL_TYPE_DIV,
- .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
- CLK_SET_RATE_PARENT, },
-@@ -793,18 +838,6 @@ static const struct {
- .pp_chg_id = INT_MIN, },
- };
-
--/* PLL output range. */
--static const struct clk_range pll_outputs[] = {
-- { .min = 2343750, .max = 1200000000 },
--};
--
--/* PLL characteristics. */
--static const struct clk_pll_characteristics pll_characteristics = {
-- .input = { .min = 12000000, .max = 50000000 },
-- .num_output = ARRAY_SIZE(pll_outputs),
-- .output = pll_outputs,
--};
--
- /* MCK0 characteristics. */
- static const struct clk_master_characteristics mck0_characteristics = {
- .output = { .min = 50000000, .max = 200000000 },
-@@ -921,7 +954,7 @@ static void __init sama7g5_pmc_setup(str
- hw = sam9x60_clk_register_frac_pll(regmap,
- &pmc_pll_lock, sama7g5_plls[i][j].n,
- sama7g5_plls[i][j].p, parent_hw, i,
-- &pll_characteristics,
-+ sama7g5_plls[i][j].c,
- sama7g5_plls[i][j].l,
- sama7g5_plls[i][j].f);
- break;
-@@ -930,7 +963,7 @@ static void __init sama7g5_pmc_setup(str
- hw = sam9x60_clk_register_div_pll(regmap,
- &pmc_pll_lock, sama7g5_plls[i][j].n,
- sama7g5_plls[i][j].p, i,
-- &pll_characteristics,
-+ sama7g5_plls[i][j].c,
- sama7g5_plls[i][j].l,
- sama7g5_plls[i][j].f);
- break;
projects / openwrt / openwrt.git / blobdiff