at91: kernel v5.15: copy config and patches from 5.10

[openwrt/openwrt.git] / target / linux / at91 / patches-5.15 / 205-ARM-at91-pm-add-support-for-waiting-MCK1.4.patch

diff --git a/target/linux/at91/patches-5.15/205-ARM-at91-pm-add-support-for-waiting-MCK1.4.patch b/target/linux/at91/patches-5.15/205-ARM-at91-pm-add-support-for-waiting-MCK1.4.patch
new file mode 100644 (file)
index 0000000..16e7337
--- /dev/null
+++ b/target/linux/at91/patches-5.15/205-ARM-at91-pm-add-support-for-waiting-MCK1.4.patch
@@ -0,0 +1,150 @@
+From 67face049c62cb37cf93da26b7fea037228d1d3d Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <claudiu.beznea@microchip.com>
+Date: Thu, 15 Apr 2021 13:49:55 +0300
+Subject: [PATCH 205/247] ARM: at91: pm: add support for waiting MCK1..4
+
+SAMA7G5 has 5 master clocks 0..4. MCK0 is controlled differently than
+MCK 1..4. MCK 1..4 should also be saved/restored in the last phase of
+suspend/resume. Thus, adapt wait_mckrdy to support also MCK1..4.
+
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
+Link: https://lore.kernel.org/r/20210415105010.569620-10-claudiu.beznea@microchip.com
+---
+ arch/arm/mach-at91/pm_suspend.S | 48 ++++++++++++++++++++++++---------
+ 1 file changed, 35 insertions(+), 13 deletions(-)
+
+--- a/arch/arm/mach-at91/pm_suspend.S
++++ b/arch/arm/mach-at91/pm_suspend.S
+@@ -22,11 +22,23 @@ tmp3       .req    r6
+ 
+ /*
+  * Wait until master clock is ready (after switching master clock source)
++ *
++ * @r_mckid:  register holding master clock identifier
++ *
++ * Side effects: overwrites r7, r8
+  */
+-      .macro wait_mckrdy
+-1:    ldr     tmp1, [pmc, #AT91_PMC_SR]
+-      tst     tmp1, #AT91_PMC_MCKRDY
+-      beq     1b
++      .macro wait_mckrdy r_mckid
++#ifdef CONFIG_SOC_SAMA7
++      cmp     \r_mckid, #0
++      beq     1f
++      mov     r7, #AT91_PMC_MCKXRDY
++      b       2f
++#endif
++1:    mov     r7, #AT91_PMC_MCKRDY
++2:    ldr     r8, [pmc, #AT91_PMC_SR]
++      and     r8, r7
++      cmp     r8, r7
++      bne     2b
+       .endm
+ 
+ /*
+@@ -231,7 +243,9 @@ sr_dis_exit:
+       bic     tmp1, tmp1, #AT91_PMC_PRES
+       orr     tmp1, tmp1, #AT91_PMC_PRES_64
+       str     tmp1, [pmc, tmp3]
+-      wait_mckrdy
++
++      mov     tmp3, #0
++      wait_mckrdy tmp3
+       b       1f
+ 
+ 0:
+@@ -267,10 +281,13 @@ sr_dis_exit:
+       bne     5f
+ 
+       /* Set lowest prescaler for fast resume. */
++      ldr     tmp3, .mckr_offset
+       ldr     tmp1, [pmc, tmp3]
+       bic     tmp1, tmp1, #AT91_PMC_PRES
+       str     tmp1, [pmc, tmp3]
+-      wait_mckrdy
++
++      mov     tmp3, #0
++      wait_mckrdy tmp3
+       b       6f
+ 
+ 5:    /* Restore RC oscillator state */
+@@ -307,6 +324,7 @@ sr_dis_exit:
+ .macro at91_pm_ulp1_mode
+       ldr     pmc, .pmc_base
+       ldr     tmp2, .mckr_offset
++      mov     tmp3, #0
+ 
+       /* Save RC oscillator state and check if it is enabled. */
+       ldr     tmp1, [pmc, #AT91_PMC_SR]
+@@ -348,7 +366,7 @@ sr_dis_exit:
+       orr     tmp1, tmp1, #AT91_PMC_CSS_MAIN
+       str     tmp1, [pmc, tmp2]
+ 
+-      wait_mckrdy
++      wait_mckrdy tmp3
+ 
+       /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
+       ldr     tmp1, [pmc, #AT91_CKGR_MOR]
+@@ -361,7 +379,7 @@ sr_dis_exit:
+       nop
+       nop
+ 
+-      wait_mckrdy
++      wait_mckrdy tmp3
+ 
+       /* Enable the crystal oscillator */
+       ldr     tmp1, [pmc, #AT91_CKGR_MOR]
+@@ -377,7 +395,7 @@ sr_dis_exit:
+       bic     tmp1, tmp1, #AT91_PMC_CSS
+       str     tmp1, [pmc, tmp2]
+ 
+-      wait_mckrdy
++      wait_mckrdy tmp3
+ 
+       /* Switch main clock source to crystal oscillator */
+       ldr     tmp1, [pmc, #AT91_CKGR_MOR]
+@@ -394,7 +412,7 @@ sr_dis_exit:
+       orr     tmp1, tmp1, #AT91_PMC_CSS_MAIN
+       str     tmp1, [pmc, tmp2]
+ 
+-      wait_mckrdy
++      wait_mckrdy tmp3
+ 
+       /* Restore RC oscillator state */
+       ldr     tmp1, .saved_osc_status
+@@ -573,10 +591,12 @@ sr_dis_exit:
+ save_mck:
+       str     tmp1, [pmc, tmp2]
+ 
+-      wait_mckrdy
++      mov     tmp3, #0
++      wait_mckrdy tmp3
+ 
+       at91_plla_disable
+ 
++      ldr     tmp3, .pm_mode
+       cmp     tmp3, #AT91_PM_ULP1
+       beq     ulp1_mode
+ 
+@@ -599,7 +619,8 @@ ulp_exit:
+       ldr     tmp2, .saved_mckr
+       str     tmp2, [pmc, tmp1]
+ 
+-      wait_mckrdy
++      mov     tmp3, #0
++      wait_mckrdy tmp3
+ 
+ .endm
+ 
+@@ -611,7 +632,8 @@ ulp_exit:
+       bic     tmp1, tmp1, #AT91_PMC_CSS
+       str     tmp1, [pmc, tmp2]
+ 
+-      wait_mckrdy
++      mov     tmp3, #0
++      wait_mckrdy tmp3
+ 
+       /*BUMEN*/
+       ldr     r0, .sfrbu