ath79: add support for Huawei AP5030DN

[openwrt/openwrt.git] / target / linux / ath79 / dts / qca9550_huawei_ap5030dn.dts

diff --git a/target/linux/ath79/dts/qca9550_huawei_ap5030dn.dts b/target/linux/ath79/dts/qca9550_huawei_ap5030dn.dts
new file mode 100644 (file)
index 0000000..1c2a75f
--- /dev/null
+++ b/target/linux/ath79/dts/qca9550_huawei_ap5030dn.dts
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca955x.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+       model = "Huawei AP5030DN";
+       compatible = "huawei,ap5030dn", "qca,qca9550", "qca,qca9558";
+
+       chosen {
+               bootargs = "console=ttyS0,9600n8";
+       };
+
+       aliases {
+               led-boot = &led_function_red;
+               led-failsafe = &led_function_red;
+               led-running = &led_function_green;
+               led-upgrade = &led_function_red;
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               led_function_green: led-status-red {
+                       function = LED_FUNCTION_STATUS;
+                       color = <LED_COLOR_ID_GREEN>;
+                       gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
+               };
+
+               led_function_red: led-status-green {
+                       function = LED_FUNCTION_STATUS;
+                       color = <LED_COLOR_ID_RED>;
+                       gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
+               };
+
+       };
+
+       keys {
+               compatible = "gpio-keys";
+
+               restart {
+                       label = "reset";
+                       linux,code = <KEY_RESTART>;
+                       gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
+                       debounce-interval = <60>;
+               };
+       };
+
+       watchdog {
+               pinctrl-names = "default";
+               pinctrl-0 = <&wdt_gpio15>;
+
+               compatible = "linux,wdt-gpio";
+               gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
+               hw_algo = "toggle";
+               hw_margin_ms = <100>;
+               always-running;
+       };
+
+       virtual_flash {
+               compatible = "mtd-concat";
+               devices = <&fwconcat0 &fwconcat1>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "firmware";
+                               reg = <0x0 0x1e00000>;
+                               compatible = "openwrt,uimage", "denx,uimage";
+                       };
+               };
+       };
+};
+
+&spi {
+       status = "okay";
+
+       flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <25000000>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "u-boot-a";
+                               reg = <0x0 0x80000>;
+                               read-only;
+                       };
+
+                       // The BootupA/B partitions store the addresses
+                       // of the main and backup kernel in flash (which is the same here).
+                       // During sysupgrade, these addresses are set to the start of the
+                       // "firmware" partition.
+                       partition@80000 {
+                               label = "BootupA";
+                               reg = <0x80000 0x20000>;
+                       };
+
+                       partition@a0000 {
+                               label = "BootupB";
+                               reg = <0xa0000 0x20000>;
+                       };
+
+                       partition@c0000 {
+                               label = "u-boot-env";
+                               reg = <0xc0000 0x20000>;
+                               read-only;
+                       };
+
+                       partition@e0000 {
+                               label = "BoardData";
+                               reg = <0xe0000 0x20000>;
+                               read-only;
+                       };
+
+                       // In the vendor layout, there are the "SysImageA" (12 MiB)
+                       // and the "ConfigA" (3 MiB) partitions here.
+                       fwconcat0: partition@100000 {
+                               label = "fwconcat0";
+                               reg = <0x100000 0xF00000>;
+                       };
+
+                       partition@1000000 {
+                               label = "u-boot-b";
+                               reg = <0x1000000 0x80000>;
+                               read-only;
+                       };
+
+                       partition@1080000 {
+                               label = "ResultA";
+                               reg = <0x1080000 0x20000>;
+                               read-only;
+                       };
+
+                       partition@10a0000 {
+                               label = "ResultB";
+                               reg = <0x10a0000 0x20000>;
+                               read-only;
+                       };
+
+                       // In the vendor layout, there are the "SysImageB" (12 MiB)
+                       // and the "ConfigB" (3 MiB) partitions here.
+                       fwconcat1: partition@10c0000 {
+                               label = "fwconcat1";
+                               reg = <0x10c0000 0xF00000>;
+                       };
+
+                       art: partition@1fc0000 {
+                               label = "art";
+                               reg = <0x1fc0000 0x40000>;
+                               read-only;
+
+                               nvmem-layout {
+                                       compatible = "fixed-layout";
+                                       #address-cells = <1>;
+                                       #size-cells = <1>;
+
+                                       macaddr_art_2005b: macaddr@2005b {
+                                               compatible = "mac-base";
+                                               reg = <0x2005b 0x6>;
+                                               #nvmem-cell-cells = <1>;
+                                       };
+
+                                       cal_art_1000: cal@1000 {
+                                               reg = <0x1000 0x440>;
+                                       };
+
+                                       cal_art_5000: cal@5000 {
+                                               reg = <0x5000 0x844>;
+                                       };
+                               };
+                       };
+               };
+       };
+};
+
+&wmac {
+       status = "okay";
+
+       nvmem-cells = <&macaddr_art_2005b 3>, <&cal_art_1000>;
+       nvmem-cell-names = "mac-address", "calibration";
+};
+
+&pcie0 {
+       status = "okay";
+
+       wifi@0,0 {
+               compatible = "qcom,ath10k";
+               reg = <0x0000 0 0 0 0>;
+               nvmem-cells = <&macaddr_art_2005b 2>, <&cal_art_5000>;
+               nvmem-cell-names = "mac-address", "calibration";
+       };
+};
+
+&eth0 {
+       status = "okay";
+
+       nvmem-cells = <&macaddr_art_2005b 0>;
+       nvmem-cell-names = "mac-address";
+
+       pll-data = <0xa6000000 0xa0000101 0xa0001313>;
+       phy-handle = <&phy0>;
+
+       gmac-config {
+               device = <&gmac>;
+               rxdv-delay = <3>;
+               rxd-delay = <3>;
+               txen-delay = <0>;
+               txd-delay = <0>;
+       };
+};
+
+&eth1 {
+       status = "okay";
+
+       nvmem-cells = <&macaddr_art_2005b 1>;
+       nvmem-cell-names = "mac-address";
+
+       pll-data = <0x03000101 0x00000101 0x00001313>;
+       phy-handle = <&phy1>;
+};
+
+&mdio0 {
+       status = "okay";
+
+       phy0: ethernet-phy@18 {
+               reg = <0x18>;
+       };
+};
+
+&mdio1 {
+       status = "okay";
+
+       phy1: ethernet-phy@1 {
+               reg = <1>;
+       };
+};
+
+&pinmux {
+       wdt_gpio15: pinmux_wdt_gpio15 {
+               pinctrl-single,bits = <0xc 0x0 0xFF000000>;
+       };
+};
+
+&wdt {
+       status = "disabled";
+};