--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
+// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
+// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
+
+#include "qcom-ipq4018-mf287_common.dtsi"
+
+/ {
+ model = "ZTE MF287Pro";
+ compatible = "zte,mf287pro";
+
+ regulator-usb-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_VBUS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&tlmm 25 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&gpio_modem_reset {
+ gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
+};
+
+&key_reset {
+ gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+};
+
+&key_wps {
+ gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
+};
+
+&led_status {
+ gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+};
+
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2000>;
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>,
+ <&tlmm 54 GPIO_ACTIVE_HIGH>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:SBL1";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+
+ partition@40000 {
+ label = "0:MIBIB";
+ reg = <0x40000 0x20000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "0:QSEE";
+ reg = <0x60000 0x60000>;
+ read-only;
+ };
+
+ partition@c0000 {
+ label = "0:CDT";
+ reg = <0xc0000 0x10000>;
+ read-only;
+ };
+
+ partition@d0000 {
+ label = "0:DDRPARAMS";
+ reg = <0xd0000 0x10000>;
+ read-only;
+ };
+
+ partition@e0000 {
+ label = "0:APPSBLENV";
+ reg = <0xe0000 0x10000>;
+ read-only;
+ };
+
+ partition@f0000 {
+ label = "0:APPSBL";
+ reg = <0xf0000 0xc0000>;
+ read-only;
+ };
+
+ partition@1b0000 {
+ label = "0:reserved1";
+ reg = <0x1b0000 0x50000>;
+ read-only;
+ };
+ };
+ };
+
+ spi-nand@1 { /* flash@1 ? */
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "fota-flag";
+ reg = <0x0 0xa0000>;
+ read-only;
+ };
+
+ partition@a0000 {
+ label = "ART";
+ reg = <0xa0000 0x80000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ precal_art_1000: precal@1000 {
+ reg = <0x1000 0x2f20>;
+ };
+
+ precal_art_5000: precal@5000 {
+ reg = <0x5000 0x2f20>;
+ };
+ };
+ };
+
+ partition@120000 {
+ label = "mac";
+ reg = <0x120000 0x80000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_mac_0: macaddr@0 {
+ compatible = "mac-base";
+ reg = <0x0 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
+
+ partition@1a0000 {
+ label = "reserved2";
+ reg = <0x1a0000 0xc0000>;
+ };
+
+ partition@260000 {
+ label = "cfg-param";
+ reg = <0x260000 0x400000>;
+ read-only;
+ };
+
+ partition@660000 {
+ label = "log";
+ reg = <0x660000 0x400000>;
+ };
+
+ partition@a60000 {
+ label = "oops";
+ reg = <0xa60000 0xa0000>;
+ };
+
+ partition@b00000 {
+ label = "reserved3";
+ reg = <0xb00000 0x500000>;
+ };
+
+ partition@1000000 {
+ label = "web";
+ reg = <0x1000000 0x800000>;
+ };
+
+ partition@1800000 {
+ label = "rootfs";
+ reg = <0x1800000 0x1d00000>;
+ };
+
+ partition@3500000 {
+ label = "data";
+ reg = <0x3500000 0x1900000>;
+ };
+
+ partition@4e00000 {
+ label = "fota";
+ reg = <0x4e00000 0x3200000>;
+ };
+ };
+ };
+};
+
+&tlmm {
+ i2c_0_pins: i2c_0_pinmux {
+ mux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
+ };
+ };
+
+ mdio_pins: mdio_pinmux {
+ mux_1 {
+ pins = "gpio6";
+ function = "mdio";
+ bias-pull-up;
+ };
+
+ mux_2 {
+ pins = "gpio7";
+ function = "mdc";
+ bias-pull-up;
+ };
+ };
+
+ serial_pins: serial_pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio12", "gpio13", "gpio14", "gpio15";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12", "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+/* The MF287Plus and MF287Pro share the same board data file */
+&wifi0 {
+ qcom,ath10k-calibration-variant = "zte,mf287plus";
+};
+
+/* The MF287Plus and MF287Pro share the same board data file */
+&wifi1{
+ qcom,ath10k-calibration-variant = "zte,mf287plus";
+};
projects / openwrt / openwrt.git / blobdiff