ramips: set clk_is_20mhz for rt2x00 on RT3352/RT5350

[openwrt/openwrt.git] / target / linux / ramips / files / arch / mips / include / asm / mach-ralink / rt305x_regs.h

diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
index 949232dbd2fc3051aecc6c18a990ccd09b3a1218..943facb6de0a0f76827d09ddb0b4dd44656f83e3 100644 (file)
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
@@ -111,6 +111,8 @@
 #define RT5350_SYSCFG0_DRAM_SIZE_32M   3
 #define RT5350_SYSCFG0_DRAM_SIZE_64M   4
 
+#define RT3352_SYSCFG0_XTAL_SEL                BIT(20)
+
 #define RT3352_SYSCFG1_USB0_HOST_MODE  BIT(10)
 
 #define RT3352_CLKCFG1_UPHY0_CLK_EN    BIT(18)