ramips: manage low reset lines

[openwrt/openwrt.git] / target / linux / ramips / patches-5.4 / 0123-mips-ralink-manage-low-reset-lines.patch

diff --git a/target/linux/ramips/patches-5.4/0123-mips-ralink-manage-low-reset-lines.patch b/target/linux/ramips/patches-5.4/0123-mips-ralink-manage-low-reset-lines.patch
new file mode 100644 (file)
index 0000000..e59044d
--- /dev/null
+++ b/target/linux/ramips/patches-5.4/0123-mips-ralink-manage-low-reset-lines.patch
@@ -0,0 +1,47 @@
+From 3f9ef7785a9cd69cb75f5e2ea4ca79a24752e496 Mon Sep 17 00:00:00 2001
+From: Sander Vanheule <sander@svanheule.net>
+Date: Wed, 3 Feb 2021 10:21:41 +0100
+Subject: MIPS: ralink: manage low reset lines
+
+Reset lines with indices smaller than 8 are currently considered invalid
+by the rt2880-reset reset controller.
+
+The MT7621 SoC uses a number of these low reset lines. The DTS defines
+reset lines "hsdma", "fe", and "mcm" with respective values 5, 6, and 2.
+As a result of the above restriction, these resets cannot be asserted or
+de-asserted by the reset controller. In cases where the bootloader does
+not de-assert these lines, this results in e.g. the MT7621's internal
+switch staying in reset.
+
+Change the reset controller to only ignore the system reset, so all
+reset lines with index greater than 0 are considered valid.
+
+Signed-off-by: Sander Vanheule <sander@svanheule.net>
+Acked-by: John Crispin <john@phrozen.org>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ arch/mips/ralink/reset.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c
+index 8126f12604071..274d33078c5eb 100644
+--- a/arch/mips/ralink/reset.c
++++ b/arch/mips/ralink/reset.c
+@@ -27,7 +27,7 @@ static int ralink_assert_device(struct reset_controller_dev *rcdev,
+ {
+       u32 val;
+ 
+-      if (id < 8)
++      if (id == 0)
+               return -1;
+ 
+       val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
+@@ -42,7 +42,7 @@ static int ralink_deassert_device(struct reset_controller_dev *rcdev,
+ {
+       u32 val;
+ 
+-      if (id < 8)
++      if (id == 0)
+               return -1;
+ 
+       val = rt_sysc_r32(SYSC_REG_RESET_CTRL);