kernel/ramips: Create kernel patches for v6.6 (from v6.1)

[openwrt/openwrt.git] / target / linux / ramips / patches-6.1 / 005-v6.5-05-mips-ralink-rt3883-remove-clock-related-code.patch

diff --git a/target/linux/ramips/patches-6.1/005-v6.5-05-mips-ralink-rt3883-remove-clock-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-05-mips-ralink-rt3883-remove-clock-related-code.patch
deleted file mode 100644 (file)
index c13c421..0000000
--- a/target/linux/ramips/patches-6.1/005-v6.5-05-mips-ralink-rt3883-remove-clock-related-code.patch
+++ /dev/null
@@ -1,85 +0,0 @@
-From 7cd1bb48885449a9323c7ff0f10012925e93b4e1 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:37 +0200
-Subject: [PATCH 5/9] mips: ralink: rt3883: remove clock related code
-
-A properly clock driver for ralink SoCs has been added. Hence there is no
-need to have clock related code in 'arch/mips/ralink' folder anymore.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/include/asm/mach-ralink/rt3883.h |  8 ------
- arch/mips/ralink/rt3883.c                  | 44 ------------------------------
- 2 files changed, 52 deletions(-)
-
---- a/arch/mips/include/asm/mach-ralink/rt3883.h
-+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
-@@ -90,14 +90,6 @@
- #define RT3883_REVID_VER_ID_SHIFT     8
- #define RT3883_REVID_ECO_ID_MASK      0x0f
- 
--#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
--#define RT3883_SYSCFG0_CPUCLK_SHIFT   8
--#define RT3883_SYSCFG0_CPUCLK_MASK    0x3
--#define RT3883_SYSCFG0_CPUCLK_250     0x0
--#define RT3883_SYSCFG0_CPUCLK_384     0x1
--#define RT3883_SYSCFG0_CPUCLK_480     0x2
--#define RT3883_SYSCFG0_CPUCLK_500     0x3
--
- #define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
- #define RT3883_SYSCFG1_PCIE_RC_MODE   BIT(8)
- #define RT3883_SYSCFG1_PCI_HOST_MODE  BIT(7)
---- a/arch/mips/ralink/rt3883.c
-+++ b/arch/mips/ralink/rt3883.c
-@@ -17,50 +17,6 @@
- 
- #include "common.h"
- 
--void __init ralink_clk_init(void)
--{
--      unsigned long cpu_rate, sys_rate;
--      u32 syscfg0;
--      u32 clksel;
--      u32 ddr2;
--
--      syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
--      clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
--              RT3883_SYSCFG0_CPUCLK_MASK);
--      ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
--
--      switch (clksel) {
--      case RT3883_SYSCFG0_CPUCLK_250:
--              cpu_rate = 250000000;
--              sys_rate = (ddr2) ? 125000000 : 83000000;
--              break;
--      case RT3883_SYSCFG0_CPUCLK_384:
--              cpu_rate = 384000000;
--              sys_rate = (ddr2) ? 128000000 : 96000000;
--              break;
--      case RT3883_SYSCFG0_CPUCLK_480:
--              cpu_rate = 480000000;
--              sys_rate = (ddr2) ? 160000000 : 120000000;
--              break;
--      case RT3883_SYSCFG0_CPUCLK_500:
--              cpu_rate = 500000000;
--              sys_rate = (ddr2) ? 166000000 : 125000000;
--              break;
--      }
--
--      ralink_clk_add("cpu", cpu_rate);
--      ralink_clk_add("10000100.timer", sys_rate);
--      ralink_clk_add("10000120.watchdog", sys_rate);
--      ralink_clk_add("10000500.uart", 40000000);
--      ralink_clk_add("10000900.i2c", 40000000);
--      ralink_clk_add("10000a00.i2s", 40000000);
--      ralink_clk_add("10000b00.spi", sys_rate);
--      ralink_clk_add("10000b40.spi", sys_rate);
--      ralink_clk_add("10000c00.uartlite", 40000000);
--      ralink_clk_add("10100000.ethernet", sys_rate);
--      ralink_clk_add("10180000.wmac", 40000000);
--}
--
- void __init ralink_of_remap(void)
- {
-       rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");