sunxi: initial 3.14 patchset

[openwrt/openwrt.git] / target / linux / sunxi / patches-3.14 / 188-clk-sunxi-implement-mmc-phasectrl.patch

diff --git a/target/linux/sunxi/patches-3.14/188-clk-sunxi-implement-mmc-phasectrl.patch b/target/linux/sunxi/patches-3.14/188-clk-sunxi-implement-mmc-phasectrl.patch
new file mode 100644 (file)
index 0000000..1288f8f
--- /dev/null
+++ b/target/linux/sunxi/patches-3.14/188-clk-sunxi-implement-mmc-phasectrl.patch
@@ -0,0 +1,95 @@
+From 36268d704307282109ec246f65cac2a42c825629 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
+Date: Fri, 20 Sep 2013 20:29:17 -0300
+Subject: [PATCH] clk: sunxi: Implement MMC phase control
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+HdG: add header exporting clk_sunxi_mmc_phase_control
+
+Signed-off-by: Emilio López <emilio@elopez.com.ar>
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+---
+ drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++
+ include/linux/clk/sunxi.h     | 22 ++++++++++++++++++++++
+ 2 files changed, 57 insertions(+)
+ create mode 100644 include/linux/clk/sunxi.h
+
+diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
+index 23baad9..9afd8dd 100644
+--- a/drivers/clk/sunxi/clk-sunxi.c
++++ b/drivers/clk/sunxi/clk-sunxi.c
+@@ -507,6 +507,41 @@ CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
+ 
+ 
+ /**
++ * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
++ */
++
++void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
++{
++      #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
++      #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
++
++      struct clk_composite *composite = to_clk_composite(hw);
++      struct clk_hw *rate_hw = composite->rate_hw;
++      struct clk_factors *factors = to_clk_factors(rate_hw);
++      unsigned long flags = 0;
++      u32 reg;
++
++      if (factors->lock)
++              spin_lock_irqsave(factors->lock, flags);
++
++      reg = readl(factors->reg);
++
++      /* set sample clock phase control */
++      reg &= ~(0x7 << 20);
++      reg |= ((sample & 0x7) << 20);
++
++      /* set output clock phase control */
++      reg &= ~(0x7 << 8);
++      reg |= ((output & 0x7) << 8);
++
++      writel(reg, factors->reg);
++
++      if (factors->lock)
++              spin_unlock_irqrestore(factors->lock, flags);
++}
++
++
++/**
+  * sunxi_factors_clk_setup() - Setup function for factor clocks
+  */
+ 
+diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
+new file mode 100644
+index 0000000..1ef5c89
+--- /dev/null
++++ b/include/linux/clk/sunxi.h
+@@ -0,0 +1,22 @@
++/*
++ * Copyright 2013 - Hans de Goede <hdegoede@redhat.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef __LINUX_CLK_SUNXI_H_
++#define __LINUX_CLK_SUNXI_H_
++
++#include <linux/clk.h>
++
++void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output);
++
++#endif
+-- 
+2.0.3
+