X-Git-Url: http://git.openwrt.org/?p=openwrt%2Fopenwrt.git;a=blobdiff_plain;f=target%2Flinux%2Fat91%2Fpatches-5.15%2F140-drivers-soc-atmel-add-support-for-sama7g5.patch;fp=target%2Flinux%2Fat91%2Fpatches-5.15%2F140-drivers-soc-atmel-add-support-for-sama7g5.patch;h=3b21017673261dc7993dc878c7d270c4c2b5f27a;hp=0000000000000000000000000000000000000000;hb=eb758a8fec2cee24e528008052fa2bd58482ca3a;hpb=c5c37886cff1705ba9be9b33df3ab121bd27fe6b

diff --git a/target/linux/at91/patches-5.15/140-drivers-soc-atmel-add-support-for-sama7g5.patch b/target/linux/at91/patches-5.15/140-drivers-soc-atmel-add-support-for-sama7g5.patch
new file mode 100644
index 0000000000..3b21017673
--- /dev/null
+++ b/target/linux/at91/patches-5.15/140-drivers-soc-atmel-add-support-for-sama7g5.patch
@@ -0,0 +1,87 @@
+From e20bb57fc51741677a6fcae04e564797fd18921b Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <claudiu.beznea@microchip.com>
+Date: Fri, 22 Jan 2021 14:21:37 +0200
+Subject: [PATCH 140/247] drivers: soc: atmel: add support for sama7g5
+
+Add support for SAMA7G5 SoCs.
+
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
+Link: https://lore.kernel.org/r/1611318097-8970-8-git-send-email-claudiu.beznea@microchip.com
+---
+ drivers/soc/atmel/soc.c | 18 ++++++++++++++++++
+ drivers/soc/atmel/soc.h |  6 ++++++
+ 2 files changed, 24 insertions(+)
+
+--- a/drivers/soc/atmel/soc.c
++++ b/drivers/soc/atmel/soc.c
+@@ -27,8 +27,10 @@
+ #define AT91_CHIPID_EXID		0x04
+ #define AT91_CIDR_VERSION(x, m)		((x) & (m))
+ #define AT91_CIDR_VERSION_MASK		GENMASK(4, 0)
++#define AT91_CIDR_VERSION_MASK_SAMA7G5	GENMASK(3, 0)
+ #define AT91_CIDR_EXT			BIT(31)
+ #define AT91_CIDR_MATCH_MASK		GENMASK(30, 5)
++#define AT91_CIDR_MASK_SAMA7G5		GENMASK(27, 5)
+ 
+ static const struct at91_soc socs[] __initconst = {
+ #ifdef CONFIG_SOC_AT91RM9200
+@@ -221,6 +223,20 @@ static const struct at91_soc socs[] __in
+ 		 AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH,
+ 		 "samv70q19", "samv7"),
+ #endif
++#ifdef CONFIG_SOC_SAMA7
++	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH,
++		 "sama7g51", "sama7g5"),
++	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G52_EXID_MATCH,
++		 "sama7g52", "sama7g5"),
++	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G53_EXID_MATCH,
++		 "sama7g53", "sama7g5"),
++	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH,
++		 "sama7g54", "sama7g5"),
++#endif
+ 	{ /* sentinel */ },
+ };
+ 
+@@ -258,6 +274,7 @@ static int __init at91_get_cidr_exid_fro
+ 	void __iomem *regs;
+ 	static const struct of_device_id chipids[] = {
+ 		{ .compatible = "atmel,sama5d2-chipid" },
++		{ .compatible = "microchip,sama7g5-chipid" },
+ 		{ },
+ 	};
+ 
+@@ -345,6 +362,7 @@ static const struct of_device_id at91_so
+ 	{ .compatible = "atmel,at91sam9", },
+ 	{ .compatible = "atmel,sama5", },
+ 	{ .compatible = "atmel,samv7", },
++	{ .compatible = "microchip,sama7g5", },
+ 	{ }
+ };
+ 
+--- a/drivers/soc/atmel/soc.h
++++ b/drivers/soc/atmel/soc.h
+@@ -48,6 +48,7 @@ at91_soc_init(const struct at91_soc *soc
+ #define AT91SAM9X5_CIDR_MATCH		0x019a05a0
+ #define AT91SAM9N12_CIDR_MATCH		0x019a07a0
+ #define SAM9X60_CIDR_MATCH		0x019b35a0
++#define SAMA7G5_CIDR_MATCH		0x00162100
+ 
+ #define AT91SAM9M11_EXID_MATCH		0x00000001
+ #define AT91SAM9M10_EXID_MATCH		0x00000002
+@@ -69,6 +70,11 @@ at91_soc_init(const struct at91_soc *soc
+ #define SAM9X60_D1G_EXID_MATCH		0x00000010
+ #define SAM9X60_D6K_EXID_MATCH		0x00000011
+ 
++#define SAMA7G51_EXID_MATCH		0x3
++#define SAMA7G52_EXID_MATCH		0x2
++#define SAMA7G53_EXID_MATCH		0x1
++#define SAMA7G54_EXID_MATCH		0x0
++
+ #define AT91SAM9XE128_CIDR_MATCH	0x329973a0
+ #define AT91SAM9XE256_CIDR_MATCH	0x329a93a0
+ #define AT91SAM9XE512_CIDR_MATCH	0x329aa3a0