ramips: add proper system clock and reset driver support for mt7621
authorShiji Yang <yangshiji66@qq.com>
Sat, 17 Jun 2023 11:30:59 +0000 (19:30 +0800)
committerNick Hainke <vincent@systemli.org>
Sun, 30 Jul 2023 11:09:23 +0000 (13:09 +0200)
commit8cacf2bda8009f07715a9617be6b26e53c5443bd
treec0da854cb93d4f81369f5145422e70575fe44dd1
parentdf47decd60808d099e663b32f60795f629ee81e3
ramips: add proper system clock and reset driver support for mt7621

This series of upstream patches makes the system controller node as a
reset provider[1][2], and it also includes some clock and reset driver
fixes[3][4]. Meanwhile, all clocks and resets properties in the SoC
device tree have been updated to be compatible with the new driver.

[1] https://lore.kernel.org/r/20220110114930.1406665-2-sergio.paracuellos@gmail.com
[2] https://lore.kernel.org/r/20220210094859.927868-2-sergio.paracuellos@gmail.com
[3] https://lore.kernel.org/r/20221217074806.3225150-1-sergio.paracuellos@gmail.com
[4] https://lore.kernel.org/r/20230206083305.147582-1-sergio.paracuellos@gmail.com

Tested on RAISECOM MSG1500 X.00

Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
target/linux/ramips/dts/mt7621.dtsi
target/linux/ramips/patches-5.15/000-v5.18-01-dt-bindings-reset-add-dt-binding-header-for-Mediatek.patch [new file with mode: 0644]
target/linux/ramips/patches-5.15/000-v5.18-02-staging-mt7621-dts-align-resets-with-binding-documen.patch [new file with mode: 0644]
target/linux/ramips/patches-5.15/001-v5.18-01-dt-bindings-clock-mediatek-mt7621-sysc-add-reset-cel.patch [new file with mode: 0644]
target/linux/ramips/patches-5.15/001-v5.18-02-clk-ralink-make-system-controller-node-a-reset-provi.patch [new file with mode: 0644]
target/linux/ramips/patches-5.15/002-v6.0-MIPS-ralink-mt7621-avoid-to-init-common-ralink-reset.patch [new file with mode: 0644]
target/linux/ramips/patches-5.15/003-v6.3-clk-ralink-fix-mt7621_gate_is_enabled-function.patch [new file with mode: 0644]