ath79: ag71xx: apply interface mode to MII0/1_CTRL on ar71xx/ar913x

[openwrt/staging/chunkeey.git] / target / linux / ath79 / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c

diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
index 1e0bb6937f1bccac658c298daaca1ad97b8f28e5..d029197d4ce26612ce3160a64ed8190d8efc81f0 100644 (file)
--- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
+++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
@@ -529,6 +529,60 @@ static void ath79_set_pll(struct ag71xx *ag)
        udelay(100);
 }
 
+static void ath79_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)
+{
+       u32 t;
+
+       t = __raw_readl(ag->mii_base);
+       t &= ~(AR71XX_MII_CTRL_IF_MASK);
+       t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
+       __raw_writel(t, ag->mii_base);
+}
+
+static void ath79_mii0_ctrl_set_if(struct ag71xx *ag)
+{
+       unsigned int mii_if;
+
+       switch (ag->phy_if_mode) {
+       case PHY_INTERFACE_MODE_MII:
+               mii_if = AR71XX_MII0_CTRL_IF_MII;
+               break;
+       case PHY_INTERFACE_MODE_GMII:
+               mii_if = AR71XX_MII0_CTRL_IF_GMII;
+               break;
+       case PHY_INTERFACE_MODE_RGMII:
+               mii_if = AR71XX_MII0_CTRL_IF_RGMII;
+               break;
+       case PHY_INTERFACE_MODE_RMII:
+               mii_if = AR71XX_MII0_CTRL_IF_RMII;
+               break;
+       default:
+               WARN(1, "Impossible PHY mode defined.\n");
+               return;
+       }
+
+       ath79_mii_ctrl_set_if(ag, mii_if);
+}
+
+static void ath79_mii1_ctrl_set_if(struct ag71xx *ag)
+{
+       unsigned int mii_if;
+
+       switch (ag->phy_if_mode) {
+       case PHY_INTERFACE_MODE_RMII:
+               mii_if = AR71XX_MII1_CTRL_IF_RMII;
+               break;
+       case PHY_INTERFACE_MODE_RGMII:
+               mii_if = AR71XX_MII1_CTRL_IF_RGMII;
+               break;
+       default:
+               WARN(1, "Impossible PHY mode defined.\n");
+               return;
+       }
+
+       ath79_mii_ctrl_set_if(ag, mii_if);
+}
+
 static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
 {
        unsigned int mii_speed;
@@ -1427,6 +1481,20 @@ static int ag71xx_probe(struct platform_device *pdev)
                goto err_free;
        }
 
+       if (of_property_read_u32(np, "qca,mac-idx", &ag->mac_idx))
+               ag->mac_idx = -1;
+       if (ag->mii_base)
+               switch (ag->mac_idx) {
+               case 0:
+                       ath79_mii0_ctrl_set_if(ag);
+                       break;
+               case 1:
+                       ath79_mii1_ctrl_set_if(ag);
+                       break;
+               default:
+                       break;
+               }
+
        netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
 
        ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);