bcm27xx: remove linux 5.10 compatibility

[openwrt/staging/chunkeey.git] / target / linux / bcm27xx / patches-5.10 / 950-0011-irqchip-bcm2835-Add-FIQ-support.patch

diff --git a/target/linux/bcm27xx/patches-5.10/950-0011-irqchip-bcm2835-Add-FIQ-support.patch b/target/linux/bcm27xx/patches-5.10/950-0011-irqchip-bcm2835-Add-FIQ-support.patch
deleted file mode 100644 (file)
index 95a4819..0000000
--- a/target/linux/bcm27xx/patches-5.10/950-0011-irqchip-bcm2835-Add-FIQ-support.patch
+++ /dev/null
@@ -1,127 +0,0 @@
-From ad12646921360036adf7ecdcf1325b9a880b316a Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
-Date: Fri, 12 Jun 2015 19:01:05 +0200
-Subject: [PATCH] irqchip: bcm2835: Add FIQ support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add a duplicate irq range with an offset on the hwirq's so the
-driver can detect that enable_fiq() is used.
-Tested with downstream dwc_otg USB controller driver.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Acked-by: Stephen Warren <swarren@wwwdotorg.org>
----
- arch/arm/mach-bcm/Kconfig     |  1 +
- drivers/irqchip/irq-bcm2835.c | 51 +++++++++++++++++++++++++++++++----
- 2 files changed, 47 insertions(+), 5 deletions(-)
-
---- a/arch/arm/mach-bcm/Kconfig
-+++ b/arch/arm/mach-bcm/Kconfig
-@@ -161,6 +161,7 @@ config ARCH_BCM2835
-       select ARM_TIMER_SP804
-       select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7
-       select BCM2835_TIMER
-+      select FIQ
-       select PINCTRL
-       select PINCTRL_BCM2835
-       select MFD_CORE
---- a/drivers/irqchip/irq-bcm2835.c
-+++ b/drivers/irqchip/irq-bcm2835.c
-@@ -45,7 +45,7 @@
- #include <asm/exception.h>
- 
- /* Put the bank and irq (32 bits) into the hwirq */
--#define MAKE_HWIRQ(b, n)      ((b << 5) | (n))
-+#define MAKE_HWIRQ(b, n)      (((b) << 5) | (n))
- #define HWIRQ_BANK(i)         (i >> 5)
- #define HWIRQ_BIT(i)          BIT(i & 0x1f)
- 
-@@ -62,9 +62,13 @@
- 
- #define REG_FIQ_CONTROL               0x0c
- #define FIQ_CONTROL_ENABLE    BIT(7)
-+#define REG_FIQ_ENABLE                FIQ_CONTROL_ENABLE
-+#define REG_FIQ_DISABLE       0
- 
- #define NR_BANKS              3
- #define IRQS_PER_BANK         32
-+#define NUMBER_IRQS           MAKE_HWIRQ(NR_BANKS, 0)
-+#define FIQ_START             (NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0))
- 
- static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
- static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
-@@ -89,14 +93,38 @@ static void __exception_irq_entry bcm283
-       struct pt_regs *regs);
- static void bcm2836_chained_handle_irq(struct irq_desc *desc);
- 
-+static inline unsigned int hwirq_to_fiq(unsigned long hwirq)
-+{
-+      hwirq -= NUMBER_IRQS;
-+      /*
-+       * The hwirq numbering used in this driver is:
-+       *   BASE (0-7) GPU1 (32-63) GPU2 (64-95).
-+       * This differ from the one used in the FIQ register:
-+       *   GPU1 (0-31) GPU2 (32-63) BASE (64-71)
-+       */
-+      if (hwirq >= 32)
-+              return hwirq - 32;
-+
-+      return hwirq + 64;
-+}
-+
- static void armctrl_mask_irq(struct irq_data *d)
- {
--      writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
-+      if (d->hwirq >= NUMBER_IRQS)
-+              writel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL);
-+      else
-+              writel_relaxed(HWIRQ_BIT(d->hwirq),
-+                             intc.disable[HWIRQ_BANK(d->hwirq)]);
- }
- 
- static void armctrl_unmask_irq(struct irq_data *d)
- {
--      writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
-+      if (d->hwirq >= NUMBER_IRQS)
-+              writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq),
-+                             intc.base + REG_FIQ_CONTROL);
-+      else
-+              writel_relaxed(HWIRQ_BIT(d->hwirq),
-+                             intc.enable[HWIRQ_BANK(d->hwirq)]);
- }
- 
- static struct irq_chip armctrl_chip = {
-@@ -142,8 +170,9 @@ static int __init armctrl_of_init(struct
-       if (!base)
-               panic("%pOF: unable to map IC registers\n", node);
- 
--      intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
--                      &armctrl_ops, NULL);
-+      intc.base = base;
-+      intc.domain = irq_domain_add_linear(node, NUMBER_IRQS * 2,
-+                                          &armctrl_ops, NULL);
-       if (!intc.domain)
-               panic("%pOF: unable to create IRQ domain\n", node);
- 
-@@ -186,6 +215,18 @@ static int __init armctrl_of_init(struct
-               set_handle_irq(bcm2835_handle_irq);
-       }
- 
-+      /* Make a duplicate irq range which is used to enable FIQ */
-+      for (b = 0; b < NR_BANKS; b++) {
-+              for (i = 0; i < bank_irqs[b]; i++) {
-+                      irq = irq_create_mapping(intc.domain,
-+                                      MAKE_HWIRQ(b, i) + NUMBER_IRQS);
-+                      BUG_ON(irq <= 0);
-+                      irq_set_chip(irq, &armctrl_chip);
-+                      set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-+              }
-+      }
-+      init_FIQ(FIQ_START);
-+
-       return 0;
- }
-