+++ /dev/null
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Subject: [PATCH] net: phy: cherry-pick Broadcom drivers updates from v4.10
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This includes following upstream commits:
-5519da874ad0 net: phy: broadcom: Move bcm54xx_auxctl_{read, write} to common library
-b14995ac2527 net: phy: broadcom: Add BCM54810 PHY entry
-5b4e29005123 net: phy: broadcom: add bcm54xx_auxctl_read
-d92ead16be40 net: phy: broadcom: Add support for BCM54612E
-3cf25904fe46 net: phy: broadcom: Update Auxiliary Control Register macros
-
-Other commits were skipped as they depend on other changes like
-ETHTOOL_PHY_DOWNSHIFT & DOWNSHIFT_DEV_DISABLE and new APIs like
-get_sset_count.
-
-One exception was picking new regs from commit d06f78c4232d ("net: phy:
-broadcom: Add support code for downshift/Wirespeed").
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -77,7 +77,7 @@ config BROADCOM_PHY
- select BCM_NET_PHYLIB
- ---help---
- Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
-- BCM5481 and BCM5482 PHYs.
-+ BCM5481, BCM54810 and BCM5482 PHYs.
-
- config BCM_CYGNUS_PHY
- tristate "Drivers for Broadcom Cygnus SoC internal PHY"
---- a/drivers/net/phy/bcm-phy-lib.c
-+++ b/drivers/net/phy/bcm-phy-lib.c
-@@ -50,6 +50,23 @@ int bcm_phy_read_exp(struct phy_device *
- }
- EXPORT_SYMBOL_GPL(bcm_phy_read_exp);
-
-+int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
-+{
-+ /* The register must be written to both the Shadow Register Select and
-+ * the Shadow Read Register Selector
-+ */
-+ phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum |
-+ regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
-+ return phy_read(phydev, MII_BCM54XX_AUX_CTL);
-+}
-+EXPORT_SYMBOL_GPL(bcm54xx_auxctl_read);
-+
-+int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
-+{
-+ return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
-+}
-+EXPORT_SYMBOL(bcm54xx_auxctl_write);
-+
- int bcm_phy_write_misc(struct phy_device *phydev,
- u16 reg, u16 chl, u16 val)
- {
---- a/drivers/net/phy/bcm-phy-lib.h
-+++ b/drivers/net/phy/bcm-phy-lib.h
-@@ -19,6 +19,9 @@
- int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val);
- int bcm_phy_read_exp(struct phy_device *phydev, u16 reg);
-
-+int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val);
-+int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum);
-+
- int bcm_phy_write_misc(struct phy_device *phydev,
- u16 reg, u16 chl, u16 value);
- int bcm_phy_read_misc(struct phy_device *phydev,
---- a/drivers/net/phy/broadcom.c
-+++ b/drivers/net/phy/broadcom.c
-@@ -18,7 +18,7 @@
- #include <linux/module.h>
- #include <linux/phy.h>
- #include <linux/brcmphy.h>
--
-+#include <linux/of.h>
-
- #define BRCM_PHY_MODEL(phydev) \
- ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
-@@ -30,9 +30,32 @@ MODULE_DESCRIPTION("Broadcom PHY driver"
- MODULE_AUTHOR("Maciej W. Rozycki");
- MODULE_LICENSE("GPL");
-
--static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
-+static int bcm54810_config(struct phy_device *phydev)
- {
-- return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
-+ int rc, val;
-+
-+ val = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
-+ val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
-+ rc = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
-+ val);
-+ if (rc < 0)
-+ return rc;
-+
-+ val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
-+ val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
-+ val |= MII_BCM54XX_AUXCTL_MISC_WREN;
-+ rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
-+ val);
-+ if (rc < 0)
-+ return rc;
-+
-+ val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
-+ val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
-+ rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
-+ if (rc < 0)
-+ return rc;
-+
-+ return 0;
- }
-
- /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
-@@ -207,6 +230,12 @@ static int bcm54xx_config_init(struct ph
- (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
- bcm54xx_adjust_rxrefclk(phydev);
-
-+ if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
-+ err = bcm54810_config(phydev);
-+ if (err)
-+ return err;
-+ }
-+
- bcm54xx_phydsp_config(phydev);
-
- return 0;
-@@ -304,6 +333,7 @@ static int bcm5482_read_status(struct ph
-
- static int bcm5481_config_aneg(struct phy_device *phydev)
- {
-+ struct device_node *np = phydev->dev.of_node;
- int ret;
-
- /* Aneg firsly. */
-@@ -334,6 +364,49 @@ static int bcm5481_config_aneg(struct ph
- phy_write(phydev, 0x18, reg);
- }
-
-+ if (of_property_read_bool(np, "enet-phy-lane-swap")) {
-+ /* Lane Swap - Undocumented register...magic! */
-+ ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
-+ 0x11B);
-+ if (ret < 0)
-+ return ret;
-+ }
-+
-+ return ret;
-+}
-+
-+static int bcm54612e_config_aneg(struct phy_device *phydev)
-+{
-+ int ret;
-+
-+ /* First, auto-negotiate. */
-+ ret = genphy_config_aneg(phydev);
-+
-+ /* Clear TX internal delay unless requested. */
-+ if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
-+ (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
-+ /* Disable TXD to GTXCLK clock delay (default set) */
-+ /* Bit 9 is the only field in shadow register 00011 */
-+ bcm_phy_write_shadow(phydev, 0x03, 0);
-+ }
-+
-+ /* Clear RX internal delay unless requested. */
-+ if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
-+ (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
-+ u16 reg;
-+
-+ /* Errata: reads require filling in the write selector field */
-+ bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
-+ MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
-+ reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
-+ /* Disable RXD to RXC delay (default set) */
-+ reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
-+ /* Clear shadow selector field */
-+ reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
-+ bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
-+ MII_BCM54XX_AUXCTL_MISC_WREN | reg);
-+ }
-+
- return ret;
- }
-
-@@ -488,6 +561,18 @@ static struct phy_driver broadcom_driver
- .config_intr = bcm_phy_config_intr,
- .driver = { .owner = THIS_MODULE },
- }, {
-+ .phy_id = PHY_ID_BCM54612E,
-+ .phy_id_mask = 0xfffffff0,
-+ .name = "Broadcom BCM54612E",
-+ .features = PHY_GBIT_FEATURES |
-+ SUPPORTED_Pause | SUPPORTED_Asym_Pause,
-+ .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
-+ .config_init = bcm54xx_config_init,
-+ .config_aneg = bcm54612e_config_aneg,
-+ .read_status = genphy_read_status,
-+ .ack_interrupt = bcm_phy_ack_intr,
-+ .config_intr = bcm_phy_config_intr,
-+}, {
- .phy_id = PHY_ID_BCM54616S,
- .phy_id_mask = 0xfffffff0,
- .name = "Broadcom BCM54616S",
-@@ -527,6 +612,18 @@ static struct phy_driver broadcom_driver
- .config_intr = bcm_phy_config_intr,
- .driver = { .owner = THIS_MODULE },
- }, {
-+ .phy_id = PHY_ID_BCM54810,
-+ .phy_id_mask = 0xfffffff0,
-+ .name = "Broadcom BCM54810",
-+ .features = PHY_GBIT_FEATURES |
-+ SUPPORTED_Pause | SUPPORTED_Asym_Pause,
-+ .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
-+ .config_init = bcm54xx_config_init,
-+ .config_aneg = bcm5481_config_aneg,
-+ .read_status = genphy_read_status,
-+ .ack_interrupt = bcm_phy_ack_intr,
-+ .config_intr = bcm_phy_config_intr,
-+}, {
- .phy_id = PHY_ID_BCM5482,
- .phy_id_mask = 0xfffffff0,
- .name = "Broadcom BCM5482",
-@@ -612,9 +709,11 @@ static struct mdio_device_id __maybe_unu
- { PHY_ID_BCM5411, 0xfffffff0 },
- { PHY_ID_BCM5421, 0xfffffff0 },
- { PHY_ID_BCM5461, 0xfffffff0 },
-+ { PHY_ID_BCM54612E, 0xfffffff0 },
- { PHY_ID_BCM54616S, 0xfffffff0 },
- { PHY_ID_BCM5464, 0xfffffff0 },
- { PHY_ID_BCM5481, 0xfffffff0 },
-+ { PHY_ID_BCM54810, 0xfffffff0 },
- { PHY_ID_BCM5482, 0xfffffff0 },
- { PHY_ID_BCM50610, 0xfffffff0 },
- { PHY_ID_BCM50610M, 0xfffffff0 },
---- a/include/linux/brcmphy.h
-+++ b/include/linux/brcmphy.h
-@@ -13,11 +13,13 @@
- #define PHY_ID_BCM5241 0x0143bc30
- #define PHY_ID_BCMAC131 0x0143bc70
- #define PHY_ID_BCM5481 0x0143bca0
-+#define PHY_ID_BCM54810 0x03625d00
- #define PHY_ID_BCM5482 0x0143bcb0
- #define PHY_ID_BCM5411 0x00206070
- #define PHY_ID_BCM5421 0x002060e0
- #define PHY_ID_BCM5464 0x002060b0
- #define PHY_ID_BCM5461 0x002060c0
-+#define PHY_ID_BCM54612E 0x03625e60
- #define PHY_ID_BCM54616S 0x03625d10
- #define PHY_ID_BCM57780 0x03625d90
-
-@@ -55,6 +57,7 @@
- #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
- #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
- #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
-+
- /* Broadcom BCM7xxx specific workarounds */
- #define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)
- #define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)
-@@ -105,11 +108,14 @@
- #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
-
- #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
-+#define MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW 0x0100
- #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
- #define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
- #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
-+#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
-+#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN (1 << 8)
-
--#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
-+#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
-
- /*
- * Broadcom LED source encodings. These are used in BCM5461, BCM5481,
-@@ -124,6 +130,7 @@
- #define BCM_LED_SRC_INTR 0x6
- #define BCM_LED_SRC_QUALITY 0x7
- #define BCM_LED_SRC_RCVLED 0x8
-+#define BCM_LED_SRC_WIRESPEED 0x9
- #define BCM_LED_SRC_MULTICOLOR1 0xa
- #define BCM_LED_SRC_OPENSHORT 0xb
- #define BCM_LED_SRC_OFF 0xe /* Tied high */
-@@ -135,6 +142,14 @@
- * Shadow values go into bits [14:10] of register 0x1c to select a shadow
- * register to access.
- */
-+
-+/* 00100: Reserved control register 2 */
-+#define BCM54XX_SHD_SCR2 0x04
-+#define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100
-+#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2
-+#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2
-+#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7
-+
- /* 00101: Spare Control Register 3 */
- #define BCM54XX_SHD_SCR3 0x05
- #define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
-@@ -189,6 +204,12 @@
- #define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
- #define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
-
-+/* BCM54810 Registers */
-+#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90)
-+#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0)
-+#define BCM54810_SHD_CLK_CTL 0x3
-+#define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9)
-+
-
- /*****************************************************************************/
- /* Fast Ethernet Transceiver definitions. */
projects / openwrt / staging / chunkeey.git / blobdiff