--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
-@@ -159,6 +159,11 @@
+@@ -163,6 +163,11 @@
/* NAND_CTRL bits */
#define BAM_MODE_EN BIT(0)
/*
* the NAND controller performs reads/writes with ECC in 516 byte chunks.
* the driver calls the chunks 'step' or 'codeword' interchangeably
-@@ -430,6 +435,13 @@ struct qcom_nand_controller {
+@@ -443,6 +448,13 @@ struct qcom_nand_controller {
* @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
* ecc/non-ecc mode for the current nand flash
* device
*/
struct qcom_nand_host {
struct nand_chip chip;
-@@ -452,6 +464,9 @@ struct qcom_nand_host {
+@@ -465,6 +477,9 @@ struct qcom_nand_host {
u32 ecc_bch_cfg;
u32 clrflashstatus;
u32 clrreadstatus;
};
/*
-@@ -475,13 +490,15 @@ struct qcom_nand_host {
+@@ -474,6 +489,7 @@ struct qcom_nand_host {
* @is_bam - whether NAND controller is using BAM
* @is_qpic - whether NAND CTRL is part of qpic IP
* @qpic_v2 - flag to indicate QPIC IP version 2
* @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
*/
struct qcom_nandc_props {
- u32 ecc_modes;
+@@ -481,6 +497,7 @@ struct qcom_nandc_props {
bool is_bam;
bool is_qpic;
bool qpic_v2;
u32 dev_cmd_reg_start;
};
-@@ -1604,7 +1621,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *
+@@ -1691,7 +1708,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *
data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
oob_size1 = host->bbm_size;
data_size2 = ecc->size - data_size1 -
((ecc->steps - 1) * 4);
oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw +
-@@ -1685,7 +1702,7 @@ check_for_erased_page(struct qcom_nand_h
+@@ -1772,7 +1789,7 @@ check_for_erased_page(struct qcom_nand_h
}
for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) {
data_size = ecc->size - ((ecc->steps - 1) * 4);
oob_size = (ecc->steps * 4) + host->ecc_bytes_hw;
} else {
-@@ -1844,7 +1861,7 @@ static int read_page_ecc(struct qcom_nan
+@@ -1930,7 +1947,7 @@ static int read_page_ecc(struct qcom_nan
for (i = 0; i < ecc->steps; i++) {
int data_size, oob_size;
data_size = ecc->size - ((ecc->steps - 1) << 2);
oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +
host->spare_bytes;
-@@ -1941,6 +1958,30 @@ static int copy_last_cw(struct qcom_nand
+@@ -2027,6 +2044,30 @@ static int copy_last_cw(struct qcom_nand
return ret;
}
/* implements ecc->read_page() */
static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf,
int oob_required, int page)
-@@ -1949,6 +1990,9 @@ static int qcom_nandc_read_page(struct n
+@@ -2035,6 +2076,9 @@ static int qcom_nandc_read_page(struct n
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
u8 *data_buf, *oob_buf = NULL;
nand_read_page_op(chip, page, 0, NULL, 0);
data_buf = buf;
oob_buf = oob_required ? chip->oob_poi : NULL;
-@@ -1968,6 +2012,9 @@ static int qcom_nandc_read_page_raw(stru
+@@ -2054,6 +2098,9 @@ static int qcom_nandc_read_page_raw(stru
int cw, ret;
u8 *data_buf = buf, *oob_buf = chip->oob_poi;
for (cw = 0; cw < ecc->steps; cw++) {
ret = qcom_nandc_read_cw_raw(mtd, chip, data_buf, oob_buf,
page, cw);
-@@ -1988,6 +2035,9 @@ static int qcom_nandc_read_oob(struct na
+@@ -2074,6 +2121,9 @@ static int qcom_nandc_read_oob(struct na
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
struct nand_ecc_ctrl *ecc = &chip->ecc;
clear_read_regs(nandc);
clear_bam_transaction(nandc);
-@@ -2008,6 +2058,9 @@ static int qcom_nandc_write_page(struct
+@@ -2094,6 +2144,9 @@ static int qcom_nandc_write_page(struct
u8 *data_buf, *oob_buf;
int i, ret;
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
clear_read_regs(nandc);
-@@ -2023,7 +2076,7 @@ static int qcom_nandc_write_page(struct
+@@ -2109,7 +2162,7 @@ static int qcom_nandc_write_page(struct
for (i = 0; i < ecc->steps; i++) {
int data_size, oob_size;
data_size = ecc->size - ((ecc->steps - 1) << 2);
oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +
host->spare_bytes;
-@@ -2080,6 +2133,9 @@ static int qcom_nandc_write_page_raw(str
+@@ -2166,6 +2219,9 @@ static int qcom_nandc_write_page_raw(str
u8 *data_buf, *oob_buf;
int i, ret;
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
clear_read_regs(nandc);
clear_bam_transaction(nandc);
-@@ -2098,7 +2154,7 @@ static int qcom_nandc_write_page_raw(str
+@@ -2184,7 +2240,7 @@ static int qcom_nandc_write_page_raw(str
data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
oob_size1 = host->bbm_size;
data_size2 = ecc->size - data_size1 -
((ecc->steps - 1) << 2);
oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw +
-@@ -2158,6 +2214,9 @@ static int qcom_nandc_write_oob(struct n
+@@ -2244,6 +2300,9 @@ static int qcom_nandc_write_oob(struct n
int data_size, oob_size;
int ret;
host->use_ecc = true;
clear_bam_transaction(nandc);
-@@ -2806,6 +2865,7 @@ static int qcom_nand_host_init_and_regis
+@@ -2899,6 +2958,7 @@ static int qcom_nand_host_init_and_regis
struct nand_chip *chip = &host->chip;
struct mtd_info *mtd = nand_to_mtd(chip);
struct device *dev = nandc->dev;
int ret;
ret = of_property_read_u32(dn, "reg", &host->cs);
-@@ -2866,6 +2926,17 @@ static int qcom_nand_host_init_and_regis
+@@ -2960,6 +3020,17 @@ static int qcom_nand_host_init_and_regis
if (ret)
nand_cleanup(chip);
return ret;
}
-@@ -3032,6 +3103,7 @@ static int qcom_nandc_remove(struct plat
+@@ -3125,6 +3196,7 @@ static int qcom_nandc_remove(struct plat
static const struct qcom_nandc_props ipq806x_nandc_props = {
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
.is_bam = false,