cns3xxx: add preliminary 4.9 support
[openwrt/staging/lynxis/omap.git] / target / linux / cns3xxx / patches-4.9 / 040-fiq_support.patch
diff --git a/target/linux/cns3xxx/patches-4.9/040-fiq_support.patch b/target/linux/cns3xxx/patches-4.9/040-fiq_support.patch
new file mode 100644 (file)
index 0000000..b391eb9
--- /dev/null
@@ -0,0 +1,40 @@
+--- a/arch/arm/mach-cns3xxx/Kconfig
++++ b/arch/arm/mach-cns3xxx/Kconfig
+@@ -5,6 +5,7 @@ menuconfig ARCH_CNS3XXX
+       select HAVE_ARM_SCU if SMP
+       select HAVE_ARM_TWD
+       select HAVE_SMP
++      select FIQ
+       help
+         Support for Cavium Networks CNS3XXX platform.
+--- a/arch/arm/mach-cns3xxx/Makefile
++++ b/arch/arm/mach-cns3xxx/Makefile
+@@ -5,5 +5,5 @@ cns3xxx-y                              += core.o pm.o
+ cns3xxx-$(CONFIG_ATAGS)                       += devices.o
+ cns3xxx-$(CONFIG_PCI)                 += pcie.o
+ cns3xxx-$(CONFIG_MACH_CNS3420VB)      += cns3420vb.o
+-cns3xxx-$(CONFIG_SMP)                 += platsmp.o headsmp.o
++cns3xxx-$(CONFIG_SMP)                 += platsmp.o headsmp.o cns3xxx_fiq.o
+ cns3xxx-$(CONFIG_HOTPLUG_CPU)         += hotplug.o
+--- a/arch/arm/mach-cns3xxx/cns3xxx.h
++++ b/arch/arm/mach-cns3xxx/cns3xxx.h
+@@ -261,6 +261,7 @@
+ #define MISC_PCIE_INT_MASK(x)                 MISC_MEM_MAP(0x978 + (x) * 0x100)
+ #define MISC_PCIE_INT_STATUS(x)                       MISC_MEM_MAP(0x97C + (x) * 0x100)
++#define MISC_FIQ_CPU(x)                               MISC_MEM_MAP(0xA58 - (x) * 0x4)
+ /*
+  * Power management and clock control
+  */
+--- a/arch/arm/mm/Kconfig
++++ b/arch/arm/mm/Kconfig
+@@ -856,7 +856,7 @@ config VDSO
+ config DMA_CACHE_RWFO
+       bool "Enable read/write for ownership DMA cache maintenance"
+-      depends on CPU_V6K && SMP
++      depends on CPU_V6K && SMP && !ARCH_CNS3XXX
+       default y
+       help
+         The Snoop Control Unit on ARM11MPCore does not detect the