ipq40xx: use patches that were sent upstream

[openwrt/staging/mkresin.git] / target / linux / ipq40xx / patches-4.14 / 072-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch

diff --git a/target/linux/ipq40xx/patches-4.14/072-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch b/target/linux/ipq40xx/patches-4.14/072-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch
new file mode 100644 (file)
index 0000000..5596e30
--- /dev/null
+++ b/target/linux/ipq40xx/patches-4.14/072-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch
@@ -0,0 +1,80 @@
+From 544af73985cd14b450bb8e8a6c22b89a555ac729 Mon Sep 17 00:00:00 2001
+From: Matthew McClintock <mmcclint@codeaurora.org>
+Date: Mon, 23 Jul 2018 09:10:35 +0200
+Subject: [PATCH 6/8] qcom: ipq4019: add cpu operating points for cpufreq
+ support
+
+This adds some operating points for cpu frequeny scaling
+
+Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
+ 1 file changed, 26 insertions(+), 8 deletions(-)
+
+Index: linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019.dtsi
+===================================================================
+--- linux-4.14.54.orig/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -41,14 +41,7 @@
+                       reg = <0x0>;
+                       clocks = <&gcc GCC_APPS_CLK_SRC>;
+                       clock-frequency = <0>;
+-                      operating-points = <
+-                              /* kHz  uV (fixed) */
+-                              48000   1100000
+-                              200000  1100000
+-                              500000  1100000
+-                              666000  1100000
+-                      >;
+-                      clock-latency = <256000>;
++                      operating-points-v2 = <&cpu0_opp_table>;
+               };
+ 
+               cpu@1 {
+@@ -61,6 +54,7 @@
+                       reg = <0x1>;
+                       clocks = <&gcc GCC_APPS_CLK_SRC>;
+                       clock-frequency = <0>;
++                      operating-points-v2 = <&cpu0_opp_table>;
+               };
+ 
+               cpu@2 {
+@@ -73,6 +67,7 @@
+                       reg = <0x2>;
+                       clocks = <&gcc GCC_APPS_CLK_SRC>;
+                       clock-frequency = <0>;
++                      operating-points-v2 = <&cpu0_opp_table>;
+               };
+ 
+               cpu@3 {
+@@ -85,6 +80,29 @@
+                       reg = <0x3>;
+                       clocks = <&gcc GCC_APPS_CLK_SRC>;
+                       clock-frequency = <0>;
++                      operating-points-v2 = <&cpu0_opp_table>;
++              };
++      };
++
++      cpu0_opp_table: opp_table0 {
++              compatible = "operating-points-v2";
++              opp-shared;
++
++              opp-48000000 {
++                      opp-hz = /bits/ 64 <48000000>;
++                      clock-latency-ns = <256000>;
++              };
++              opp-200000000 {
++                      opp-hz = /bits/ 64 <200000000>;
++                      clock-latency-ns = <256000>;
++              };
++              opp-500000000 {
++                      opp-hz = /bits/ 64 <500000000>;
++                      clock-latency-ns = <256000>;
++              };
++              opp-716000000 {
++                      opp-hz = /bits/ 64 <716000000>;
++                      clock-latency-ns = <256000>;
+               };
+ 
+               L2: l2-cache {