ramips: switch to Linux 6.6

[openwrt/staging/nbd.git] / target / linux / ramips / patches-6.1 / 005-v6.5-01-dt-bindings-clock-add-mtmips-SoCs-system-controller.patch

diff --git a/target/linux/ramips/patches-6.1/005-v6.5-01-dt-bindings-clock-add-mtmips-SoCs-system-controller.patch b/target/linux/ramips/patches-6.1/005-v6.5-01-dt-bindings-clock-add-mtmips-SoCs-system-controller.patch
deleted file mode 100644 (file)
index 94784f7..0000000
--- a/target/linux/ramips/patches-6.1/005-v6.5-01-dt-bindings-clock-add-mtmips-SoCs-system-controller.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From 612616e6381929e7f9e303f8b8ad3655cc101516 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:33 +0200
-Subject: [PATCH 1/9] dt-bindings: clock: add mtmips SoCs system controller
-
-Adds device tree binding documentation for system controller node present
-in Mediatek MIPS and Ralink SOCs. This node is a clock and reset provider
-for the rest of the world. This covers RT2880, RT3050, RT3052, RT3350,
-RT3883, RT5350, MT7620, MT7628 and MT7688 SoCs.
-
-Reviewed-by: Rob Herring <robh@kernel.org>
-Acked-by: Stephen Boyd <sboyd@kernel.org>
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- .../bindings/clock/mediatek,mtmips-sysc.yaml       | 64 ++++++++++++++++++++++
- 1 file changed, 64 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
-@@ -0,0 +1,64 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MTMIPS SoCs System Controller
-+
-+maintainers:
-+  - Sergio Paracuellos <sergio.paracuellos@gmail.com>
-+
-+description: |
-+  MediaTek MIPS and Ralink SoCs provides a system controller to allow
-+  to access to system control registers. These registers include clock
-+  and reset related ones so this node is both clock and reset provider
-+  for the rest of the world.
-+
-+  These SoCs have an XTAL from where the cpu clock is
-+  provided as well as derived clocks for the bus and the peripherals.
-+
-+properties:
-+  compatible:
-+    items:
-+      - enum:
-+          - ralink,mt7620-sysc
-+          - ralink,mt7628-sysc
-+          - ralink,mt7688-sysc
-+          - ralink,rt2880-sysc
-+          - ralink,rt3050-sysc
-+          - ralink,rt3052-sysc
-+          - ralink,rt3352-sysc
-+          - ralink,rt3883-sysc
-+          - ralink,rt5350-sysc
-+      - const: syscon
-+
-+  reg:
-+    maxItems: 1
-+
-+  '#clock-cells':
-+    description:
-+      The first cell indicates the clock number.
-+    const: 1
-+
-+  '#reset-cells':
-+    description:
-+      The first cell indicates the reset bit within the register.
-+    const: 1
-+
-+required:
-+  - compatible
-+  - reg
-+  - '#clock-cells'
-+  - '#reset-cells'
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    syscon@0 {
-+      compatible = "ralink,rt5350-sysc", "syscon";
-+      reg = <0x0 0x100>;
-+      #clock-cells = <1>;
-+      #reset-cells = <1>;
-+    };