+++ /dev/null
-From b9185c75f7ec2b600ebe0d49281e216a2456b764 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
-Date: Thu, 13 May 2021 15:11:06 +0200
-Subject: [PATCH] fix(plat/marvell/a3720/uart): fix configuring UART clock
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-When configuring the UART_BAUD_REG register, the function
-console_a3700_core_init() currently only changes the baud divisor field,
-leaving other fields to their previous value.
-
-This is incorrect, because the baud divisor is computed with the
-assumption that the parent clock rate is 25 MHz, and since the other
-fields in this register configure the parent clock, which could have
-been changed by U-Boot or Linux.
-
-Fix this function to also configure the other fields so that the UART
-parent clock is selected to be the xtal clock.
-
-For example without this change TF-A prints only
-
- ERROR: a3700_system_off needs to be implemented
-
-followed by garbage after plat_crash_console_init() is called.
-
-After applying this change instead of garbage it also print crash info:
-
- PANIC at PC : 0x0000000004023800
-
-Signed-off-by: Pali Rohár <pali@kernel.org>
-Change-Id: I72f338355cc60d939b8bb978d9c7fdd576416b81
----
- drivers/marvell/uart/a3700_console.S | 7 ++-----
- 1 file changed, 2 insertions(+), 5 deletions(-)
-
---- a/drivers/marvell/uart/a3700_console.S
-+++ b/drivers/marvell/uart/a3700_console.S
-@@ -49,12 +49,9 @@ func console_a3700_core_init
- lsl w2, w2, #4
- add w1, w1, w2, lsr #1
- udiv w2, w1, w2
-- and w2, w2, #0x3ff
-+ and w2, w2, #0x3ff /* clear all other bits to use default clock */
-
-- ldr w3, [x0, #UART_BAUD_REG]
-- bic w3, w3, 0x3ff
-- orr w3, w3, w2
-- str w3, [x0, #UART_BAUD_REG]/* set baud rate divisor */
-+ str w2, [x0, #UART_BAUD_REG]/* set baud rate divisor */
-
- /* Set UART to default 16X scheme */
- mov w3, #0
projects / openwrt / staging / stintel.git / blobdiff