+++ /dev/null
-From cc1d1d1b68d18a31aeb8a572ca6b3929b083855c Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Wed, 17 Apr 2019 18:58:33 +0800
-Subject: [PATCH] dts: support layerscape
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This is an integrated patch of dts for layerscape
-
-Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
-Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
-Signed-off-by: Alan Wang <alan.wang@nxp.com>
-Signed-off-by: Alison Wang <alison.wang@nxp.com>
-Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
-Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
-Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
-Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
-Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
-Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
-Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
-Signed-off-by: Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
-Signed-off-by: Changming Huang <jerry.huang@nxp.com>
-Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
-Signed-off-by: Constantin Tudor <constantin.tudor@nxp.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
-Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
-Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
-Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com>
-Signed-off-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
-Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
-Signed-off-by: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
-Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
-Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
-Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
-Signed-off-by: Li Yang <leoyang.li@nxp.com>
-Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
-Signed-off-by: Mathew McBride <matt@traverse.com.au>
-Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
-Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
-Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
-Signed-off-by: Peng Ma <peng.ma@nxp.com>
-Signed-off-by: Po Liu <po.liu@nxp.com>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
-Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
-Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
-Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
-Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
-Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
-Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
-Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
-Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com>
-Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
-Signed-off-by: Scott Wood <oss@buserror.net>
-Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
-Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
-Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
-Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
-Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
-Signed-off-by: Tao Yang <b31903@freescale.com>
-Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
-Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo@nxp.com>
-Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
-Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
-Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
-Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
-Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
-Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
-Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
-Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
-Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
-Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
-Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
----
- arch/arm/boot/dts/Makefile | 3 +-
- arch/arm/boot/dts/imx25.dtsi | 4 +-
- arch/arm/boot/dts/imx28.dtsi | 4 +-
- arch/arm/boot/dts/imx35.dtsi | 4 +-
- arch/arm/boot/dts/imx53.dtsi | 4 +-
- arch/arm/boot/dts/ls1021a-iot.dts | 262 ++++
- arch/arm/boot/dts/ls1021a-qds.dts | 32 +
- arch/arm/boot/dts/ls1021a-twr.dts | 27 +
- arch/arm/boot/dts/ls1021a.dtsi | 111 +-
- arch/arm64/boot/dts/freescale/Makefile | 16 +-
- .../boot/dts/freescale/fsl-ls1012a-2g5rdb.dts | 126 ++
- .../boot/dts/freescale/fsl-ls1012a-frdm.dts | 97 +-
- .../boot/dts/freescale/fsl-ls1012a-frwy.dts | 179 +++
- .../boot/dts/freescale/fsl-ls1012a-qds.dts | 136 +-
- .../boot/dts/freescale/fsl-ls1012a-rdb.dts | 100 +-
- .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 210 ++-
- .../boot/dts/freescale/fsl-ls1043-post.dtsi | 3 +-
- .../dts/freescale/fsl-ls1043a-qds-sdk.dts | 263 ++++
- .../boot/dts/freescale/fsl-ls1043a-qds.dts | 206 ++-
- .../dts/freescale/fsl-ls1043a-rdb-sdk.dts | 262 ++++
- .../dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 140 ++
- .../boot/dts/freescale/fsl-ls1043a-rdb.dts | 76 +-
- .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 382 +++--
- .../boot/dts/freescale/fsl-ls1046-post.dtsi | 2 +-
- .../dts/freescale/fsl-ls1046a-qds-sdk.dts | 268 ++++
- .../boot/dts/freescale/fsl-ls1046a-qds.dts | 194 ++-
- .../dts/freescale/fsl-ls1046a-rdb-sdk.dts | 307 ++++
- .../dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 133 ++
- .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 48 +-
- .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 386 +++--
- .../boot/dts/freescale/fsl-ls1088a-qds.dts | 88 +-
- .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 150 +-
- .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 546 ++++++-
- .../boot/dts/freescale/fsl-ls2080a-qds.dts | 100 +-
- .../boot/dts/freescale/fsl-ls2080a-rdb.dts | 118 +-
- .../boot/dts/freescale/fsl-ls2080a-simu.dts | 38 +-
- .../arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 50 +-
- .../boot/dts/freescale/fsl-ls2081a-rdb.dts | 163 ++
- .../boot/dts/freescale/fsl-ls2088a-qds.dts | 158 +-
- .../boot/dts/freescale/fsl-ls2088a-rdb.dts | 118 +-
- .../arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 52 +-
- .../boot/dts/freescale/fsl-ls208xa-qds.dtsi | 43 +-
- .../boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 60 +-
- .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 299 ++--
- .../boot/dts/freescale/fsl-lx2160a-qds.dts | 353 +++++
- .../boot/dts/freescale/fsl-lx2160a-rdb.dts | 241 +++
- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 1318 +++++++++++++++++
- .../boot/dts/freescale/fsl-tmu-map1.dtsi | 99 ++
- .../boot/dts/freescale/fsl-tmu-map2.dtsi | 99 ++
- .../boot/dts/freescale/fsl-tmu-map3.dtsi | 99 ++
- arch/arm64/boot/dts/freescale/fsl-tmu.dtsi | 251 ++++
- .../dts/freescale/qoriq-bman-portals-sdk.dtsi | 55 +
- .../dts/freescale/qoriq-bman-portals.dtsi | 8 +-
- .../boot/dts/freescale/qoriq-dpaa-eth.dtsi | 97 ++
- .../dts/freescale/qoriq-fman3-0-10g-0.dtsi | 11 +-
- .../dts/freescale/qoriq-fman3-0-10g-1.dtsi | 11 +-
- .../dts/freescale/qoriq-fman3-0-1g-0.dtsi | 7 +-
- .../dts/freescale/qoriq-fman3-0-1g-1.dtsi | 7 +-
- .../dts/freescale/qoriq-fman3-0-1g-2.dtsi | 7 +-
- .../dts/freescale/qoriq-fman3-0-1g-3.dtsi | 7 +-
- .../dts/freescale/qoriq-fman3-0-1g-4.dtsi | 7 +-
- .../dts/freescale/qoriq-fman3-0-1g-5.dtsi | 7 +-
- .../boot/dts/freescale/qoriq-fman3-0-6oh.dtsi | 47 +
- .../boot/dts/freescale/qoriq-fman3-0.dtsi | 67 +-
- .../dts/freescale/qoriq-qman-portals-sdk.dtsi | 38 +
- .../dts/freescale/qoriq-qman-portals.dtsi | 9 +-
- .../boot/dts/freescale/traverse-ls1043s.dts | 29 +
- .../boot/dts/freescale/traverse-ls1043v.dts | 29 +
- 68 files changed, 7660 insertions(+), 1211 deletions(-)
- create mode 100644 arch/arm/boot/dts/ls1021a-iot.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu.dtsi
- create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi
- create mode 100644 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
- create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
- create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi
-
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -496,7 +496,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
- imx7s-warp.dtb
- dtb-$(CONFIG_SOC_LS1021A) += \
- ls1021a-qds.dtb \
-- ls1021a-twr.dtb
-+ ls1021a-twr.dtb \
-+ ls1021a-iot.dtb
- dtb-$(CONFIG_SOC_VF610) += \
- vf500-colibri-eval-v3.dtb \
- vf610-colibri-eval-v3.dtb \
---- a/arch/arm/boot/dts/imx25.dtsi
-+++ b/arch/arm/boot/dts/imx25.dtsi
-@@ -122,7 +122,7 @@
- };
-
- can1: can@43f88000 {
-- compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
-+ compatible = "fsl,imx25-flexcan";
- reg = <0x43f88000 0x4000>;
- interrupts = <43>;
- clocks = <&clks 75>, <&clks 75>;
-@@ -131,7 +131,7 @@
- };
-
- can2: can@43f8c000 {
-- compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
-+ compatible = "fsl,imx25-flexcan";
- reg = <0x43f8c000 0x4000>;
- interrupts = <44>;
- clocks = <&clks 76>, <&clks 76>;
---- a/arch/arm/boot/dts/imx28.dtsi
-+++ b/arch/arm/boot/dts/imx28.dtsi
-@@ -1038,7 +1038,7 @@
- };
-
- can0: can@80032000 {
-- compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
-+ compatible = "fsl,imx28-flexcan";
- reg = <0x80032000 0x2000>;
- interrupts = <8>;
- clocks = <&clks 58>, <&clks 58>;
-@@ -1047,7 +1047,7 @@
- };
-
- can1: can@80034000 {
-- compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
-+ compatible = "fsl,imx28-flexcan";
- reg = <0x80034000 0x2000>;
- interrupts = <9>;
- clocks = <&clks 59>, <&clks 59>;
---- a/arch/arm/boot/dts/imx35.dtsi
-+++ b/arch/arm/boot/dts/imx35.dtsi
-@@ -303,7 +303,7 @@
- };
-
- can1: can@53fe4000 {
-- compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
-+ compatible = "fsl,imx35-flexcan";
- reg = <0x53fe4000 0x1000>;
- clocks = <&clks 33>, <&clks 33>;
- clock-names = "ipg", "per";
-@@ -312,7 +312,7 @@
- };
-
- can2: can@53fe8000 {
-- compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
-+ compatible = "fsl,imx35-flexcan";
- reg = <0x53fe8000 0x1000>;
- clocks = <&clks 34>, <&clks 34>;
- clock-names = "ipg", "per";
---- a/arch/arm/boot/dts/imx53.dtsi
-+++ b/arch/arm/boot/dts/imx53.dtsi
-@@ -536,7 +536,7 @@
- };
-
- can1: can@53fc8000 {
-- compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
-+ compatible = "fsl,imx53-flexcan";
- reg = <0x53fc8000 0x4000>;
- interrupts = <82>;
- clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
-@@ -546,7 +546,7 @@
- };
-
- can2: can@53fcc000 {
-- compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
-+ compatible = "fsl,imx53-flexcan";
- reg = <0x53fcc000 0x4000>;
- interrupts = <83>;
- clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
---- /dev/null
-+++ b/arch/arm/boot/dts/ls1021a-iot.dts
-@@ -0,0 +1,262 @@
-+/*
-+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+
-+/dts-v1/;
-+#include "ls1021a.dtsi"
-+
-+/ {
-+ model = "LS1021A IOT Board";
-+
-+ sys_mclk: clock-mclk {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <24576000>;
-+ };
-+
-+ regulators {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ reg_3p3v: regulator@0 {
-+ compatible = "regulator-fixed";
-+ reg = <0>;
-+ regulator-name = "3P3V";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-always-on;
-+ };
-+
-+ reg_2p5v: regulator@1 {
-+ compatible = "regulator-fixed";
-+ reg = <1>;
-+ regulator-name = "2P5V";
-+ regulator-min-microvolt = <2500000>;
-+ regulator-max-microvolt = <2500000>;
-+ regulator-always-on;
-+ };
-+ };
-+
-+ sound {
-+ compatible = "simple-audio-card";
-+ simple-audio-card,format = "i2s";
-+ simple-audio-card,widgets =
-+ "Microphone", "Microphone Jack",
-+ "Headphone", "Headphone Jack",
-+ "Speaker", "Speaker Ext",
-+ "Line", "Line In Jack";
-+ simple-audio-card,routing =
-+ "MIC_IN", "Microphone Jack",
-+ "Microphone Jack", "Mic Bias",
-+ "LINE_IN", "Line In Jack",
-+ "Headphone Jack", "HP_OUT",
-+ "Speaker Ext", "LINE_OUT";
-+
-+ simple-audio-card,cpu {
-+ sound-dai = <&sai2>;
-+ frame-master;
-+ bitclock-master;
-+ };
-+
-+ simple-audio-card,codec {
-+ sound-dai = <&codec>;
-+ frame-master;
-+ bitclock-master;
-+ };
-+ };
-+
-+ firmware {
-+ optee {
-+ compatible = "linaro,optee-tz";
-+ method = "smc";
-+ };
-+ };
-+};
-+
-+&enet0 {
-+ tbi-handle = <&tbi1>;
-+ phy-handle = <&phy1>;
-+ phy-connection-type = "sgmii";
-+ status = "okay";
-+};
-+
-+&enet1 {
-+ tbi-handle = <&tbi1>;
-+ phy-handle = <&phy3>;
-+ phy-connection-type = "sgmii";
-+ status = "okay";
-+};
-+
-+&enet2 {
-+ fixed-link = <0 1 1000 0 0>;
-+ phy-connection-type = "rgmii-id";
-+ status = "okay";
-+};
-+
-+&can0{
-+ status = "disabled";
-+};
-+
-+&can1{
-+ status = "disabled";
-+};
-+
-+&can2{
-+ status = "disabled";
-+};
-+
-+&can3{
-+ status = "okay";
-+};
-+
-+&esdhc{
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+
-+ max1239@35 {
-+ compatible = "maxim,max1239";
-+ reg = <0x35>;
-+ #io-channel-cells = <1>;
-+ };
-+
-+ codec: sgtl5000@2a {
-+ #sound-dai-cells=<0x0>;
-+ compatible = "fsl,sgtl5000";
-+ reg = <0x2a>;
-+ VDDA-supply = <®_3p3v>;
-+ VDDIO-supply = <®_2p5v>;
-+ clocks = <&sys_mclk 1>;
-+ };
-+
-+ pca9555: pca9555@23 {
-+ compatible = "nxp,pca9555";
-+ /*pinctrl-names = "default";*/
-+ /*interrupt-parent = <&gpio2>;
-+ interrupts = <19 0x2>;*/
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+ interrupt-controller;
-+ #interrupt-cells = <2>;
-+ reg = <0x23>;
-+ };
-+
-+ ina220@44 {
-+ compatible = "ti,ina220";
-+ reg = <0x44>;
-+ shunt-resistor = <1000>;
-+ };
-+
-+ ina220@45 {
-+ compatible = "ti,ina220";
-+ reg = <0x45>;
-+ shunt-resistor = <1000>;
-+ };
-+
-+ lm75b@48 {
-+ compatible = "nxp,lm75a";
-+ reg = <0x48>;
-+ };
-+
-+ adt7461a@4c {
-+ compatible = "adt7461a";
-+ reg = <0x4c>;
-+ };
-+
-+ hdmi: sii9022a@39 {
-+ compatible = "fsl,sii902x";
-+ reg = <0x39>;
-+ interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
-+ };
-+};
-+
-+&i2c1 {
-+ status = "disabled";
-+};
-+
-+&ifc {
-+ status = "disabled";
-+};
-+
-+&lpuart0 {
-+ status = "okay";
-+};
-+
-+&mdio0 {
-+ phy0: ethernet-phy@0 {
-+ reg = <0x0>;
-+ };
-+ phy1: ethernet-phy@1 {
-+ reg = <0x1>;
-+ };
-+ phy2: ethernet-phy@2 {
-+ reg = <0x2>;
-+ };
-+ phy3: ethernet-phy@3 {
-+ reg = <0x3>;
-+ };
-+ tbi1: tbi-phy@1f {
-+ reg = <0x1f>;
-+ device_type = "tbi-phy";
-+ };
-+};
-+
-+&qspi {
-+ num-cs = <2>;
-+ status = "okay";
-+
-+ qflash0: s25fl128s@0 {
-+ compatible = "spansion,s25fl129p1";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ spi-max-frequency = <20000000>;
-+ reg = <0>;
-+ };
-+};
-+
-+&sai2 {
-+ status = "okay";
-+};
-+
-+&uart0 {
-+ status = "okay";
-+};
-+
-+&uart1 {
-+ status = "okay";
-+};
-+
-+&dcu {
-+ display = <&display>;
-+ status = "okay";
-+
-+ display: display@0 {
-+ bits-per-pixel = <24>;
-+
-+ display-timings {
-+ native-mode = <&timing0>;
-+
-+ timing0: mode0 {
-+ clock-frequency = <25000000>;
-+ hactive = <640>;
-+ vactive = <480>;
-+ hback-porch = <80>;
-+ hfront-porch = <80>;
-+ vback-porch = <16>;
-+ vfront-porch = <16>;
-+ hsync-len = <12>;
-+ vsync-len = <2>;
-+ hsync-active = <1>;
-+ vsync-active = <1>;
-+ };
-+ };
-+ };
-+};
---- a/arch/arm/boot/dts/ls1021a-qds.dts
-+++ b/arch/arm/boot/dts/ls1021a-qds.dts
-@@ -124,6 +124,21 @@
- };
- };
-
-+&qspi {
-+ num-cs = <2>;
-+ status = "okay";
-+
-+ qflash0: s25fl128s@0 {
-+ compatible = "spansion,m25p80";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ spi-max-frequency = <20000000>;
-+ reg = <0>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <4>;
-+ };
-+};
-+
- &enet0 {
- tbi-handle = <&tbi0>;
- phy-handle = <&sgmii_phy1c>;
-@@ -239,6 +254,11 @@
- device-width = <1>;
- };
-
-+ nand@2,0 {
-+ compatible = "fsl,ifc-nand";
-+ reg = <0x2 0x0 0x10000>;
-+ };
-+
- fpga: board-control@3,0 {
- #address-cells = <1>;
- #size-cells = <1>;
-@@ -316,6 +336,10 @@
- };
- };
-
-+&esdhc {
-+ status = "okay";
-+};
-+
- &sai2 {
- status = "okay";
- };
-@@ -331,3 +355,11 @@
- &uart1 {
- status = "okay";
- };
-+
-+&can0 {
-+ status = "okay";
-+};
-+
-+&can1 {
-+ status = "okay";
-+};
---- a/arch/arm/boot/dts/ls1021a-twr.dts
-+++ b/arch/arm/boot/dts/ls1021a-twr.dts
-@@ -142,6 +142,21 @@
- };
- };
-
-+&qspi {
-+ num-cs = <2>;
-+ status = "okay";
-+
-+ qflash0: n25q128a13@0 {
-+ compatible = "n25q128a13", "jedec,spi-nor";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ spi-max-frequency = <20000000>;
-+ reg = <0>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <4>;
-+ };
-+};
-+
- &enet0 {
- tbi-handle = <&tbi0>;
- phy-handle = <&sgmii_phy2>;
-@@ -235,6 +250,10 @@
- };
- };
-
-+&esdhc {
-+ status = "okay";
-+};
-+
- &sai1 {
- status = "okay";
- };
-@@ -250,3 +269,11 @@
- &uart1 {
- status = "okay";
- };
-+
-+&can0 {
-+ status = "okay";
-+};
-+
-+&can1 {
-+ status = "okay";
-+};
---- a/arch/arm/boot/dts/ls1021a.dtsi
-+++ b/arch/arm/boot/dts/ls1021a.dtsi
-@@ -146,12 +146,13 @@
- ifc: ifc@1530000 {
- compatible = "fsl,ifc", "simple-bus";
- reg = <0x0 0x1530000 0x0 0x10000>;
-+ big-endian;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- dcfg: dcfg@1ee0000 {
- compatible = "fsl,ls1021a-dcfg", "syscon";
-- reg = <0x0 0x1ee0000 0x0 0x10000>;
-+ reg = <0x0 0x1ee0000 0x0 0x1000>;
- big-endian;
- };
-
-@@ -334,25 +335,44 @@
- status = "disabled";
- };
-
-+ qspi: quadspi@1550000 {
-+ compatible = "fsl,ls1021a-qspi";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x1550000 0x0 0x10000>,
-+ <0x0 0x40000000 0x0 0x4000000>;
-+ reg-names = "QuadSPI", "QuadSPI-memory";
-+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "qspi_en", "qspi";
-+ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
-+ big-endian;
-+ status = "disabled";
-+ };
-+
- i2c0: i2c@2180000 {
-- compatible = "fsl,vf610-i2c";
-+ compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2180000 0x0 0x10000>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 1>;
-+ dma-names = "tx", "rx";
-+ dmas = <&edma0 1 39>,
-+ <&edma0 1 38>;
-+ fsl-scl-gpio = <&gpio3 23 0>;
- status = "disabled";
- };
-
- i2c1: i2c@2190000 {
-- compatible = "fsl,vf610-i2c";
-+ compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2190000 0x0 0x10000>;
- interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 1>;
-+ fsl-scl-gpio = <&gpio3 23 0>;
- status = "disabled";
- };
-
-@@ -497,6 +517,17 @@
- status = "disabled";
- };
-
-+ ftm0: ftm0@29d0000 {
-+ compatible = "fsl,ls1021a-ftm-alarm";
-+ reg = <0x0 0x29d0000 0x0 0x10000>,
-+ <0x0 0x1ee2144 0x0 0x4>,
-+ <0x0 0x0157051c 0x0 0x4>;
-+ reg-names = "ftm", "pmctrl", "scrachpad";
-+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
-+ big-endian;
-+ status = "okay";
-+ };
-+
- wdog0: watchdog@2ad0000 {
- compatible = "fsl,imx21-wdt";
- reg = <0x0 0x2ad0000 0x0 0x10000>;
-@@ -550,6 +581,25 @@
- <&clockgen 4 1>;
- };
-
-+ qdma: qdma@8390000 {
-+ compatible = "fsl,ls1021a-qdma";
-+ reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
-+ <0x0 0x8389000 0x0 0x1000>, /* Status regs */
-+ <0x0 0x838a000 0x0 0x2000>; /* Block regs */
-+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "qdma-error",
-+ "qdma-queue0", "qdma-queue1";
-+ channels = <8>;
-+ block-number = <2>;
-+ block-offset = <0x1000>;
-+ queues = <2>;
-+ status-sizes = <64>;
-+ queue-sizes = <64 64>;
-+ big-endian;
-+ };
-+
- dcu: dcu@2ce0000 {
- compatible = "fsl,ls1021a-dcu";
- reg = <0x0 0x2ce0000 0x0 0x10000>;
-@@ -693,6 +743,11 @@
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
-+ configure-gfladj;
-+ usb3-lpm-capable;
-+ snps,dis-u1u2-when-u3-quirk;
-+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+ snps,host-vbus-glitches;
- };
-
- pcie@3400000 {
-@@ -700,7 +755,9 @@
- reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
- 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
-- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
-+ interrupt-names = "pme", "aer";
- fsl,pcie-scfg = <&scfg 0>;
- #address-cells = <3>;
- #size-cells = <2>;
-@@ -716,6 +773,7 @@
- <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
- };
-
- pcie@3500000 {
-@@ -723,7 +781,9 @@
- reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
- 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
-- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
-+ interrupt-names = "pme", "aer";
- fsl,pcie-scfg = <&scfg 1>;
- #address-cells = <3>;
- #size-cells = <2>;
-@@ -739,6 +799,47 @@
- <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
- <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ can0: can@2a70000 {
-+ compatible = "fsl,ls1021ar2-flexcan";
-+ reg = <0x0 0x2a70000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
-+ clock-names = "ipg", "per";
-+ big-endian;
-+ status = "disabled";
-+ };
-+
-+ can1: can@2a80000 {
-+ compatible = "fsl,ls1021ar2-flexcan";
-+ reg = <0x0 0x2a80000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
-+ clock-names = "ipg", "per";
-+ big-endian;
-+ status = "disabled";
-+ };
-+
-+ can2: can@2a90000 {
-+ compatible = "fsl,ls1021ar2-flexcan";
-+ reg = <0x0 0x2a90000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
-+ clock-names = "ipg", "per";
-+ big-endian;
-+ status = "disabled";
-+ };
-+
-+ can3: can@2aa0000 {
-+ compatible = "fsl,ls1021ar2-flexcan";
-+ reg = <0x0 0x2aa0000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
-+ clock-names = "ipg", "per";
-+ big-endian;
-+ status = "disabled";
- };
- };
- };
---- a/arch/arm64/boot/dts/freescale/Makefile
-+++ b/arch/arm64/boot/dts/freescale/Makefile
-@@ -1,19 +1,33 @@
- # SPDX-License-Identifier: GPL-2.0
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
--
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
-+
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += traverse-ls1043v.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += traverse-ls1043s.dtb
-+
- always := $(dtb-y)
- subdir-y := $(dts-dirs)
- clean-files := *.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
-@@ -0,0 +1,126 @@
-+/*
-+ * Device Tree file for NXP LS1012A 2G5RDB Board.
-+ *
-+ * Copyright 2017 NXP
-+ *
-+ * Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPLv2 or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ * a) This library is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of the
-+ * License, or (at your option) any later version.
-+ *
-+ * This library is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ * b) Permission is hereby granted, free of charge, to any person
-+ * obtaining a copy of this software and associated documentation
-+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use,
-+ * copy, modify, merge, publish, distribute, sublicense, and/or
-+ * sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following
-+ * conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be
-+ * included in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+/dts-v1/;
-+
-+#include "fsl-ls1012a.dtsi"
-+
-+/ {
-+ model = "LS1012A 2G5RDB Board";
-+ compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
-+
-+ aliases {
-+ ethernet0 = &pfe_mac0;
-+ ethernet1 = &pfe_mac1;
-+ };
-+};
-+
-+&duart0 {
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+};
-+
-+&qspi {
-+ num-cs = <2>;
-+ bus-num = <0>;
-+ status = "okay";
-+
-+ qflash0: s25fs512s@0 {
-+ compatible = "spansion,m25p80";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ spi-max-frequency = <20000000>;
-+ m25p,fast-read;
-+ reg = <0>;
-+ };
-+};
-+
-+&sata {
-+ status = "okay";
-+};
-+
-+&pfe {
-+ status = "okay";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pfe_mac0: ethernet@0 {
-+ compatible = "fsl,pfe-gemac-port";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0>; /* GEM_ID */
-+ fsl,mdio-mux-val = <0x0>;
-+ phy-mode = "sgmii-2500";
-+ phy-handle = <&sgmii_phy1>;
-+ };
-+
-+ pfe_mac1: ethernet@1 {
-+ compatible = "fsl,pfe-gemac-port";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x1>; /* GEM_ID */
-+ fsl,mdio-mux-val = <0x0>;
-+ phy-mode = "sgmii-2500";
-+ phy-handle = <&sgmii_phy2>;
-+ };
-+
-+ mdio@0 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ sgmii_phy1: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ reg = <0x1>;
-+ };
-+
-+ sgmii_phy2: ethernet-phy@2 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ reg = <0x2>;
-+ };
-+ };
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
-@@ -1,45 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree file for Freescale LS1012A Freedom Board.
- *
- * Copyright 2016 Freescale Semiconductor, Inc.
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
- /dts-v1/;
-
-@@ -49,6 +13,11 @@
- model = "LS1012A Freedom Board";
- compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
-
-+ aliases {
-+ ethernet0 = &pfe_mac0;
-+ ethernet1 = &pfe_mac1;
-+ };
-+
- sys_mclk: clock-mclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
-@@ -110,6 +79,45 @@
- };
- };
-
-+&pfe {
-+ status = "okay";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pfe_mac0: ethernet@0 {
-+ compatible = "fsl,pfe-gemac-port";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0>; /* GEM_ID */
-+ fsl,mdio-mux-val = <0x0>;
-+ phy-mode = "sgmii";
-+ phy-handle = <&sgmii_phy1>;
-+ };
-+
-+ pfe_mac1: ethernet@1 {
-+ compatible = "fsl,pfe-gemac-port";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x1>; /* GEM_ID */
-+ fsl,mdio-mux-val = <0x0>;
-+ phy-mode = "sgmii";
-+ phy-handle = <&sgmii_phy2>;
-+ };
-+
-+ mdio@0 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ sgmii_phy1: ethernet-phy@2 {
-+ reg = <0x2>;
-+ };
-+
-+ sgmii_phy2: ethernet-phy@1 {
-+ reg = <0x1>;
-+ };
-+ };
-+};
-+
- &sai2 {
- status = "okay";
- };
-@@ -117,3 +125,18 @@
- &sata {
- status = "okay";
- };
-+
-+&qspi {
-+ status = "okay";
-+ qflash0: s25fs512s@0 {
-+ compatible = "spansion,m25p80";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ spi-max-frequency = <20000000>;
-+ m25p,fast-read;
-+ reg = <0>;
-+ spi-rx-bus-width = <2>;
-+ spi-tx-bus-width = <2>;
-+ };
-+
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
-@@ -0,0 +1,179 @@
-+/*
-+ * Device Tree file for NXP LS1012A FRWY Board.
-+ *
-+ * Copyright 2018 NXP
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPLv2 or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ * a) This library is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of the
-+ * License, or (at your option) any later version.
-+ *
-+ * This library is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ * b) Permission is hereby granted, free of charge, to any person
-+ * obtaining a copy of this software and associated documentation
-+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use,
-+ * copy, modify, merge, publish, distribute, sublicense, and/or
-+ * sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following
-+ * conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be
-+ * included in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+/dts-v1/;
-+
-+#include "fsl-ls1012a.dtsi"
-+
-+/ {
-+ model = "LS1012A FRWY Board";
-+ compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
-+
-+ aliases {
-+ ethernet0 = &pfe_mac0;
-+ ethernet1 = &pfe_mac1;
-+ };
-+
-+ sys_mclk: clock-mclk {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <25000000>;
-+ };
-+
-+ reg_1p8v: regulator-1p8v {
-+ compatible = "regulator-fixed";
-+ regulator-name = "1P8V";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-always-on;
-+ };
-+
-+ sound {
-+ compatible = "simple-audio-card";
-+ simple-audio-card,format = "i2s";
-+ simple-audio-card,widgets =
-+ "Microphone", "Microphone Jack",
-+ "Headphone", "Headphone Jack",
-+ "Speaker", "Speaker Ext",
-+ "Line", "Line In Jack";
-+ simple-audio-card,routing =
-+ "MIC_IN", "Microphone Jack",
-+ "Microphone Jack", "Mic Bias",
-+ "LINE_IN", "Line In Jack",
-+ "Headphone Jack", "HP_OUT",
-+ "Speaker Ext", "LINE_OUT";
-+
-+ simple-audio-card,cpu {
-+ sound-dai = <&sai2>;
-+ frame-master;
-+ bitclock-master;
-+ };
-+
-+ simple-audio-card,codec {
-+ sound-dai = <&codec>;
-+ frame-master;
-+ bitclock-master;
-+ system-clock-frequency = <25000000>;
-+ };
-+ };
-+};
-+
-+&pcie {
-+ status = "okay";
-+};
-+
-+&duart0 {
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+
-+ codec: sgtl5000@a {
-+ compatible = "fsl,sgtl5000";
-+ #sound-dai-cells = <0>;
-+ reg = <0xa>;
-+ VDDA-supply = <®_1p8v>;
-+ VDDIO-supply = <®_1p8v>;
-+ clocks = <&sys_mclk>;
-+ };
-+};
-+
-+&qspi {
-+ num-cs = <1>;
-+ bus-num = <0>;
-+ status = "okay";
-+
-+ qflash0: w25q16dw@0 {
-+ compatible = "spansion,m25p80";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ m25p,fast-read;
-+ spi-max-frequency = <20000000>;
-+ reg = <0>;
-+ };
-+};
-+
-+&pfe {
-+ status = "okay";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pfe_mac0: ethernet@0 {
-+ compatible = "fsl,pfe-gemac-port";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0>; /* GEM_ID */
-+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
-+ fsl,mdio-mux-val = <0x0>;
-+ phy-mode = "sgmii";
-+ phy-handle = <&sgmii_phy1>;
-+ };
-+
-+ pfe_mac1: ethernet@1 {
-+ compatible = "fsl,pfe-gemac-port";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x1>; /* GEM_ID */
-+ fsl,mdio-mux-val = <0x0>;
-+ phy-mode = "sgmii";
-+ phy-handle = <&sgmii_phy2>;
-+ };
-+
-+ mdio@0 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ sgmii_phy1: ethernet-phy@2 {
-+ reg = <0x2>;
-+ };
-+
-+ sgmii_phy2: ethernet-phy@1 {
-+ reg = <0x1>;
-+ };
-+ };
-+};
-+
-+&sai2 {
-+ status = "okay";
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
-@@ -1,45 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree file for Freescale LS1012A QDS Board.
- *
- * Copyright 2016 Freescale Semiconductor, Inc.
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
- /dts-v1/;
-
-@@ -49,6 +13,11 @@
- model = "LS1012A QDS Board";
- compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
-
-+ aliases {
-+ ethernet0 = &pfe_mac0;
-+ ethernet1 = &pfe_mac1;
-+ };
-+
- sys_mclk: clock-mclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
-@@ -93,6 +62,43 @@
- };
- };
-
-+&pcie {
-+ status = "okay";
-+};
-+
-+&dspi {
-+ bus-num = <0>;
-+ status = "okay";
-+
-+ flash@0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "n25q128a11", "jedec,spi-nor";
-+ reg = <0>;
-+ spi-max-frequency = <10000000>;
-+ };
-+
-+ flash@1 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "sst25wf040b", "jedec,spi-nor";
-+ spi-cpol;
-+ spi-cpha;
-+ reg = <1>;
-+ spi-max-frequency = <10000000>;
-+ };
-+
-+ flash@2 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "en25s64", "jedec,spi-nor";
-+ spi-cpol;
-+ spi-cpha;
-+ reg = <2>;
-+ spi-max-frequency = <10000000>;
-+ };
-+};
-+
- &duart0 {
- status = "okay";
- };
-@@ -131,6 +137,47 @@
- };
- };
-
-+&pfe {
-+ status = "okay";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pfe_mac0: ethernet@0 {
-+ compatible = "fsl,pfe-gemac-port";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0>; /* GEM_ID */
-+ fsl,mdio-mux-val = <0x2>;
-+ phy-mode = "sgmii-2500";
-+ phy-handle = <&sgmii_phy1>;
-+ };
-+
-+ pfe_mac1: ethernet@1 {
-+ compatible = "fsl,pfe-gemac-port";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x1>; /* GEM_ID */
-+ fsl,mdio-mux-val = <0x3>;
-+ phy-mode = "sgmii-2500";
-+ phy-handle = <&sgmii_phy2>;
-+ };
-+
-+ mdio@0 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ sgmii_phy1: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ reg = <0x1>;
-+ };
-+
-+ sgmii_phy2: ethernet-phy@2 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ reg = <0x2>;
-+ };
-+ };
-+};
-+
- &sai2 {
- status = "okay";
- };
-@@ -138,3 +185,18 @@
- &sata {
- status = "okay";
- };
-+
-+&qspi {
-+ status = "okay";
-+ qflash0: s25fs512s@0 {
-+ compatible = "spansion,m25p80";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ spi-max-frequency = <20000000>;
-+ m25p,fast-read;
-+ reg = <0>;
-+ spi-rx-bus-width = <2>;
-+ spi-tx-bus-width = <2>;
-+ };
-+
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
-@@ -1,45 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree file for Freescale LS1012A RDB Board.
- *
- * Copyright 2016 Freescale Semiconductor, Inc.
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
- /dts-v1/;
-
-@@ -48,6 +12,15 @@
- / {
- model = "LS1012A RDB Board";
- compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
-+
-+ aliases {
-+ ethernet0 = &pfe_mac0;
-+ ethernet1 = &pfe_mac1;
-+ };
-+};
-+
-+&pcie {
-+ status = "okay";
- };
-
- &duart0 {
-@@ -74,3 +47,56 @@
- &sata {
- status = "okay";
- };
-+
-+&pfe {
-+ status = "okay";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pfe_mac0: ethernet@0 {
-+ compatible = "fsl,pfe-gemac-port";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0>; /* GEM_ID */
-+ fsl,mdio-mux-val = <0x0>;
-+ phy-mode = "sgmii";
-+ phy-handle = <&sgmii_phy>;
-+ };
-+
-+ pfe_mac1: ethernet@1 {
-+ compatible = "fsl,pfe-gemac-port";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x1>; /* GEM_ID */
-+ fsl,mdio-mux-val = <0x0>;
-+ phy-mode = "rgmii-txid";
-+ phy-handle = <&rgmii_phy>;
-+ };
-+ mdio@0 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ sgmii_phy: ethernet-phy@2 {
-+ reg = <0x2>;
-+ };
-+
-+ rgmii_phy: ethernet-phy@1 {
-+ reg = <0x1>;
-+ };
-+ };
-+};
-+
-+&qspi {
-+ status = "okay";
-+ qflash0: s25fs512s@0 {
-+ compatible = "spansion,m25p80";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ spi-max-frequency = <20000000>;
-+ m25p,fast-read;
-+ reg = <0>;
-+ spi-rx-bus-width = <2>;
-+ spi-tx-bus-width = <2>;
-+ };
-+
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
-@@ -1,45 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree Include file for Freescale Layerscape-1012A family SoC.
- *
- * Copyright 2016 Freescale Semiconductor, Inc.
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- #include <dt-bindings/interrupt-controller/arm-gic.h>
-@@ -64,12 +28,30 @@
- #address-cells = <1>;
- #size-cells = <0>;
-
-- cpu0: cpu@0 {
-+ cooling_map0: cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0>;
- clocks = <&clockgen 1 0>;
- #cooling-cells = <2>;
-+ cpu-idle-states = <&CPU_PH20>;
-+ };
-+ };
-+
-+ idle-states {
-+ /*
-+ * PSCI node is not added default, U-boot will add missing
-+ * parts if it determines to use PSCI.
-+ */
-+ entry-method = "arm,psci";
-+
-+ CPU_PH20: cpu-ph20 {
-+ compatible = "arm,idle-state";
-+ idle-state-name = "PH20";
-+ arm,psci-suspend-param = <0x0>;
-+ entry-latency-us = <1000>;
-+ exit-latency-us = <1000>;
-+ min-residency-us = <3000>;
- };
- };
-
-@@ -247,7 +229,7 @@
- dcfg: dcfg@1ee0000 {
- compatible = "fsl,ls1012a-dcfg",
- "syscon";
-- reg = <0x0 0x1ee0000 0x0 0x10000>;
-+ reg = <0x0 0x1ee0000 0x0 0x1000>;
- big-endian;
- };
-
-@@ -304,44 +286,25 @@
- #thermal-sensor-cells = <1>;
- };
-
-- thermal-zones {
-- cpu_thermal: cpu-thermal {
-- polling-delay-passive = <1000>;
-- polling-delay = <5000>;
-- thermal-sensors = <&tmu 0>;
--
-- trips {
-- cpu_alert: cpu-alert {
-- temperature = <85000>;
-- hysteresis = <2000>;
-- type = "passive";
-- };
--
-- cpu_crit: cpu-crit {
-- temperature = <95000>;
-- hysteresis = <2000>;
-- type = "critical";
-- };
-- };
-+ #include "fsl-tmu.dtsi"
-
-- cooling-maps {
-- map0 {
-- trip = <&cpu_alert>;
-- cooling-device =
-- <&cpu0 THERMAL_NO_LIMIT
-- THERMAL_NO_LIMIT>;
-- };
-- };
-- };
-+ ftm0: ftm0@29d0000 {
-+ compatible = "fsl,ls1012a-ftm-alarm";
-+ reg = <0x0 0x29d0000 0x0 0x10000>,
-+ <0x0 0x1ee2140 0x0 0x4>;
-+ reg-names = "ftm", "pmctrl";
-+ interrupts = <0 86 0x4>;
-+ big-endian;
- };
-
- i2c0: i2c@2180000 {
-- compatible = "fsl,vf610-i2c";
-+ compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2180000 0x0 0x10000>;
- interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&clockgen 4 0>;
-+ clocks = <&clockgen 4 3>;
-+ scl-gpios = <&gpio0 13 0>;
- status = "disabled";
- };
-
-@@ -351,7 +314,20 @@
- #size-cells = <0>;
- reg = <0x0 0x2190000 0x0 0x10000>;
- interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 3>;
-+ status = "disabled";
-+ };
-+
-+ dspi: dspi@2100000 {
-+ compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2100000 0x0 0x10000>;
-+ interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "dspi";
- clocks = <&clockgen 4 0>;
-+ spi-num-chipselects = <5>;
-+ big-endian;
- status = "disabled";
- };
-
-@@ -400,6 +376,20 @@
- big-endian;
- };
-
-+ qspi: quadspi@1550000 {
-+ compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x1550000 0x0 0x10000>,
-+ <0x0 0x40000000 0x0 0x10000000>;
-+ reg-names = "QuadSPI", "QuadSPI-memory";
-+ interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "qspi_en", "qspi";
-+ clocks = <&clockgen 4 0>, <&clockgen 4 0>;
-+ big-endian;
-+ status = "disabled";
-+ };
-+
- sai1: sai@2b50000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,vf610-sai";
-@@ -451,6 +441,8 @@
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
-+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+ snps,host-vbus-glitches;
- };
-
- sata: sata@3200000 {
-@@ -471,5 +463,85 @@
- dr_mode = "host";
- phy_type = "ulpi";
- };
-+
-+ msi: msi-controller1@1572000 {
-+ compatible = "fsl,ls1012a-msi";
-+ reg = <0x0 0x1572000 0x0 0x8>;
-+ msi-controller;
-+ interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ pcie: pcie@3400000 {
-+ compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
-+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
-+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
-+ reg-names = "regs", "config";
-+ interrupts = <0 118 0x4>, /* AER interrupt */
-+ <0 117 0x4>; /* PME interrupt */
-+ interrupt-names = "aer", "pme";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ num-lanes = <4>;
-+ bus-range = <0x0 0xff>;
-+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
-+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+ msi-parent = <&msi>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ rcpm: rcpm@1ee2000 {
-+ compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
-+ reg = <0x0 0x1ee2000 0x0 0x1000>;
-+ fsl,#rcpm-wakeup-cells = <1>;
-+ };
-+ };
-+
-+ reserved-memory {
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ pfe_reserved: packetbuffer@83400000 {
-+ reg = <0 0x83400000 0 0xc00000>;
-+ };
-+ };
-+
-+ pfe: pfe@04000000 {
-+ compatible = "fsl,pfe";
-+ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
-+ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
-+ reg-names = "pfe", "pfe-ddr";
-+ fsl,pfe-num-interfaces = <0x2>;
-+ interrupts = <0 172 0x4>, /* HIF interrupt */
-+ <0 173 0x4>, /*HIF_NOCPY interrupt */
-+ <0 174 0x4>; /* WoL interrupt */
-+ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
-+ memory-region = <&pfe_reserved>;
-+ fsl,pfe-scfg = <&scfg 0>;
-+ fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
-+ clocks = <&clockgen 4 0>;
-+ clock-names = "pfe";
-+
-+ status = "okay";
-+ };
-+
-+ firmware {
-+ optee {
-+ compatible = "linaro,optee-tz";
-+ method = "smc";
-+ };
-+ };
-+};
-+
-+&thermal_zones {
-+ thermal-zone0 {
-+ status = "okay";
- };
- };
---- a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
-@@ -1,9 +1,8 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
- * QorIQ FMan v3 device tree nodes for ls1043
- *
- * Copyright 2015-2016 Freescale Semiconductor Inc.
-- *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- */
-
- &soc {
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
-@@ -0,0 +1,263 @@
-+/*
-+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
-+ *
-+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
-+ *
-+ * Mingkai Hu <Mingkai.hu@freescale.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPLv2 or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ * a) This library is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of the
-+ * License, or (at your option) any later version.
-+ *
-+ * This library is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ * b) Permission is hereby granted, free of charge, to any person
-+ * obtaining a copy of this software and associated documentation
-+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use,
-+ * copy, modify, merge, publish, distribute, sublicense, and/or
-+ * sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following
-+ * conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be
-+ * included in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#include "fsl-ls1043a-qds.dts"
-+#include "qoriq-qman-portals-sdk.dtsi"
-+#include "qoriq-bman-portals-sdk.dtsi"
-+
-+&bman_fbpr {
-+ compatible = "fsl,bman-fbpr";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_fqd {
-+ compatible = "fsl,qman-fqd";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_pfdr {
-+ compatible = "fsl,qman-pfdr";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+
-+&soc {
-+/delete-property/ dma-coherent;
-+
-+#include "qoriq-dpaa-eth.dtsi"
-+#include "qoriq-fman3-0-6oh.dtsi"
-+
-+pcie@3400000 {
-+ /delete-property/ iommu-map;
-+ dma-coherent;
-+};
-+
-+pcie@3500000 {
-+ /delete-property/ iommu-map;
-+ dma-coherent;
-+};
-+
-+pcie@3600000 {
-+ /delete-property/ iommu-map;
-+ dma-coherent;
-+};
-+
-+/delete-node/ iommu@9000000;
-+};
-+
-+&fman0 {
-+ compatible = "fsl,fman", "simple-bus";
-+ dma-coherent;
-+};
-+
-+&clockgen {
-+ dma-coherent;
-+};
-+
-+&scfg {
-+ dma-coherent;
-+};
-+
-+&crypto {
-+ dma-coherent;
-+};
-+
-+&dcfg {
-+ dma-coherent;
-+};
-+
-+&ifc {
-+ dma-coherent;
-+};
-+
-+&qspi {
-+ dma-coherent;
-+};
-+
-+&esdhc {
-+ dma-coherent;
-+};
-+
-+&ddr {
-+ dma-coherent;
-+};
-+
-+&tmu {
-+ dma-coherent;
-+};
-+
-+&qman {
-+ dma-coherent;
-+};
-+
-+&bman {
-+ dma-coherent;
-+};
-+
-+&bportals {
-+ dma-coherent;
-+};
-+
-+&qportals {
-+ dma-coherent;
-+};
-+
-+&dspi0 {
-+ dma-coherent;
-+};
-+
-+&dspi1 {
-+ dma-coherent;
-+};
-+
-+&i2c0 {
-+ dma-coherent;
-+};
-+
-+&i2c1 {
-+ dma-coherent;
-+};
-+
-+&i2c2 {
-+ dma-coherent;
-+};
-+
-+&i2c3 {
-+ dma-coherent;
-+};
-+
-+&duart0 {
-+ dma-coherent;
-+};
-+
-+&duart1 {
-+ dma-coherent;
-+};
-+
-+&duart2 {
-+ dma-coherent;
-+};
-+
-+&duart3 {
-+ dma-coherent;
-+};
-+
-+&gpio1 {
-+ dma-coherent;
-+};
-+
-+&gpio2 {
-+ dma-coherent;
-+};
-+
-+&gpio3 {
-+ dma-coherent;
-+};
-+
-+&gpio4 {
-+ dma-coherent;
-+};
-+
-+&uqe {
-+ dma-coherent;
-+};
-+
-+&lpuart0 {
-+ dma-coherent;
-+};
-+
-+&lpuart1 {
-+ dma-coherent;
-+};
-+
-+&lpuart2 {
-+ dma-coherent;
-+};
-+
-+&lpuart3 {
-+ dma-coherent;
-+};
-+
-+&lpuart4 {
-+ dma-coherent;
-+};
-+
-+&lpuart5 {
-+ dma-coherent;
-+};
-+
-+&ftm0 {
-+ dma-coherent;
-+};
-+
-+&wdog0 {
-+ dma-coherent;
-+};
-+
-+&edma0 {
-+ dma-coherent;
-+};
-+
-+&qdma {
-+ dma-coherent;
-+};
-+
-+&msi1 {
-+ dma-coherent;
-+};
-+
-+&msi2 {
-+ dma-coherent;
-+};
-+
-+&msi3 {
-+ dma-coherent;
-+};
-+
-+&ptp_timer0 {
-+ dma-coherent;
-+};
-+
-+&fsldpaa {
-+ dma-coherent;
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
-@@ -1,47 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree Include file for Freescale Layerscape-1043A family SoC.
- *
- * Copyright 2014-2015 Freescale Semiconductor, Inc.
- *
- * Mingkai Hu <Mingkai.hu@freescale.com>
-- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- /dts-v1/;
-@@ -60,6 +23,22 @@
- serial1 = &duart1;
- serial2 = &duart2;
- serial3 = &duart3;
-+ sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
-+ sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
-+ sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
-+ sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
-+ qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
-+ qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
-+ qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
-+ qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
-+ qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
-+ qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
-+ qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
-+ qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
-+ emi1_slot1 = &ls1043mdio_s1;
-+ emi1_slot2 = &ls1043mdio_s2;
-+ emi1_slot3 = &ls1043mdio_s3;
-+ emi1_slot4 = &ls1043mdio_s4;
- };
-
- chosen {
-@@ -97,8 +76,11 @@
- };
-
- fpga: board-control@2,0 {
-- compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
-+ compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus";
- reg = <0x2 0x0 0x0000100>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0 2 0 0x100>;
- };
- };
-
-@@ -179,7 +161,153 @@
- #size-cells = <1>;
- spi-max-frequency = <20000000>;
- reg = <0>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <4>;
- };
- };
-
- #include "fsl-ls1043-post.dtsi"
-+
-+&fman0 {
-+ ethernet@e0000 {
-+ phy-handle = <&qsgmii_phy_s2_p1>;
-+ phy-connection-type = "sgmii";
-+ };
-+
-+ ethernet@e2000 {
-+ phy-handle = <&qsgmii_phy_s2_p2>;
-+ phy-connection-type = "sgmii";
-+ };
-+
-+ ethernet@e4000 {
-+ phy-handle = <&rgmii_phy1>;
-+ phy-connection-type = "rgmii";
-+ };
-+
-+ ethernet@e6000 {
-+ phy-handle = <&rgmii_phy2>;
-+ phy-connection-type = "rgmii";
-+ };
-+
-+ ethernet@e8000 {
-+ phy-handle = <&qsgmii_phy_s2_p3>;
-+ phy-connection-type = "sgmii";
-+ };
-+
-+ ethernet@ea000 {
-+ phy-handle = <&qsgmii_phy_s2_p4>;
-+ phy-connection-type = "sgmii";
-+ };
-+
-+ ethernet@f0000 { /* DTSEC9/10GEC1 */
-+ fixed-link = <1 1 10000 0 0>;
-+ phy-connection-type = "xgmii";
-+ };
-+};
-+
-+&fpga {
-+ mdio-mux-emi1 {
-+ compatible = "mdio-mux-mmioreg", "mdio-mux";
-+ mdio-parent-bus = <&mdio0>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x54 1>; /* BRDCFG4 */
-+ mux-mask = <0xe0>; /* EMI1 */
-+
-+ /* On-board RGMII1 PHY */
-+ ls1043mdio0: mdio@0 {
-+ reg = <0>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ rgmii_phy1: ethernet-phy@1 { /* MAC3 */
-+ reg = <0x1>;
-+ };
-+ };
-+
-+ /* On-board RGMII2 PHY */
-+ ls1043mdio1: mdio@1 {
-+ reg = <0x20>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ rgmii_phy2: ethernet-phy@2 { /* MAC4 */
-+ reg = <0x2>;
-+ };
-+ };
-+
-+ /* Slot 1 */
-+ ls1043mdio_s1: mdio@2 {
-+ reg = <0x40>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+
-+ qsgmii_phy_s1_p1: ethernet-phy@4 {
-+ reg = <0x4>;
-+ };
-+ qsgmii_phy_s1_p2: ethernet-phy@5 {
-+ reg = <0x5>;
-+ };
-+ qsgmii_phy_s1_p3: ethernet-phy@6 {
-+ reg = <0x6>;
-+ };
-+ qsgmii_phy_s1_p4: ethernet-phy@7 {
-+ reg = <0x7>;
-+ };
-+
-+ sgmii_phy_s1_p1: ethernet-phy@1c {
-+ reg = <0x1c>;
-+ };
-+ };
-+
-+ /* Slot 2 */
-+ ls1043mdio_s2: mdio@3 {
-+ reg = <0x60>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+
-+ qsgmii_phy_s2_p1: ethernet-phy@8 {
-+ reg = <0x8>;
-+ };
-+ qsgmii_phy_s2_p2: ethernet-phy@9 {
-+ reg = <0x9>;
-+ };
-+ qsgmii_phy_s2_p3: ethernet-phy@a {
-+ reg = <0xa>;
-+ };
-+ qsgmii_phy_s2_p4: ethernet-phy@b {
-+ reg = <0xb>;
-+ };
-+
-+ sgmii_phy_s2_p1: ethernet-phy@1c {
-+ reg = <0x1c>;
-+ };
-+ };
-+
-+ /* Slot 3 */
-+ ls1043mdio_s3: mdio@4 {
-+ reg = <0x80>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+
-+ sgmii_phy_s3_p1: ethernet-phy@1c {
-+ reg = <0x1c>;
-+ };
-+ };
-+
-+ /* Slot 4 */
-+ ls1043mdio_s4: mdio@5 {
-+ reg = <0xa0>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+
-+ sgmii_phy_s4_p1: ethernet-phy@1c {
-+ reg = <0x1c>;
-+ };
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
-@@ -0,0 +1,262 @@
-+/*
-+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
-+ *
-+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
-+ *
-+ * Mingkai Hu <Mingkai.hu@freescale.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPLv2 or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ * a) This library is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of the
-+ * License, or (at your option) any later version.
-+ *
-+ * This library is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ * b) Permission is hereby granted, free of charge, to any person
-+ * obtaining a copy of this software and associated documentation
-+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use,
-+ * copy, modify, merge, publish, distribute, sublicense, and/or
-+ * sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following
-+ * conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be
-+ * included in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#include "fsl-ls1043a-rdb.dts"
-+#include "qoriq-qman-portals-sdk.dtsi"
-+#include "qoriq-bman-portals-sdk.dtsi"
-+
-+&bman_fbpr {
-+ compatible = "fsl,bman-fbpr";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_fqd {
-+ compatible = "fsl,qman-fqd";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_pfdr {
-+ compatible = "fsl,qman-pfdr";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+
-+&soc {
-+/delete-property/ dma-coherent;
-+
-+#include "qoriq-dpaa-eth.dtsi"
-+#include "qoriq-fman3-0-6oh.dtsi"
-+
-+pcie@3400000 {
-+ /delete-property/ iommu-map;
-+ dma-coherent;
-+};
-+
-+pcie@3500000 {
-+ /delete-property/ iommu-map;
-+ dma-coherent;
-+};
-+
-+pcie@3600000 {
-+ /delete-property/ iommu-map;
-+ dma-coherent;
-+};
-+
-+/delete-node/ iommu@9000000;
-+};
-+
-+&fman0 {
-+ compatible = "fsl,fman", "simple-bus";
-+};
-+
-+&clockgen {
-+ dma-coherent;
-+};
-+
-+&scfg {
-+ dma-coherent;
-+};
-+
-+&crypto {
-+ dma-coherent;
-+};
-+
-+&dcfg {
-+ dma-coherent;
-+};
-+
-+&ifc {
-+ dma-coherent;
-+};
-+
-+&qspi {
-+ dma-coherent;
-+};
-+
-+&esdhc {
-+ dma-coherent;
-+};
-+
-+&ddr {
-+ dma-coherent;
-+};
-+
-+&tmu {
-+ dma-coherent;
-+};
-+
-+&qman {
-+ dma-coherent;
-+};
-+
-+&bman {
-+ dma-coherent;
-+};
-+
-+&bportals {
-+ dma-coherent;
-+};
-+
-+&qportals {
-+ dma-coherent;
-+};
-+
-+&dspi0 {
-+ dma-coherent;
-+};
-+
-+&dspi1 {
-+ dma-coherent;
-+};
-+
-+&i2c0 {
-+ dma-coherent;
-+};
-+
-+&i2c1 {
-+ dma-coherent;
-+};
-+
-+&i2c2 {
-+ dma-coherent;
-+};
-+
-+&i2c3 {
-+ dma-coherent;
-+};
-+
-+&duart0 {
-+ dma-coherent;
-+};
-+
-+&duart1 {
-+ dma-coherent;
-+};
-+
-+&duart2 {
-+ dma-coherent;
-+};
-+
-+&duart3 {
-+ dma-coherent;
-+};
-+
-+&gpio1 {
-+ dma-coherent;
-+};
-+
-+&gpio2 {
-+ dma-coherent;
-+};
-+
-+&gpio3 {
-+ dma-coherent;
-+};
-+
-+&gpio4 {
-+ dma-coherent;
-+};
-+
-+&lpuart0 {
-+ dma-coherent;
-+};
-+
-+&lpuart1 {
-+ dma-coherent;
-+};
-+
-+&lpuart2 {
-+ dma-coherent;
-+};
-+
-+&lpuart3 {
-+ dma-coherent;
-+};
-+
-+&lpuart4 {
-+ dma-coherent;
-+};
-+
-+&lpuart5 {
-+ dma-coherent;
-+};
-+
-+&ftm0 {
-+ dma-coherent;
-+};
-+
-+&wdog0 {
-+ dma-coherent;
-+};
-+
-+&edma0 {
-+ dma-coherent;
-+};
-+
-+&qdma {
-+ dma-coherent;
-+};
-+
-+&msi1 {
-+ dma-coherent;
-+};
-+
-+&msi2 {
-+ dma-coherent;
-+};
-+
-+&msi3 {
-+ dma-coherent;
-+};
-+
-+&fman0 {
-+ dma-coherent;
-+};
-+
-+&ptp_timer0 {
-+ dma-coherent;
-+};
-+
-+&fsldpaa {
-+ dma-coherent;
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
-@@ -0,0 +1,140 @@
-+/*
-+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
-+ *
-+ * Copyright (C) 2014-2015, Freescale Semiconductor
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#include "fsl-ls1043a-rdb-sdk.dts"
-+
-+&soc {
-+ bp7: buffer-pool@7 {
-+ compatible = "fsl,p4080-bpool", "fsl,bpool";
-+ fsl,bpid = <7>;
-+ fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
-+ fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
-+ dma-coherent;
-+ };
-+
-+ bp8: buffer-pool@8 {
-+ compatible = "fsl,p4080-bpool", "fsl,bpool";
-+ fsl,bpid = <8>;
-+ fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
-+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
-+ dma-coherent;
-+ };
-+
-+ bp9: buffer-pool@9 {
-+ compatible = "fsl,p4080-bpool", "fsl,bpool";
-+ fsl,bpid = <9>;
-+ fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
-+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
-+ dma-coherent;
-+ };
-+
-+ fsl,dpaa {
-+ compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
-+ dma-coherent;
-+
-+ ethernet@0 {
-+ compatible = "fsl,dpa-ethernet-init";
-+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+ fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
-+ fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
-+ };
-+
-+ ethernet@1 {
-+ compatible = "fsl,dpa-ethernet-init";
-+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+ fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
-+ fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
-+ };
-+
-+ ethernet@2 {
-+ compatible = "fsl,dpa-ethernet-init";
-+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+ fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
-+ fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
-+ };
-+
-+ ethernet@3 {
-+ compatible = "fsl,dpa-ethernet-init";
-+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+ fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
-+ fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
-+ };
-+
-+ ethernet@4 {
-+ compatible = "fsl,dpa-ethernet-init";
-+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+ fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
-+ fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
-+ };
-+
-+ ethernet@5 {
-+ compatible = "fsl,dpa-ethernet-init";
-+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+ fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
-+ fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
-+ };
-+
-+ ethernet@8 {
-+ compatible = "fsl,dpa-ethernet-init";
-+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+ fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
-+ fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
-+
-+ };
-+ dpa-fman0-oh@2 {
-+ compatible = "fsl,dpa-oh";
-+ /* Define frame queues for the OH port*/
-+ /* <OH Rx error, OH Rx default> */
-+ fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
-+ fsl,fman-oh-port = <&fman0_oh2>;
-+ };
-+ };
-+
-+ pcie@3400000 {
-+ /delete-property/ iommu-map;
-+ };
-+
-+ pcie@3500000 {
-+ /delete-property/ iommu-map;
-+ };
-+
-+ pcie@3600000 {
-+ /delete-property/ iommu-map;
-+ };
-+
-+ /delete-node/ iommu@9000000;
-+};
-+/ {
-+ reserved-memory {
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ /* For legacy usdpaa based use-cases, update the size and
-+ alignment parameters. e.g. to allocate 256 MB memory:
-+ size = <0 0x10000000>;
-+ alignment = <0 0x10000000>;
-+ */
-+ usdpaa_mem: usdpaa_mem {
-+ compatible = "fsl,usdpaa-mem";
-+ alloc-ranges = <0 0 0x10000 0>;
-+ size = <0 0x1000>;
-+ alignment = <0 0x1000>;
-+ };
-+ };
-+};
-+
-+&fman0 {
-+ fman0_oh2: port@83000 {
-+ cell-index = <1>;
-+ compatible = "fsl,fman-port-oh";
-+ reg = <0x83000 0x1000>;
-+ };
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
-@@ -1,47 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree Include file for Freescale Layerscape-1043A family SoC.
- *
- * Copyright 2014-2015 Freescale Semiconductor, Inc.
- *
- * Mingkai Hu <Mingkai.hu@freescale.com>
-- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- /dts-v1/;
-@@ -51,7 +14,6 @@
- model = "LS1043A RDB Board";
-
- aliases {
-- crypto = &crypto;
- serial0 = &duart0;
- serial1 = &duart1;
- serial2 = &duart2;
-@@ -86,6 +48,10 @@
- compatible = "pericom,pt7c4338";
- reg = <0x68>;
- };
-+ rtc@51 {
-+ compatible = "nxp,pcf85263";
-+ reg = <0x51>;
-+ };
- };
-
- &ifc {
-@@ -130,6 +96,38 @@
- reg = <0>;
- spi-max-frequency = <1000000>; /* input clock */
- };
-+
-+ slic@2 {
-+ compatible = "maxim,ds26522";
-+ reg = <2>;
-+ spi-max-frequency = <2000000>;
-+ fsl,spi-cs-sck-delay = <100>;
-+ fsl,spi-sck-cs-delay = <50>;
-+ };
-+
-+ slic@3 {
-+ compatible = "maxim,ds26522";
-+ reg = <3>;
-+ spi-max-frequency = <2000000>;
-+ fsl,spi-cs-sck-delay = <100>;
-+ fsl,spi-sck-cs-delay = <50>;
-+ };
-+};
-+
-+&uqe {
-+ ucc_hdlc: ucc@2000 {
-+ compatible = "fsl,ucc-hdlc";
-+ rx-clock-name = "clk8";
-+ tx-clock-name = "clk9";
-+ fsl,rx-sync-clock = "rsync_pin";
-+ fsl,tx-sync-clock = "tsync_pin";
-+ fsl,tx-timeslot-mask = <0xfffffffe>;
-+ fsl,rx-timeslot-mask = <0xfffffffe>;
-+ fsl,tdm-framer-type = "e1";
-+ fsl,tdm-id = <0>;
-+ fsl,siram-entry-id = <0>;
-+ fsl,tdm-interface;
-+ };
- };
-
- &duart0 {
---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
-@@ -1,47 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree Include file for Freescale Layerscape-1043A family SoC.
- *
- * Copyright 2014-2015 Freescale Semiconductor, Inc.
- *
- * Mingkai Hu <Mingkai.hu@freescale.com>
-- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- #include <dt-bindings/thermal/thermal.h>
-@@ -54,6 +17,7 @@
- #size-cells = <2>;
-
- aliases {
-+ crypto = &crypto;
- fman0 = &fman0;
- ethernet0 = &enet0;
- ethernet1 = &enet1;
-@@ -74,13 +38,14 @@
- *
- * Currently supported enable-method is psci v0.2
- */
-- cpu0: cpu@0 {
-+ cooling_map0: cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0>;
- clocks = <&clockgen 1 0>;
- next-level-cache = <&l2>;
- #cooling-cells = <2>;
-+ cpu-idle-states = <&CPU_PH20>;
- };
-
- cpu1: cpu@1 {
-@@ -89,6 +54,7 @@
- reg = <0x1>;
- clocks = <&clockgen 1 0>;
- next-level-cache = <&l2>;
-+ cpu-idle-states = <&CPU_PH20>;
- };
-
- cpu2: cpu@2 {
-@@ -97,6 +63,7 @@
- reg = <0x2>;
- clocks = <&clockgen 1 0>;
- next-level-cache = <&l2>;
-+ cpu-idle-states = <&CPU_PH20>;
- };
-
- cpu3: cpu@3 {
-@@ -105,6 +72,7 @@
- reg = <0x3>;
- clocks = <&clockgen 1 0>;
- next-level-cache = <&l2>;
-+ cpu-idle-states = <&CPU_PH20>;
- };
-
- l2: l2-cache {
-@@ -112,6 +80,23 @@
- };
- };
-
-+ idle-states {
-+ /*
-+ * PSCI node is not added default, U-boot will add missing
-+ * parts if it determines to use PSCI.
-+ */
-+ entry-method = "arm,psci";
-+
-+ CPU_PH20: cpu-ph20 {
-+ compatible = "arm,idle-state";
-+ idle-state-name = "PH20";
-+ arm,psci-suspend-param = <0x0>;
-+ entry-latency-us = <1000>;
-+ exit-latency-us = <1000>;
-+ min-residency-us = <3000>;
-+ };
-+ };
-+
- memory@80000000 {
- device_type = "memory";
- reg = <0x0 0x80000000 0 0x80000000>;
-@@ -196,6 +181,8 @@
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
-+ dma-coherent;
-
- clockgen: clocking@1ee1000 {
- compatible = "fsl,ls1043a-clockgen";
-@@ -204,6 +191,49 @@
- clocks = <&sysclk>;
- };
-
-+ smmu: iommu@9000000 {
-+ compatible = "arm,mmu-500";
-+ reg = <0 0x9000000 0 0x400000>;
-+ dma-coherent;
-+ stream-match-mask = <0x7f00>;
-+ #global-interrupts = <2>;
-+ #iommu-cells = <1>;
-+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
- scfg: scfg@1570000 {
- compatible = "fsl,ls1043a-scfg", "syscon";
- reg = <0x0 0x1570000 0x0 0x10000>;
-@@ -255,7 +285,7 @@
-
- dcfg: dcfg@1ee0000 {
- compatible = "fsl,ls1043a-dcfg", "syscon";
-- reg = <0x0 0x1ee0000 0x0 0x10000>;
-+ reg = <0x0 0x1ee0000 0x0 0x1000>;
- big-endian;
- };
-
-@@ -342,36 +372,7 @@
- #thermal-sensor-cells = <1>;
- };
-
-- thermal-zones {
-- cpu_thermal: cpu-thermal {
-- polling-delay-passive = <1000>;
-- polling-delay = <5000>;
--
-- thermal-sensors = <&tmu 3>;
--
-- trips {
-- cpu_alert: cpu-alert {
-- temperature = <85000>;
-- hysteresis = <2000>;
-- type = "passive";
-- };
-- cpu_crit: cpu-crit {
-- temperature = <95000>;
-- hysteresis = <2000>;
-- type = "critical";
-- };
-- };
--
-- cooling-maps {
-- map0 {
-- trip = <&cpu_alert>;
-- cooling-device =
-- <&cpu0 THERMAL_NO_LIMIT
-- THERMAL_NO_LIMIT>;
-- };
-- };
-- };
-- };
-+ #include "fsl-tmu.dtsi"
-
- qman: qman@1880000 {
- compatible = "fsl,qman";
-@@ -422,7 +423,7 @@
- };
-
- i2c0: i2c@2180000 {
-- compatible = "fsl,vf610-i2c";
-+ compatible = "fsl,vf610-i2c", "fsl,ls1043a-vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2180000 0x0 0x10000>;
-@@ -432,6 +433,7 @@
- dmas = <&edma0 1 39>,
- <&edma0 1 38>;
- dma-names = "tx", "rx";
-+ scl-gpios = <&gpio4 12 0>;
- status = "disabled";
- };
-
-@@ -536,6 +538,72 @@
- #interrupt-cells = <2>;
- };
-
-+ uqe: uqe@2400000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ device_type = "qe";
-+ compatible = "fsl,qe", "simple-bus";
-+ ranges = <0x0 0x0 0x2400000 0x40000>;
-+ reg = <0x0 0x2400000 0x0 0x480>;
-+ brg-frequency = <100000000>;
-+ bus-frequency = <200000000>;
-+
-+ fsl,qe-num-riscs = <1>;
-+ fsl,qe-num-snums = <28>;
-+
-+ qeic: qeic@80 {
-+ compatible = "fsl,qe-ic";
-+ reg = <0x80 0x80>;
-+ #address-cells = <0>;
-+ interrupt-controller;
-+ #interrupt-cells = <1>;
-+ interrupts = <0 77 0x04 0 77 0x04>;
-+ };
-+
-+ si1: si@700 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "fsl,ls1043-qe-si",
-+ "fsl,t1040-qe-si";
-+ reg = <0x700 0x80>;
-+ };
-+
-+ siram1: siram@1000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "fsl,ls1043-qe-siram",
-+ "fsl,t1040-qe-siram";
-+ reg = <0x1000 0x800>;
-+ };
-+
-+ ucc@2000 {
-+ cell-index = <1>;
-+ reg = <0x2000 0x200>;
-+ interrupts = <32>;
-+ interrupt-parent = <&qeic>;
-+ };
-+
-+ ucc@2200 {
-+ cell-index = <3>;
-+ reg = <0x2200 0x200>;
-+ interrupts = <34>;
-+ interrupt-parent = <&qeic>;
-+ };
-+
-+ muram@10000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
-+ ranges = <0x0 0x10000 0x6000>;
-+
-+ data-only@0 {
-+ compatible = "fsl,qe-muram-data",
-+ "fsl,cpm-muram-data";
-+ reg = <0x0 0x6000>;
-+ };
-+ };
-+ };
-+
- lpuart0: serial@2950000 {
- compatible = "fsl,ls1021a-lpuart";
- reg = <0x0 0x2950000 0x0 0x1000>;
-@@ -590,6 +658,16 @@
- status = "disabled";
- };
-
-+ ftm0: ftm0@29d0000 {
-+ compatible = "fsl,ls1043a-ftm-alarm";
-+ reg = <0x0 0x29d0000 0x0 0x10000>,
-+ <0x0 0x1ee2140 0x0 0x4>;
-+ reg-names = "ftm", "pmctrl";
-+ interrupts = <0 86 0x4>;
-+ big-endian;
-+ status = "okay";
-+ };
-+
- wdog0: wdog@2ad0000 {
- compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
- reg = <0x0 0x2ad0000 0x0 0x10000>;
-@@ -615,41 +693,81 @@
- <&clockgen 4 0>;
- };
-
-- usb0: usb3@2f00000 {
-- compatible = "snps,dwc3";
-- reg = <0x0 0x2f00000 0x0 0x10000>;
-- interrupts = <0 60 0x4>;
-- dr_mode = "host";
-- snps,quirk-frame-length-adjustment = <0x20>;
-- snps,dis_rxdet_inp3_quirk;
-- };
--
-- usb1: usb3@3000000 {
-- compatible = "snps,dwc3";
-- reg = <0x0 0x3000000 0x0 0x10000>;
-- interrupts = <0 61 0x4>;
-- dr_mode = "host";
-- snps,quirk-frame-length-adjustment = <0x20>;
-- snps,dis_rxdet_inp3_quirk;
-- };
--
-- usb2: usb3@3100000 {
-- compatible = "snps,dwc3";
-- reg = <0x0 0x3100000 0x0 0x10000>;
-- interrupts = <0 63 0x4>;
-- dr_mode = "host";
-- snps,quirk-frame-length-adjustment = <0x20>;
-- snps,dis_rxdet_inp3_quirk;
-- };
--
-- sata: sata@3200000 {
-- compatible = "fsl,ls1043a-ahci";
-- reg = <0x0 0x3200000 0x0 0x10000>,
-- <0x0 0x20140520 0x0 0x4>;
-- reg-names = "ahci", "sata-ecc";
-- interrupts = <0 69 0x4>;
-- clocks = <&clockgen 4 0>;
-- dma-coherent;
-+ aux_bus: aux_bus {
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ compatible = "simple-bus";
-+ ranges;
-+ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
-+
-+ usb0: usb3@2f00000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x2f00000 0x0 0x10000>;
-+ interrupts = <0 60 0x4>;
-+ dr_mode = "host";
-+ snps,quirk-frame-length-adjustment = <0x20>;
-+ snps,dis_rxdet_inp3_quirk;
-+ usb3-lpm-capable;
-+ snps,dis-u1u2-when-u3-quirk;
-+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+ snps,host-vbus-glitches;
-+ };
-+
-+ usb1: usb3@3000000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x3000000 0x0 0x10000>;
-+ interrupts = <0 61 0x4>;
-+ dr_mode = "host";
-+ snps,quirk-frame-length-adjustment = <0x20>;
-+ snps,dis_rxdet_inp3_quirk;
-+ usb3-lpm-capable;
-+ snps,dis-u1u2-when-u3-quirk;
-+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+ snps,host-vbus-glitches;
-+ };
-+
-+ usb2: usb3@3100000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x3100000 0x0 0x10000>;
-+ interrupts = <0 63 0x4>;
-+ dr_mode = "host";
-+ snps,quirk-frame-length-adjustment = <0x20>;
-+ snps,dis_rxdet_inp3_quirk;
-+ usb3-lpm-capable;
-+ snps,dis-u1u2-when-u3-quirk;
-+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+ snps,host-vbus-glitches;
-+ };
-+
-+ sata: sata@3200000 {
-+ compatible = "fsl,ls1043a-ahci";
-+ reg = <0x0 0x3200000 0x0 0x10000>,
-+ <0x0 0x20140520 0x0 0x4>;
-+ reg-names = "ahci", "sata-ecc";
-+ interrupts = <0 69 0x4>;
-+ clocks = <&clockgen 4 0>;
-+ };
-+ };
-+
-+ qdma: qdma@8380000 {
-+ compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
-+ reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
-+ <0x0 0x8390000 0x0 0x10000>, /* Status regs */
-+ <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
-+ interrupts = <0 152 0x4>,
-+ <0 39 0x4>,
-+ <0 40 0x4>,
-+ <0 41 0x4>,
-+ <0 42 0x4>;
-+ interrupt-names = "qdma-error", "qdma-queue0",
-+ "qdma-queue1", "qdma-queue2", "qdma-queue3";
-+ channels = <8>;
-+ block-number = <1>;
-+ block-offset = <0x10000>;
-+ queues = <2>;
-+ status-sizes = <64>;
-+ queue-sizes = <64 64>;
-+ big-endian;
- };
-
- msi1: msi-controller1@1571000 {
-@@ -678,13 +796,13 @@
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
-- interrupts = <0 118 0x4>, /* controller interrupt */
-- <0 117 0x4>; /* PME interrupt */
-- interrupt-names = "intr", "pme";
-+ interrupts = <0 117 0x4>, /* PME interrupt */
-+ <0 118 0x4>; /* aer interrupt */
-+ interrupt-names = "pme", "aer";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
-- dma-coherent;
-+ iommu-map = <0 &smmu 0 1>;
- num-lanes = <4>;
- bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
-@@ -696,6 +814,7 @@
- <0000 0 0 2 &gic 0 111 0x4>,
- <0000 0 0 3 &gic 0 112 0x4>,
- <0000 0 0 4 &gic 0 113 0x4>;
-+ status = "disabled";
- };
-
- pcie@3500000 {
-@@ -703,13 +822,13 @@
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
-- interrupts = <0 128 0x4>,
-- <0 127 0x4>;
-- interrupt-names = "intr", "pme";
-+ interrupts = <0 127 0x4>,
-+ <0 128 0x4>;
-+ interrupt-names = "pme", "aer";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
-- dma-coherent;
-+ iommu-map = <0 &smmu 0 1>;
- num-lanes = <2>;
- bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
-@@ -721,6 +840,7 @@
- <0000 0 0 2 &gic 0 121 0x4>,
- <0000 0 0 3 &gic 0 122 0x4>,
- <0000 0 0 4 &gic 0 123 0x4>;
-+ status = "disabled";
- };
-
- pcie@3600000 {
-@@ -728,13 +848,13 @@
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
- reg-names = "regs", "config";
-- interrupts = <0 162 0x4>,
-- <0 161 0x4>;
-- interrupt-names = "intr", "pme";
-+ interrupts = <0 161 0x4>,
-+ <0 162 0x4>;
-+ interrupt-names = "pme", "aer";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
-- dma-coherent;
-+ iommu-map = <0 &smmu 0 1>;
- num-lanes = <2>;
- bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
-@@ -746,6 +866,14 @@
- <0000 0 0 2 &gic 0 155 0x4>,
- <0000 0 0 3 &gic 0 156 0x4>,
- <0000 0 0 4 &gic 0 157 0x4>;
-+ status = "disabled";
-+ };
-+ };
-+
-+ firmware {
-+ optee {
-+ compatible = "linaro,optee-tz";
-+ method = "smc";
- };
- };
-
-@@ -753,3 +881,29 @@
-
- #include "qoriq-qman-portals.dtsi"
- #include "qoriq-bman-portals.dtsi"
-+
-+&thermal_zones {
-+ thermal-zone0 {
-+ status = "okay";
-+ };
-+
-+ thermal-zone1 {
-+ status = "okay";
-+ };
-+
-+ thermal-zone2 {
-+ status = "okay";
-+ };
-+
-+ thermal-zone3 {
-+ status = "okay";
-+ };
-+
-+ thermal-zone4 {
-+ status = "okay";
-+ };
-+
-+ thermal-zone5 {
-+ status = "okay";
-+ };
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
-@@ -1,9 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
- * QorIQ FMan v3 device tree nodes for ls1046
- *
- * Copyright 2015-2016 Freescale Semiconductor Inc.
- *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- */
-
- &soc {
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
-@@ -0,0 +1,268 @@
-+/*
-+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
-+ *
-+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
-+ *
-+ * Mingkai Hu <Mingkai.hu@freescale.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPLv2 or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ * a) This library is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of the
-+ * License, or (at your option) any later version.
-+ *
-+ * This library is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ * b) Permission is hereby granted, free of charge, to any person
-+ * obtaining a copy of this software and associated documentation
-+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use,
-+ * copy, modify, merge, publish, distribute, sublicense, and/or
-+ * sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following
-+ * conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be
-+ * included in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#include "fsl-ls1046a-qds.dts"
-+#include "qoriq-qman-portals-sdk.dtsi"
-+#include "qoriq-bman-portals-sdk.dtsi"
-+
-+&bman_fbpr {
-+ compatible = "fsl,bman-fbpr";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_fqd {
-+ compatible = "fsl,qman-fqd";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_pfdr {
-+ compatible = "fsl,qman-pfdr";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+
-+&soc {
-+/delete-property/ dma-coherent;
-+
-+#include "qoriq-dpaa-eth.dtsi"
-+#include "qoriq-fman3-0-6oh.dtsi"
-+
-+pcie@3400000 {
-+ /delete-property/ iommu-map;
-+};
-+
-+pcie@3500000 {
-+ /delete-property/ iommu-map;
-+};
-+
-+pcie@3600000 {
-+ /delete-property/ iommu-map;
-+};
-+
-+/delete-node/ iommu@9000000;
-+};
-+
-+&fsldpaa {
-+ ethernet@9 {
-+ compatible = "fsl,dpa-ethernet";
-+ fsl,fman-mac = <&enet7>;
-+ dma-coherent;
-+ };
-+};
-+
-+&fman0 {
-+ compatible = "fsl,fman", "simple-bus";
-+ dma-coherent;
-+};
-+
-+&clockgen {
-+ dma-coherent;
-+};
-+
-+&scfg {
-+ dma-coherent;
-+};
-+
-+&crypto {
-+ dma-coherent;
-+};
-+
-+&dcfg {
-+ dma-coherent;
-+};
-+
-+&ifc {
-+ dma-coherent;
-+};
-+
-+&qspi {
-+ dma-coherent;
-+};
-+
-+&esdhc {
-+ dma-coherent;
-+};
-+
-+&ddr {
-+ dma-coherent;
-+};
-+
-+&tmu {
-+ dma-coherent;
-+};
-+
-+&qman {
-+ dma-coherent;
-+};
-+
-+&bman {
-+ dma-coherent;
-+};
-+
-+&bportals {
-+ dma-coherent;
-+};
-+
-+&qportals {
-+ dma-coherent;
-+};
-+
-+&dspi {
-+ dma-coherent;
-+};
-+
-+&i2c0 {
-+ dma-coherent;
-+};
-+
-+&i2c1 {
-+ dma-coherent;
-+};
-+
-+&i2c2 {
-+ dma-coherent;
-+};
-+
-+&i2c3 {
-+ dma-coherent;
-+};
-+
-+&duart0 {
-+ dma-coherent;
-+};
-+
-+&duart1 {
-+ dma-coherent;
-+};
-+
-+&duart2 {
-+ dma-coherent;
-+};
-+
-+&duart3 {
-+ dma-coherent;
-+};
-+
-+&gpio0 {
-+ dma-coherent;
-+};
-+
-+&gpio1 {
-+ dma-coherent;
-+};
-+
-+&gpio2 {
-+ dma-coherent;
-+};
-+
-+&gpio3 {
-+ dma-coherent;
-+};
-+
-+&lpuart0 {
-+ dma-coherent;
-+};
-+
-+&lpuart1 {
-+ dma-coherent;
-+};
-+
-+&lpuart2 {
-+ dma-coherent;
-+};
-+
-+&lpuart3 {
-+ dma-coherent;
-+};
-+
-+&lpuart4 {
-+ dma-coherent;
-+};
-+
-+&lpuart5 {
-+ dma-coherent;
-+};
-+
-+&ftm0 {
-+ dma-coherent;
-+};
-+
-+&wdog0 {
-+ dma-coherent;
-+};
-+
-+&edma0 {
-+ dma-coherent;
-+};
-+
-+&sata {
-+ dma-coherent;
-+};
-+
-+&qdma {
-+ dma-coherent;
-+};
-+
-+&msi1 {
-+ dma-coherent;
-+};
-+
-+&msi2 {
-+ dma-coherent;
-+};
-+
-+&msi3 {
-+ dma-coherent;
-+};
-+
-+&ptp_timer0 {
-+ dma-coherent;
-+};
-+
-+&serdes1 {
-+ dma-coherent;
-+};
-+
-+&fsldpaa {
-+ dma-coherent;
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
-@@ -1,47 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree Include file for Freescale Layerscape-1046A family SoC.
- *
- * Copyright 2016 Freescale Semiconductor, Inc.
- *
- * Shaohui Xie <Shaohui.Xie@nxp.com>
-- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- /dts-v1/;
-@@ -61,6 +24,20 @@
- serial1 = &duart1;
- serial2 = &duart2;
- serial3 = &duart3;
-+
-+ emi1_slot1 = &ls1046mdio_s1;
-+ emi1_slot2 = &ls1046mdio_s2;
-+ emi1_slot4 = &ls1046mdio_s4;
-+
-+ sgmii_s1_p1 = &sgmii_phy_s1_p1;
-+ sgmii_s1_p2 = &sgmii_phy_s1_p2;
-+ sgmii_s1_p3 = &sgmii_phy_s1_p3;
-+ sgmii_s1_p4 = &sgmii_phy_s1_p4;
-+ sgmii_s4_p1 = &sgmii_phy_s4_p1;
-+ qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
-+ qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
-+ qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
-+ qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
- };
-
- chosen {
-@@ -188,8 +165,9 @@
- };
-
- fpga: board-control@2,0 {
-- compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";
-+ compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus";
- reg = <0x2 0x0 0x0000100>;
-+ ranges = <0 2 0 0x100>;
- };
- };
-
-@@ -206,9 +184,145 @@
- compatible = "spansion,m25p80";
- #address-cells = <1>;
- #size-cells = <1>;
-- spi-max-frequency = <20000000>;
-+ spi-max-frequency = <50000000>;
- reg = <0>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <4>;
- };
- };
-
- #include "fsl-ls1046-post.dtsi"
-+
-+&fman0 {
-+ ethernet@e0000 {
-+ phy-handle = <&qsgmii_phy_s2_p1>;
-+ phy-connection-type = "sgmii";
-+ };
-+
-+ ethernet@e2000 {
-+ phy-handle = <&sgmii_phy_s4_p1>;
-+ phy-connection-type = "sgmii";
-+ };
-+
-+ ethernet@e4000 {
-+ phy-handle = <&rgmii_phy1>;
-+ phy-connection-type = "rgmii";
-+ };
-+
-+ ethernet@e6000 {
-+ phy-handle = <&rgmii_phy2>;
-+ phy-connection-type = "rgmii";
-+ };
-+
-+ ethernet@e8000 {
-+ phy-handle = <&sgmii_phy_s1_p3>;
-+ phy-connection-type = "sgmii";
-+ };
-+
-+ ethernet@ea000 {
-+ phy-handle = <&sgmii_phy_s1_p4>;
-+ phy-connection-type = "sgmii";
-+ };
-+
-+ ethernet@f0000 { /* DTSEC9/10GEC1 */
-+ phy-handle = <&sgmii_phy_s1_p1>;
-+ phy-connection-type = "xgmii";
-+ };
-+
-+ ethernet@f2000 { /* DTSEC10/10GEC2 */
-+ phy-handle = <&sgmii_phy_s1_p2>;
-+ phy-connection-type = "xgmii";
-+ };
-+};
-+
-+&fpga {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ mdio-mux-emi1 {
-+ compatible = "mdio-mux-mmioreg", "mdio-mux";
-+ mdio-parent-bus = <&mdio0>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x54 1>; /* BRDCFG4 */
-+ mux-mask = <0xe0>; /* EMI1 */
-+
-+ /* On-board RGMII1 PHY */
-+ ls1046mdio0: mdio@0 {
-+ reg = <0>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ rgmii_phy1: ethernet-phy@1 { /* MAC3 */
-+ reg = <0x1>;
-+ };
-+ };
-+
-+ /* On-board RGMII2 PHY */
-+ ls1046mdio1: mdio@1 {
-+ reg = <0x20>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ rgmii_phy2: ethernet-phy@2 { /* MAC4 */
-+ reg = <0x2>;
-+ };
-+ };
-+
-+ /* Slot 1 */
-+ ls1046mdio_s1: mdio@2 {
-+ reg = <0x40>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+
-+ sgmii_phy_s1_p1: ethernet-phy@1c {
-+ reg = <0x1c>;
-+ };
-+
-+ sgmii_phy_s1_p2: ethernet-phy@1d {
-+ reg = <0x1d>;
-+ };
-+
-+ sgmii_phy_s1_p3: ethernet-phy@1e {
-+ reg = <0x1e>;
-+ };
-+
-+ sgmii_phy_s1_p4: ethernet-phy@1f {
-+ reg = <0x1f>;
-+ };
-+ };
-+
-+ /* Slot 2 */
-+ ls1046mdio_s2: mdio@3 {
-+ reg = <0x60>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+
-+ qsgmii_phy_s2_p1: ethernet-phy@8 {
-+ reg = <0x8>;
-+ };
-+ qsgmii_phy_s2_p2: ethernet-phy@9 {
-+ reg = <0x9>;
-+ };
-+ qsgmii_phy_s2_p3: ethernet-phy@a {
-+ reg = <0xa>;
-+ };
-+ qsgmii_phy_s2_p4: ethernet-phy@b {
-+ reg = <0xb>;
-+ };
-+ };
-+
-+ /* Slot 4 */
-+ ls1046mdio_s4: mdio@5 {
-+ reg = <0x80>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+
-+ sgmii_phy_s4_p1: ethernet-phy@1c {
-+ reg = <0x1c>;
-+ };
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
-@@ -0,0 +1,307 @@
-+/*
-+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
-+ *
-+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
-+ *
-+ * Mingkai Hu <Mingkai.hu@freescale.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPLv2 or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ * a) This library is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of the
-+ * License, or (at your option) any later version.
-+ *
-+ * This library is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ * b) Permission is hereby granted, free of charge, to any person
-+ * obtaining a copy of this software and associated documentation
-+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use,
-+ * copy, modify, merge, publish, distribute, sublicense, and/or
-+ * sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following
-+ * conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be
-+ * included in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#include "fsl-ls1046a-rdb.dts"
-+#include "qoriq-qman-portals-sdk.dtsi"
-+#include "qoriq-bman-portals-sdk.dtsi"
-+
-+&bman_fbpr {
-+ compatible = "fsl,bman-fbpr";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_fqd {
-+ compatible = "fsl,qman-fqd";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_pfdr {
-+ compatible = "fsl,qman-pfdr";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+
-+&soc {
-+/delete-property/ dma-coherent;
-+
-+#include "qoriq-dpaa-eth.dtsi"
-+#include "qoriq-fman3-0-6oh.dtsi"
-+
-+pcie@3400000 {
-+ /delete-property/ iommu-map;
-+};
-+
-+pcie@3500000 {
-+ /delete-property/ iommu-map;
-+};
-+
-+pcie@3600000 {
-+ /delete-property/ iommu-map;
-+};
-+
-+/delete-node/ iommu@9000000;
-+};
-+
-+&fsldpaa {
-+ ethernet@0 {
-+ status = "disabled";
-+ };
-+ ethernet@1 {
-+ status = "disabled";
-+ };
-+ ethernet@9 {
-+ compatible = "fsl,dpa-ethernet";
-+ fsl,fman-mac = <&enet7>;
-+ dma-coherent;
-+ };
-+};
-+
-+&fman0 {
-+ compatible = "fsl,fman", "simple-bus";
-+};
-+
-+&mdio9 {
-+ pcsphy6: ethernet-phy@0 {
-+ backplane-mode = "10gbase-kr";
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ reg = <0x0>;
-+ fsl,lane-handle = <&serdes1>;
-+ fsl,lane-reg = <0x8C0 0x40>; /* lane D */
-+ };
-+};
-+
-+&mdio10 {
-+ pcsphy7: ethernet-phy@0 {
-+ backplane-mode = "10gbase-kr";
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ reg = <0x0>;
-+ fsl,lane-handle = <&serdes1>;
-+ fsl,lane-reg = <0x880 0x40>; /* lane C */
-+ };
-+};
-+
-+/* Update MAC connections to backplane PHYs
-+ * &mac9 {
-+ * phy-handle = <&pcsphy6>;
-+ *};
-+ *
-+ *&mac10 {
-+ * phy-handle = <&pcsphy7>;
-+ *};
-+*/
-+
-+&clockgen {
-+ dma-coherent;
-+};
-+
-+&scfg {
-+ dma-coherent;
-+};
-+
-+&crypto {
-+ dma-coherent;
-+};
-+
-+&dcfg {
-+ dma-coherent;
-+};
-+
-+&ifc {
-+ dma-coherent;
-+};
-+
-+&qspi {
-+ dma-coherent;
-+};
-+
-+&esdhc {
-+ dma-coherent;
-+};
-+
-+&ddr {
-+ dma-coherent;
-+};
-+
-+&tmu {
-+ dma-coherent;
-+};
-+
-+&qman {
-+ dma-coherent;
-+};
-+
-+&bman {
-+ dma-coherent;
-+};
-+
-+&bportals {
-+ dma-coherent;
-+};
-+
-+&qportals {
-+ dma-coherent;
-+};
-+
-+&dspi {
-+ dma-coherent;
-+};
-+
-+&i2c0 {
-+ dma-coherent;
-+};
-+
-+&i2c1 {
-+ dma-coherent;
-+};
-+
-+&i2c2 {
-+ dma-coherent;
-+};
-+
-+&i2c3 {
-+ dma-coherent;
-+};
-+
-+&duart0 {
-+ dma-coherent;
-+};
-+
-+&duart1 {
-+ dma-coherent;
-+};
-+
-+&duart2 {
-+ dma-coherent;
-+};
-+
-+&duart3 {
-+ dma-coherent;
-+};
-+
-+&gpio0 {
-+ dma-coherent;
-+};
-+
-+&gpio1 {
-+ dma-coherent;
-+};
-+
-+&gpio2 {
-+ dma-coherent;
-+};
-+
-+&gpio3 {
-+ dma-coherent;
-+};
-+
-+&lpuart0 {
-+ dma-coherent;
-+};
-+
-+&lpuart1 {
-+ dma-coherent;
-+};
-+
-+&lpuart2 {
-+ dma-coherent;
-+};
-+
-+&lpuart3 {
-+ dma-coherent;
-+};
-+
-+&lpuart4 {
-+ dma-coherent;
-+};
-+
-+&lpuart5 {
-+ dma-coherent;
-+};
-+
-+&ftm0 {
-+ dma-coherent;
-+};
-+
-+&wdog0 {
-+ dma-coherent;
-+};
-+
-+&edma0 {
-+ dma-coherent;
-+};
-+
-+&sata {
-+ dma-coherent;
-+};
-+
-+&qdma {
-+ dma-coherent;
-+};
-+
-+&msi1 {
-+ dma-coherent;
-+};
-+
-+&msi2 {
-+ dma-coherent;
-+};
-+
-+&msi3 {
-+ dma-coherent;
-+};
-+
-+&fman0 {
-+ dma-coherent;
-+};
-+
-+&ptp_timer0 {
-+ dma-coherent;
-+};
-+
-+&serdes1 {
-+ dma-coherent;
-+};
-+
-+&fsldpaa {
-+ dma-coherent;
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
-@@ -0,0 +1,133 @@
-+/*
-+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
-+ *
-+ * Copyright (C) 2016, Freescale Semiconductor
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#include "fsl-ls1046a-rdb-sdk.dts"
-+
-+&soc {
-+ bp7: buffer-pool@7 {
-+ compatible = "fsl,ls1046a-bpool", "fsl,bpool";
-+ fsl,bpid = <7>;
-+ fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
-+ fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
-+ dma-coherent;
-+ };
-+
-+ bp8: buffer-pool@8 {
-+ compatible = "fsl,ls1046a-bpool", "fsl,bpool";
-+ fsl,bpid = <8>;
-+ fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
-+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
-+ dma-coherent;
-+ };
-+
-+ bp9: buffer-pool@9 {
-+ compatible = "fsl,ls1046a-bpool", "fsl,bpool";
-+ fsl,bpid = <9>;
-+ fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
-+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
-+ dma-coherent;
-+ };
-+
-+ fsl,dpaa {
-+ compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
-+ dma-coherent;
-+
-+ ethernet@2 {
-+ compatible = "fsl,dpa-ethernet-init";
-+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+ fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
-+ fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
-+ };
-+
-+ ethernet@3 {
-+ compatible = "fsl,dpa-ethernet-init";
-+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+ fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
-+ fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
-+ };
-+
-+ ethernet@4 {
-+ compatible = "fsl,dpa-ethernet-init";
-+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+ fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
-+ fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
-+ };
-+
-+ ethernet@5 {
-+ compatible = "fsl,dpa-ethernet-init";
-+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+ fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
-+ fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
-+ };
-+
-+ ethernet@8 {
-+ compatible = "fsl,dpa-ethernet-init";
-+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+ fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
-+ fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
-+ };
-+
-+ ethernet@9 {
-+ compatible = "fsl,dpa-ethernet-init";
-+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+ fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
-+ fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
-+ };
-+
-+ dpa-fman0-oh@2 {
-+ compatible = "fsl,dpa-oh";
-+ /* Define frame queues for the OH port*/
-+ /* <OH Rx error, OH Rx default> */
-+ fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
-+ fsl,fman-oh-port = <&fman0_oh2>;
-+ };
-+ };
-+
-+ pcie@3400000 {
-+ /delete-property/ iommu-map;
-+ };
-+
-+ pcie@3500000 {
-+ /delete-property/ iommu-map;
-+ };
-+
-+ pcie@3600000 {
-+ /delete-property/ iommu-map;
-+ };
-+
-+ /delete-node/ iommu@9000000;
-+};
-+/ {
-+ reserved-memory {
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ /* For legacy usdpaa based use-cases, update the size and
-+ alignment parameters. e.g. to allocate 256 MB memory:
-+ size = <0 0x10000000>;
-+ alignment = <0 0x10000000>;
-+ */
-+ usdpaa_mem: usdpaa_mem {
-+ compatible = "fsl,usdpaa-mem";
-+ alloc-ranges = <0 0 0x10000 0>;
-+ size = <0 0x1000>;
-+ alignment = <0 0x1000>;
-+ };
-+ };
-+};
-+
-+&fman0 {
-+ fman0_oh2: port@83000 {
-+ cell-index = <1>;
-+ compatible = "fsl,fman-port-oh";
-+ reg = <0x83000 0x1000>;
-+ };
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
-@@ -1,47 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree Include file for Freescale Layerscape-1046A family SoC.
- *
- * Copyright 2016 Freescale Semiconductor, Inc.
- *
- * Mingkai Hu <mingkai.hu@nxp.com>
-- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- /dts-v1/;
-@@ -139,21 +102,26 @@
- num-cs = <2>;
- bus-num = <0>;
- status = "okay";
-+ fsl,qspi-has-second-chip;
-
- qflash0: s25fs512s@0 {
- compatible = "spansion,m25p80";
- #address-cells = <1>;
- #size-cells = <1>;
-- spi-max-frequency = <20000000>;
-+ spi-max-frequency = <50000000>;
- reg = <0>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <4>;
- };
-
- qflash1: s25fs512s@1 {
- compatible = "spansion,m25p80";
- #address-cells = <1>;
- #size-cells = <1>;
-- spi-max-frequency = <20000000>;
-+ spi-max-frequency = <50000000>;
- reg = <1>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <4>;
- };
- };
-
---- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
-@@ -1,47 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree Include file for Freescale Layerscape-1046A family SoC.
- *
- * Copyright 2016 Freescale Semiconductor, Inc.
- *
- * Mingkai Hu <mingkai.hu@nxp.com>
-- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- #include <dt-bindings/interrupt-controller/arm-gic.h>
-@@ -70,7 +33,7 @@
- #address-cells = <1>;
- #size-cells = <0>;
-
-- cpu0: cpu@0 {
-+ cooling_map0: cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a72";
- reg = <0x0>;
-@@ -122,7 +85,7 @@
- CPU_PH20: cpu-ph20 {
- compatible = "arm,idle-state";
- idle-state-name = "PH20";
-- arm,psci-suspend-param = <0x00010000>;
-+ arm,psci-suspend-param = <0x0>;
- entry-latency-us = <1000>;
- exit-latency-us = <1000>;
- min-residency-us = <3000>;
-@@ -188,6 +151,8 @@
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
-+ dma-coherent;
-
- ddr: memory-controller@1080000 {
- compatible = "fsl,qoriq-memory-controller";
-@@ -214,7 +179,6 @@
- clock-names = "qspi_en", "qspi";
- clocks = <&clockgen 4 1>, <&clockgen 4 1>;
- big-endian;
-- fsl,qspi-has-second-chip;
- status = "disabled";
- };
-
-@@ -229,6 +193,49 @@
- bus-width = <4>;
- };
-
-+ smmu: iommu@9000000 {
-+ compatible = "arm,mmu-500";
-+ reg = <0 0x9000000 0 0x400000>;
-+ dma-coherent;
-+ stream-match-mask = <0x7f00>;
-+ #global-interrupts = <2>;
-+ #iommu-cells = <1>;
-+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
- scfg: scfg@1570000 {
- compatible = "fsl,ls1046a-scfg", "syscon";
- reg = <0x0 0x1570000 0x0 0x10000>;
-@@ -304,7 +311,7 @@
-
- dcfg: dcfg@1ee0000 {
- compatible = "fsl,ls1046a-dcfg", "syscon";
-- reg = <0x0 0x1ee0000 0x0 0x10000>;
-+ reg = <0x0 0x1ee0000 0x0 0x1000>;
- big-endian;
- };
-
-@@ -362,36 +369,7 @@
- #thermal-sensor-cells = <1>;
- };
-
-- thermal-zones {
-- cpu_thermal: cpu-thermal {
-- polling-delay-passive = <1000>;
-- polling-delay = <5000>;
-- thermal-sensors = <&tmu 3>;
--
-- trips {
-- cpu_alert: cpu-alert {
-- temperature = <85000>;
-- hysteresis = <2000>;
-- type = "passive";
-- };
--
-- cpu_crit: cpu-crit {
-- temperature = <95000>;
-- hysteresis = <2000>;
-- type = "critical";
-- };
-- };
--
-- cooling-maps {
-- map0 {
-- trip = <&cpu_alert>;
-- cooling-device =
-- <&cpu0 THERMAL_NO_LIMIT
-- THERMAL_NO_LIMIT>;
-- };
-- };
-- };
-- };
-+ #include "fsl-tmu.dtsi"
-
- dspi: dspi@2100000 {
- compatible = "fsl,ls1021a-v1.0-dspi";
-@@ -407,7 +385,7 @@
- };
-
- i2c0: i2c@2180000 {
-- compatible = "fsl,vf610-i2c";
-+ compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2180000 0x0 0x10000>;
-@@ -416,6 +394,7 @@
- dmas = <&edma0 1 39>,
- <&edma0 1 38>;
- dma-names = "tx", "rx";
-+ scl-gpios = <&gpio3 12 0>;
- status = "disabled";
- };
-
-@@ -440,12 +419,13 @@
- };
-
- i2c3: i2c@21b0000 {
-- compatible = "fsl,vf610-i2c";
-+ compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x21b0000 0x0 0x10000>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
-+ scl-gpios = <&gpio3 12 0>;
- status = "disabled";
- };
-
-@@ -571,6 +551,15 @@
- status = "disabled";
- };
-
-+ ftm0: ftm0@29d0000 {
-+ compatible = "fsl,ls1046a-ftm-alarm";
-+ reg = <0x0 0x29d0000 0x0 0x10000>,
-+ <0x0 0x1ee2140 0x0 0x4>;
-+ reg-names = "ftm", "pmctrl";
-+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-+ big-endian;
-+ };
-+
- wdog0: watchdog@2ad0000 {
- compatible = "fsl,imx21-wdt";
- reg = <0x0 0x2ad0000 0x0 0x10000>;
-@@ -595,40 +584,81 @@
- <&clockgen 4 1>;
- };
-
-- usb0: usb@2f00000 {
-- compatible = "snps,dwc3";
-- reg = <0x0 0x2f00000 0x0 0x10000>;
-- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-- dr_mode = "host";
-- snps,quirk-frame-length-adjustment = <0x20>;
-- snps,dis_rxdet_inp3_quirk;
-- };
--
-- usb1: usb@3000000 {
-- compatible = "snps,dwc3";
-- reg = <0x0 0x3000000 0x0 0x10000>;
-- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-- dr_mode = "host";
-- snps,quirk-frame-length-adjustment = <0x20>;
-- snps,dis_rxdet_inp3_quirk;
-- };
--
-- usb2: usb@3100000 {
-- compatible = "snps,dwc3";
-- reg = <0x0 0x3100000 0x0 0x10000>;
-- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-- dr_mode = "host";
-- snps,quirk-frame-length-adjustment = <0x20>;
-- snps,dis_rxdet_inp3_quirk;
-- };
--
-- sata: sata@3200000 {
-- compatible = "fsl,ls1046a-ahci";
-- reg = <0x0 0x3200000 0x0 0x10000>,
-- <0x0 0x20140520 0x0 0x4>;
-- reg-names = "ahci", "sata-ecc";
-- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&clockgen 4 1>;
-+ aux_bus: aux_bus {
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ compatible = "simple-bus";
-+ ranges;
-+ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
-+
-+ usb0: usb@2f00000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x2f00000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-+ dr_mode = "host";
-+ snps,quirk-frame-length-adjustment = <0x20>;
-+ snps,dis_rxdet_inp3_quirk;
-+ usb3-lpm-capable;
-+ snps,dis-u1u2-when-u3-quirk;
-+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+ snps,host-vbus-glitches;
-+ };
-+
-+ usb1: usb@3000000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x3000000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-+ dr_mode = "host";
-+ snps,quirk-frame-length-adjustment = <0x20>;
-+ snps,dis_rxdet_inp3_quirk;
-+ usb3-lpm-capable;
-+ snps,dis-u1u2-when-u3-quirk;
-+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+ snps,host-vbus-glitches;
-+ };
-+
-+ usb2: usb@3100000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x3100000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-+ dr_mode = "host";
-+ snps,quirk-frame-length-adjustment = <0x20>;
-+ snps,dis_rxdet_inp3_quirk;
-+ usb3-lpm-capable;
-+ snps,dis-u1u2-when-u3-quirk;
-+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+ snps,host-vbus-glitches;
-+ };
-+
-+ sata: sata@3200000 {
-+ compatible = "fsl,ls1046a-ahci";
-+ reg = <0x0 0x3200000 0x0 0x10000>,
-+ <0x0 0x20140520 0x0 0x4>;
-+ reg-names = "ahci", "sata-ecc";
-+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 1>;
-+ };
-+ };
-+
-+ qdma: qdma@8380000 {
-+ compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
-+ reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
-+ <0x0 0x8390000 0x0 0x10000>, /* Status regs */
-+ <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
-+ interrupts = <0 153 0x4>,
-+ <0 39 0x4>,
-+ <0 40 0x4>,
-+ <0 41 0x4>,
-+ <0 42 0x4>;
-+ interrupt-names = "qdma-error", "qdma-queue0",
-+ "qdma-queue1", "qdma-queue2", "qdma-queue3";
-+ channels = <8>;
-+ block-number = <1>;
-+ block-offset = <0x10000>;
-+ queues = <2>;
-+ status-sizes = <64>;
-+ queue-sizes = <64 64>;
-+ big-endian;
- };
-
- msi1: msi-controller@1580000 {
-@@ -661,6 +691,125 @@
- <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- };
-
-+ pcie@3400000 {
-+ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
-+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
-+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
-+ reg-names = "regs", "config";
-+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
-+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
-+ interrupt-names = "pme", "aer";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ dma-coherent;
-+ iommu-map = <0 &smmu 0 1>;
-+ num-lanes = <4>;
-+ bus-range = <0x0 0xff>;
-+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
-+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+ msi-parent = <&msi1>, <&msi2>, <&msi3>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ pcie_ep@3400000 {
-+ compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
-+ reg = <0x00 0x03400000 0x0 0x00100000
-+ 0x40 0x00000000 0x8 0x00000000>;
-+ reg-names = "regs", "addr_space";
-+ num-ib-windows = <6>;
-+ num-ob-windows = <8>;
-+ num-lanes = <2>;
-+ status = "disabled";
-+ };
-+
-+ pcie@3500000 {
-+ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
-+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
-+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
-+ reg-names = "regs", "config";
-+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "pme", "aer";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ dma-coherent;
-+ iommu-map = <0 &smmu 0 1>;
-+ num-lanes = <2>;
-+ bus-range = <0x0 0xff>;
-+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
-+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+ msi-parent = <&msi1>, <&msi2>, <&msi3>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ pcie_ep@3500000 {
-+ compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
-+ reg = <0x00 0x03500000 0x0 0x00100000
-+ 0x48 0x00000000 0x8 0x00000000>;
-+ reg-names = "regs", "addr_space";
-+ num-ib-windows = <6>;
-+ num-ob-windows = <8>;
-+ num-lanes = <2>;
-+ status = "disabled";
-+ };
-+
-+ pcie@3600000 {
-+ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
-+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
-+ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
-+ reg-names = "regs", "config";
-+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "pme", "aer";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ dma-coherent;
-+ iommu-map = <0 &smmu 0 1>;
-+ num-lanes = <2>;
-+ bus-range = <0x0 0xff>;
-+ ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
-+ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+ msi-parent = <&msi1>, <&msi2>, <&msi3>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ pcie_ep@3600000 {
-+ compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
-+ reg = <0x00 0x03600000 0x0 0x00100000
-+ 0x50 0x00000000 0x8 0x00000000>;
-+ reg-names = "regs", "addr_space";
-+ num-ib-windows = <6>;
-+ num-ob-windows = <8>;
-+ num-lanes = <2>;
-+ status = "disabled";
-+ };
-+
-+ serdes1: serdes@1ea0000 {
-+ reg = <0x0 0x1ea0000 0 0x00002000>;
-+ compatible = "fsl,serdes-10g";
-+ };
-+
- };
-
- reserved-memory {
-@@ -689,7 +838,36 @@
- no-map;
- };
- };
-+
-+ firmware {
-+ optee {
-+ compatible = "linaro,optee-tz";
-+ method = "smc";
-+ };
-+ };
- };
-
- #include "qoriq-qman-portals.dtsi"
- #include "qoriq-bman-portals.dtsi"
-+
-+&thermal_zones {
-+ thermal-zone0 {
-+ status = "okay";
-+ };
-+
-+ thermal-zone1 {
-+ status = "okay";
-+ };
-+
-+ thermal-zone2 {
-+ status = "okay";
-+ };
-+
-+ thermal-zone3 {
-+ status = "okay";
-+ };
-+
-+ thermal-zone4 {
-+ status = "okay";
-+ };
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree file for NXP LS1088A QDS Board.
- *
-@@ -5,43 +6,6 @@
- *
- * Harninder Rai <harninder.rai@nxp.com>
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- /dts-v1/;
-@@ -134,6 +98,30 @@
- };
- };
-
-+&qspi {
-+ status = "okay";
-+ fsl,qspi-has-second-chip;
-+ qflash0: s25fs512s@0 {
-+ compatible = "spansion,m25p80";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ spi-max-frequency = <20000000>;
-+ reg = <0>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <4>;
-+ };
-+
-+ qflash1: s25fs512s@1 {
-+ compatible = "spansion,m25p80";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ spi-max-frequency = <20000000>;
-+ reg = <1>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <4>;
-+ };
-+};
-+
- &duart0 {
- status = "okay";
- };
-@@ -149,3 +137,29 @@
- &sata {
- status = "okay";
- };
-+
-+&pcs_mdio1 {
-+ pcs_phy1: ethernet-phy@0 {
-+ backplane-mode = "10gbase-kr";
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ reg = <0x0>;
-+ fsl,lane-handle = <&serdes1>;
-+ fsl,lane-reg = <0x840 0x40>;/* lane B */
-+ };
-+};
-+
-+&pcs_mdio2 {
-+ pcs_phy2: ethernet-phy@0 {
-+ backplane-mode = "10gbase-kr";
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ reg = <0x0>;
-+ fsl,lane-handle = <&serdes1>;
-+ fsl,lane-reg = <0x800 0x40>;/* lane A */
-+ };
-+};
-+
-+/* Update DPMAC connections to backplane PHYs, under SerDes 0x1D_0xXX.
-+ * &dpmac1 {
-+ * phy-handle = <&pcs_phy1>;
-+ * };
-+ */
---- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree file for NXP LS1088A RDB Board.
- *
-@@ -5,43 +6,6 @@
- *
- * Harninder Rai <harninder.rai@nxp.com>
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- /dts-v1/;
-@@ -110,6 +74,31 @@
- };
- };
-
-+&qspi {
-+ status = "okay";
-+ fsl,qspi-has-second-chip;
-+ qflash0: s25fs512s@0 {
-+ compatible = "spansion,m25p80";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ spi-max-frequency = <20000000>;
-+ reg = <0>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <4>;
-+ };
-+
-+ qflash1: s25fs512s@1 {
-+ compatible = "spansion,m25p80";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ spi-max-frequency = <20000000>;
-+ reg = <1>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <4>;
-+ };
-+
-+};
-+
- &duart0 {
- status = "okay";
- };
-@@ -118,6 +107,14 @@
- status = "okay";
- };
-
-+&usb0 {
-+ status = "okay";
-+};
-+
-+&usb1 {
-+ status = "okay";
-+};
-+
- &esdhc {
- status = "okay";
- };
-@@ -125,3 +122,82 @@
- &sata {
- status = "okay";
- };
-+
-+&emdio1 {
-+ /* Freescale F104 PHY1 */
-+ mdio1_phy1: emdio1_phy@1 {
-+ reg = <0x1c>;
-+ phy-connection-type = "qsgmii";
-+ };
-+ mdio1_phy2: emdio1_phy@2 {
-+ reg = <0x1d>;
-+ phy-connection-type = "qsgmii";
-+ };
-+ mdio1_phy3: emdio1_phy@3 {
-+ reg = <0x1e>;
-+ phy-connection-type = "qsgmii";
-+ };
-+ mdio1_phy4: emdio1_phy@4 {
-+ reg = <0x1f>;
-+ phy-connection-type = "qsgmii";
-+ };
-+ /* F104 PHY2 */
-+ mdio1_phy5: emdio1_phy@5 {
-+ reg = <0x0c>;
-+ phy-connection-type = "qsgmii";
-+ };
-+ mdio1_phy6: emdio1_phy@6 {
-+ reg = <0x0d>;
-+ phy-connection-type = "qsgmii";
-+ };
-+ mdio1_phy7: emdio1_phy@7 {
-+ reg = <0x0e>;
-+ phy-connection-type = "qsgmii";
-+ };
-+ mdio1_phy8: emdio1_phy@8 {
-+ reg = <0x0f>;
-+ phy-connection-type = "qsgmii";
-+ };
-+};
-+
-+&emdio2 {
-+ /* Aquantia AQR105 10G PHY */
-+ mdio2_phy1: emdio2_phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ interrupts = <0 2 0x4>;
-+ reg = <0x0>;
-+ phy-connection-type = "xfi";
-+ };
-+};
-+
-+/* DPMAC connections to external PHYs
-+ * based on LS1088A RM RevC - $24.1.2 SerDes Options
-+ */
-+/* DPMAC1 is 10G SFP+, fixed link */
-+&dpmac2 {
-+ phy-handle = <&mdio2_phy1>;
-+};
-+&dpmac3 {
-+ phy-handle = <&mdio1_phy5>;
-+};
-+&dpmac4 {
-+ phy-handle = <&mdio1_phy6>;
-+};
-+&dpmac5 {
-+ phy-handle = <&mdio1_phy7>;
-+};
-+&dpmac6 {
-+ phy-handle = <&mdio1_phy8>;
-+};
-+&dpmac7 {
-+ phy-handle = <&mdio1_phy1>;
-+};
-+&dpmac8 {
-+ phy-handle = <&mdio1_phy2>;
-+};
-+&dpmac9 {
-+ phy-handle = <&mdio1_phy3>;
-+};
-+&dpmac10 {
-+ phy-handle = <&mdio1_phy4>;
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree Include file for NXP Layerscape-1088A family SoC.
- *
-@@ -5,43 +6,6 @@
- *
- * Harninder Rai <harninder.rai@nxp.com>
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/thermal/thermal.h>
-@@ -61,7 +25,7 @@
- #size-cells = <0>;
-
- /* We have 2 clusters having 4 Cortex-A53 cores each */
-- cpu0: cpu@0 {
-+ cooling_map0: cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0>;
-@@ -94,7 +58,7 @@
- cpu-idle-states = <&CPU_PH20>;
- };
-
-- cpu4: cpu@100 {
-+ cooling_map1: cpu4: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x100>;
-@@ -130,7 +94,7 @@
- CPU_PH20: cpu-ph20 {
- compatible = "arm,idle-state";
- idle-state-name = "PH20";
-- arm,psci-suspend-param = <0x00010000>;
-+ arm,psci-suspend-param = <0x0>;
- entry-latency-us = <1000>;
- exit-latency-us = <1000>;
- min-residency-us = <3000>;
-@@ -147,6 +111,15 @@
- <0x0 0x0c0d0000 0 0x1000>, /* GICH */
- <0x0 0x0c0e0000 0 0x20000>; /* GICV */
- interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ its: gic-its@6020000 {
-+ compatible = "arm,gic-v3-its";
-+ msi-controller;
-+ reg = <0x0 0x6020000 0 0x20000>;
-+ };
- };
-
- timer {
-@@ -169,11 +142,31 @@
- clock-output-names = "sysclk";
- };
-
-+ dcfg: dcfg@1e00000 {
-+ compatible = "fsl,ls1088a-dcfg", "syscon";
-+ reg = <0x0 0x1e00000 0x0 0x10000>;
-+ little-endian;
-+ };
-+
-+ rstcr: syscon@1e60000 {
-+ compatible = "fsl,ls1088a-rstcr", "syscon";
-+ reg = <0x0 0x1e60000 0x0 0x4>;
-+ };
-+
-+ reboot {
-+ compatible = "syscon-reboot";
-+ regmap = <&rstcr>;
-+ offset = <0x0>;
-+ mask = <0x02>;
-+ };
-+
-+
- soc {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
-
- clockgen: clocking@1300000 {
- compatible = "fsl,ls1088a-clockgen";
-@@ -229,43 +222,7 @@
- #thermal-sensor-cells = <1>;
- };
-
-- thermal-zones {
-- cpu_thermal: cpu-thermal {
-- polling-delay-passive = <1000>;
-- polling-delay = <5000>;
-- thermal-sensors = <&tmu 0>;
--
-- trips {
-- cpu_alert: cpu-alert {
-- temperature = <85000>;
-- hysteresis = <2000>;
-- type = "passive";
-- };
--
-- cpu_crit: cpu-crit {
-- temperature = <95000>;
-- hysteresis = <2000>;
-- type = "critical";
-- };
-- };
--
-- cooling-maps {
-- map0 {
-- trip = <&cpu_alert>;
-- cooling-device =
-- <&cpu0 THERMAL_NO_LIMIT
-- THERMAL_NO_LIMIT>;
-- };
--
-- map1 {
-- trip = <&cpu_alert>;
-- cooling-device =
-- <&cpu4 THERMAL_NO_LIMIT
-- THERMAL_NO_LIMIT>;
-- };
-- };
-- };
-- };
-+ #include "fsl-tmu.dtsi"
-
- duart0: serial@21c0500 {
- compatible = "fsl,ns16550", "ns16550a";
-@@ -283,6 +240,62 @@
- status = "disabled";
- };
-
-+ cluster1_core0_watchdog: wdt@c000000 {
-+ compatible = "arm,sp805-wdt", "arm,primecell";
-+ reg = <0x0 0xc000000 0x0 0x1000>;
-+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+ clock-names = "apb_pclk", "wdog_clk";
-+ };
-+
-+ cluster1_core1_watchdog: wdt@c010000 {
-+ compatible = "arm,sp805-wdt", "arm,primecell";
-+ reg = <0x0 0xc010000 0x0 0x1000>;
-+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+ clock-names = "apb_pclk", "wdog_clk";
-+ };
-+
-+ cluster1_core2_watchdog: wdt@c020000 {
-+ compatible = "arm,sp805-wdt", "arm,primecell";
-+ reg = <0x0 0xc020000 0x0 0x1000>;
-+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+ clock-names = "apb_pclk", "wdog_clk";
-+ };
-+
-+ cluster1_core3_watchdog: wdt@c030000 {
-+ compatible = "arm,sp805-wdt", "arm,primecell";
-+ reg = <0x0 0xc030000 0x0 0x1000>;
-+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+ clock-names = "apb_pclk", "wdog_clk";
-+ };
-+
-+ cluster2_core0_watchdog: wdt@c100000 {
-+ compatible = "arm,sp805-wdt", "arm,primecell";
-+ reg = <0x0 0xc100000 0x0 0x1000>;
-+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+ clock-names = "apb_pclk", "wdog_clk";
-+ };
-+
-+ cluster2_core1_watchdog: wdt@c110000 {
-+ compatible = "arm,sp805-wdt", "arm,primecell";
-+ reg = <0x0 0xc110000 0x0 0x1000>;
-+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+ clock-names = "apb_pclk", "wdog_clk";
-+ };
-+
-+ cluster2_core2_watchdog: wdt@c120000 {
-+ compatible = "arm,sp805-wdt", "arm,primecell";
-+ reg = <0x0 0xc120000 0x0 0x1000>;
-+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+ clock-names = "apb_pclk", "wdog_clk";
-+ };
-+
-+ cluster2_core3_watchdog: wdt@c130000 {
-+ compatible = "arm,sp805-wdt", "arm,primecell";
-+ reg = <0x0 0xc130000 0x0 0x1000>;
-+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+ clock-names = "apb_pclk", "wdog_clk";
-+ };
-+
- gpio0: gpio@2300000 {
- compatible = "fsl,qoriq-gpio";
- reg = <0x0 0x2300000 0x0 0x10000>;
-@@ -323,6 +336,72 @@
- #interrupt-cells = <2>;
- };
-
-+ /* TODO: WRIOP (CCSR?) */
-+ emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
-+ * E-MDIO1: 0x1_6000
-+ */
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8B96000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian; /* force the driver in LE mode */
-+
-+ /* Not necessary on the QDS, but needed on the RDB */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
-+ * E-MDIO2: 0x1_7000
-+ */
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8B97000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian; /* force the driver in LE mode */
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio1: mdio@0x8c07000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c07000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio2: mdio@0x8c0b000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c0b000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio3: mdio@0x8c0f000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c0f000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio4: mdio@0x8c13000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c13000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- ifc: ifc@2240000 {
- compatible = "fsl,ifc", "simple-bus";
- reg = <0x0 0x2240000 0x0 0x20000>;
-@@ -333,13 +412,22 @@
- status = "disabled";
- };
-
-+ ftm0: ftm0@2800000 {
-+ compatible = "fsl,ls1088a-ftm-alarm";
-+ reg = <0x0 0x2800000 0x0 0x10000>,
-+ <0x0 0x1e34050 0x0 0x4>;
-+ reg-names = "ftm", "pmctrl";
-+ interrupts = <0 44 4>;
-+ };
-+
- i2c0: i2c@2000000 {
-- compatible = "fsl,vf610-i2c";
-+ compatible = "fsl,vf610-i2c", "fsl,ls1088a-vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2000000 0x0 0x10000>;
- interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&clockgen 4 3>;
-+ clocks = <&clockgen 4 7>;
-+ scl-gpios = <&gpio3 30 0>;
- status = "disabled";
- };
-
-@@ -349,7 +437,7 @@
- #size-cells = <0>;
- reg = <0x0 0x2010000 0x0 0x10000>;
- interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&clockgen 4 3>;
-+ clocks = <&clockgen 4 7>;
- status = "disabled";
- };
-
-@@ -359,7 +447,7 @@
- #size-cells = <0>;
- reg = <0x0 0x2020000 0x0 0x10000>;
- interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&clockgen 4 3>;
-+ clocks = <&clockgen 4 7>;
- status = "disabled";
- };
-
-@@ -369,7 +457,7 @@
- #size-cells = <0>;
- reg = <0x0 0x2030000 0x0 0x10000>;
- interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&clockgen 4 3>;
-+ clocks = <&clockgen 4 7>;
- status = "disabled";
- };
-
-@@ -385,6 +473,28 @@
- status = "disabled";
- };
-
-+ usb0: usb3@3100000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x3100000 0x0 0x10000>;
-+ interrupts = <0 80 0x4>; /* Level high type */
-+ dr_mode = "host";
-+ configure-gfladj;
-+ snps,dis_rxdet_inp3_quirk;
-+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+ snps,host-vbus-glitches;
-+ };
-+
-+ usb1: usb3@3110000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x3110000 0x0 0x10000>;
-+ interrupts = <0 81 0x4>; /* Level high type */
-+ dr_mode = "host";
-+ configure-gfladj;
-+ snps,dis_rxdet_inp3_quirk;
-+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+ snps,host-vbus-glitches;
-+ };
-+
- sata: sata@3200000 {
- compatible = "fsl,ls1088a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000>,
-@@ -395,6 +505,17 @@
- dma-coherent;
- status = "disabled";
- };
-+ qspi: quadspi@20c0000 {
-+ compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x20c0000 0x0 0x10000>,
-+ <0x0 0x20000000 0x0 0x10000000>;
-+ reg-names = "QuadSPI", "QuadSPI-memory";
-+ interrupts = <0 25 0x4>; /* Level high type */
-+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+ clock-names = "qspi_en", "qspi";
-+ };
-
- crypto: crypto@8000000 {
- compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
-@@ -434,6 +555,267 @@
- interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-+
-+ pcie@3400000 {
-+ compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
-+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
-+ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
-+ reg-names = "regs", "config";
-+ interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
-+ interrupt-names = "aer";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ dma-coherent;
-+ num-lanes = <4>;
-+ bus-range = <0x0 0xff>;
-+ ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
-+ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+ msi-parent = <&its>;
-+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ pcie@3500000 {
-+ compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
-+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
-+ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
-+ reg-names = "regs", "config";
-+ interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
-+ interrupt-names = "aer";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ dma-coherent;
-+ num-lanes = <4>;
-+ bus-range = <0x0 0xff>;
-+ ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
-+ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+ msi-parent = <&its>;
-+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ pcie@3600000 {
-+ compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
-+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
-+ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
-+ reg-names = "regs", "config";
-+ interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
-+ interrupt-names = "aer";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ dma-coherent;
-+ num-lanes = <8>;
-+ bus-range = <0x0 0xff>;
-+ ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
-+ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+ msi-parent = <&its>;
-+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ fsl_mc: fsl-mc@80c000000 {
-+ compatible = "fsl,qoriq-mc";
-+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
-+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
-+ msi-parent = <&its>;
-+ iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
-+ dma-coherent;
-+ #address-cells = <3>;
-+ #size-cells = <1>;
-+
-+ /*
-+ * Region type 0x0 - MC portals
-+ * Region type 0x1 - QBMAN portals
-+ */
-+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
-+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
-+
-+ dpmacs {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ dpmac1: dpmac@1 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <1>;
-+ };
-+
-+ dpmac2: dpmac@2 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <2>;
-+ };
-+
-+ dpmac3: dpmac@3 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <3>;
-+ };
-+
-+ dpmac4: dpmac@4 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <4>;
-+ };
-+
-+ dpmac5: dpmac@5 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <5>;
-+ };
-+
-+ dpmac6: dpmac@6 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <6>;
-+ };
-+
-+ dpmac7: dpmac@7 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <7>;
-+ };
-+
-+ dpmac8: dpmac@8 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <8>;
-+ };
-+
-+ dpmac9: dpmac@9 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <9>;
-+ };
-+
-+ dpmac10: dpmac@a {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0xa>;
-+ };
-+ };
-+ };
-+
-+ smmu: iommu@5000000 {
-+ compatible = "arm,mmu-500";
-+ reg = <0 0x5000000 0 0x800000>;
-+ #global-interrupts = <12>;
-+ #iommu-cells = <1>;
-+ stream-match-mask = <0x7C00>;
-+ interrupts = <0 13 4>, /* global secure fault */
-+ <0 14 4>, /* combined secure interrupt */
-+ <0 15 4>, /* global non-secure fault */
-+ <0 16 4>, /* combined non-secure interrupt */
-+ /* performance counter interrupts 0-7 */
-+ <0 211 4>,
-+ <0 212 4>,
-+ <0 213 4>,
-+ <0 214 4>,
-+ <0 215 4>,
-+ <0 216 4>,
-+ <0 217 4>,
-+ <0 218 4>,
-+ /* per context interrupt, 64 interrupts */
-+ <0 146 4>,
-+ <0 147 4>,
-+ <0 148 4>,
-+ <0 149 4>,
-+ <0 150 4>,
-+ <0 151 4>,
-+ <0 152 4>,
-+ <0 153 4>,
-+ <0 154 4>,
-+ <0 155 4>,
-+ <0 156 4>,
-+ <0 157 4>,
-+ <0 158 4>,
-+ <0 159 4>,
-+ <0 160 4>,
-+ <0 161 4>,
-+ <0 162 4>,
-+ <0 163 4>,
-+ <0 164 4>,
-+ <0 165 4>,
-+ <0 166 4>,
-+ <0 167 4>,
-+ <0 168 4>,
-+ <0 169 4>,
-+ <0 170 4>,
-+ <0 171 4>,
-+ <0 172 4>,
-+ <0 173 4>,
-+ <0 174 4>,
-+ <0 175 4>,
-+ <0 176 4>,
-+ <0 177 4>,
-+ <0 178 4>,
-+ <0 179 4>,
-+ <0 180 4>,
-+ <0 181 4>,
-+ <0 182 4>,
-+ <0 183 4>,
-+ <0 184 4>,
-+ <0 185 4>,
-+ <0 186 4>,
-+ <0 187 4>,
-+ <0 188 4>,
-+ <0 189 4>,
-+ <0 190 4>,
-+ <0 191 4>,
-+ <0 192 4>,
-+ <0 193 4>,
-+ <0 194 4>,
-+ <0 195 4>,
-+ <0 196 4>,
-+ <0 197 4>,
-+ <0 198 4>,
-+ <0 199 4>,
-+ <0 200 4>,
-+ <0 201 4>,
-+ <0 202 4>,
-+ <0 203 4>,
-+ <0 204 4>,
-+ <0 205 4>,
-+ <0 206 4>,
-+ <0 207 4>,
-+ <0 208 4>,
-+ <0 209 4>;
-+ };
-+
-+ serdes1: serdes@1ea0000 {
-+ compatible = "fsl,serdes-10g";
-+ reg = <0x0 0x1ea0000 0 0x00002000>;
-+ little-endian;
-+ };
- };
-
-+ firmware {
-+ optee {
-+ compatible = "linaro,optee-tz";
-+ method = "smc";
-+ };
-+ };
-+};
-+
-+#include "fsl-tmu-map1.dtsi"
-+
-+&thermal_zones {
-+ thermal-zone0 {
-+ status = "okay";
-+ };
-+
-+ thermal-zone1 {
-+ status = "okay";
-+ };
- };
---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree file for Freescale LS2080a QDS Board.
- *
-@@ -7,43 +8,6 @@
- * Abhimanyu Saini <abhimanyu.saini@nxp.com>
- * Bhupesh Sharma <bhupesh.sharma@freescale.com>
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- /dts-v1/;
-@@ -59,3 +23,65 @@
- stdout-path = "serial0:115200n8";
- };
- };
-+
-+&ifc {
-+ boardctrl: board-control@3,0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
-+ reg = <3 0 0x300>; /* TODO check address */
-+ ranges = <0 3 0 0x300>;
-+
-+ mdio_mux_emi1 {
-+ compatible = "mdio-mux-mmioreg", "mdio-mux";
-+ mdio-parent-bus = <&emdio1>;
-+ reg = <0x54 1>; /* BRDCFG4 */
-+ mux-mask = <0xe0>; /* EMI1_MDIO */
-+
-+ #address-cells=<1>;
-+ #size-cells = <0>;
-+
-+ /* Child MDIO buses, one for each riser card:
-+ * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
-+ * VSC8234 PHYs on the riser cards.
-+ */
-+
-+ mdio_mux3: mdio@60 {
-+ reg = <0x60>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ mdio0_phy12: mdio_phy0@1c {
-+ reg = <0x1c>;
-+ phy-connection-type = "sgmii";
-+ };
-+ mdio0_phy13: mdio_phy1@1d {
-+ reg = <0x1d>;
-+ phy-connection-type = "sgmii";
-+ };
-+ mdio0_phy14: mdio_phy2@1e {
-+ reg = <0x1e>;
-+ phy-connection-type = "sgmii";
-+ };
-+ mdio0_phy15: mdio_phy3@1f {
-+ reg = <0x1f>;
-+ phy-connection-type = "sgmii";
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
-+&dpmac9 {
-+ phy-handle = <&mdio0_phy12>;
-+};
-+&dpmac10 {
-+ phy-handle = <&mdio0_phy13>;
-+};
-+&dpmac11 {
-+ phy-handle = <&mdio0_phy14>;
-+};
-+&dpmac12 {
-+ phy-handle = <&mdio0_phy15>;
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree file for Freescale LS2080a RDB Board.
- *
-@@ -7,43 +8,6 @@
- * Abhimanyu Saini <abhimanyu.saini@nxp.com>
- * Bhupesh Sharma <bhupesh.sharma@freescale.com>
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- /dts-v1/;
-@@ -59,3 +23,83 @@
- stdout-path = "serial1:115200n8";
- };
- };
-+
-+&emdio1 {
-+ status = "disabled";
-+ /* CS4340 PHYs */
-+ mdio1_phy1: emdio1_phy@1 {
-+ reg = <0x10>;
-+ phy-connection-type = "xfi";
-+ };
-+ mdio1_phy2: emdio1_phy@2 {
-+ reg = <0x11>;
-+ phy-connection-type = "xfi";
-+ };
-+ mdio1_phy3: emdio1_phy@3 {
-+ reg = <0x12>;
-+ phy-connection-type = "xfi";
-+ };
-+ mdio1_phy4: emdio1_phy@4 {
-+ reg = <0x13>;
-+ phy-connection-type = "xfi";
-+ };
-+};
-+
-+&emdio2 {
-+ /* AQR405 PHYs */
-+ mdio2_phy1: emdio2_phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ interrupts = <0 1 0x4>; /* Level high type */
-+ reg = <0x0>;
-+ phy-connection-type = "xfi";
-+ };
-+ mdio2_phy2: emdio2_phy@2 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ interrupts = <0 2 0x4>; /* Level high type */
-+ reg = <0x1>;
-+ phy-connection-type = "xfi";
-+ };
-+ mdio2_phy3: emdio2_phy@3 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ interrupts = <0 4 0x4>; /* Level high type */
-+ reg = <0x2>;
-+ phy-connection-type = "xfi";
-+ };
-+ mdio2_phy4: emdio2_phy@4 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ interrupts = <0 5 0x4>; /* Level high type */
-+ reg = <0x3>;
-+ phy-connection-type = "xfi";
-+ };
-+};
-+
-+/* Update DPMAC connections to external PHYs, under the assumption of
-+ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
-+ */
-+/* Leave Cortina nodes commented out until driver is integrated
-+ *&dpmac1 {
-+ * phy-handle = <&mdio1_phy1>;
-+ *};
-+ *&dpmac2 {
-+ * phy-handle = <&mdio1_phy2>;
-+ *};
-+ *&dpmac3 {
-+ * phy-handle = <&mdio1_phy3>;
-+ *};
-+ *&dpmac4 {
-+ * phy-handle = <&mdio1_phy4>;
-+ *};
-+ */
-+
-+&dpmac5 {
-+ phy-handle = <&mdio2_phy1>;
-+};
-+&dpmac6 {
-+ phy-handle = <&mdio2_phy2>;
-+};
-+&dpmac7 {
-+ phy-handle = <&mdio2_phy3>;
-+};
-+&dpmac8 {
-+ phy-handle = <&mdio2_phy4>;
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree file for Freescale LS2080a software Simulator model
- *
-@@ -5,43 +6,6 @@
- *
- * Bhupesh Sharma <bhupesh.sharma@freescale.com>
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPL or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- /dts-v1/;
---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree Include file for Freescale Layerscape-2080A family SoC.
- *
-@@ -6,49 +7,12 @@
- * Abhimanyu Saini <abhimanyu.saini@nxp.com>
- * Bhupesh Sharma <bhupesh.sharma@freescale.com>
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- #include "fsl-ls208xa.dtsi"
-
- &cpu {
-- cpu0: cpu@0 {
-+ cooling_map0: cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0>;
-@@ -67,7 +31,7 @@
- next-level-cache = <&cluster0_l2>;
- };
-
-- cpu2: cpu@100 {
-+ cooling_map1: cpu2: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x100>;
-@@ -86,7 +50,7 @@
- next-level-cache = <&cluster1_l2>;
- };
-
-- cpu4: cpu@200 {
-+ cooling_map2: cpu4: cpu@200 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x200>;
-@@ -105,7 +69,7 @@
- next-level-cache = <&cluster2_l2>;
- };
-
-- cpu6: cpu@300 {
-+ cooling_map3: cpu6: cpu@300 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x300>;
-@@ -150,6 +114,10 @@
- };
- };
-
-+&timer {
-+ fsl,erratum-a008585;
-+};
-+
- &pcie1 {
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
-@@ -0,0 +1,163 @@
-+/*
-+ * Device Tree file for NXP LS2081A RDB Board.
-+ *
-+ * Copyright 2017 NXP
-+ *
-+ * Priyanka Jain <priyanka.jain@nxp.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPLv2 or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ * a) This library is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of the
-+ * License, or (at your option) any later version.
-+ *
-+ * This library is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ * b) Permission is hereby granted, free of charge, to any person
-+ * obtaining a copy of this software and associated documentation
-+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use,
-+ * copy, modify, merge, publish, distribute, sublicense, and/or
-+ * sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following
-+ * conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be
-+ * included in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+/dts-v1/;
-+
-+#include "fsl-ls2088a.dtsi"
-+
-+/ {
-+ model = "NXP Layerscape 2081A RDB Board";
-+ compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
-+
-+ aliases {
-+ serial0 = &serial0;
-+ serial1 = &serial1;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial1:115200n8";
-+ };
-+};
-+
-+&esdhc {
-+ status = "okay";
-+};
-+
-+&ifc {
-+ status = "disabled";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+ pca9547@75 {
-+ compatible = "nxp,pca9547";
-+ reg = <0x75>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ i2c@1 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x01>;
-+ rtc@51 {
-+ compatible = "nxp,pcf2129";
-+ reg = <0x51>;
-+ };
-+ };
-+
-+ i2c@2 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x02>;
-+
-+ ina220@40 {
-+ compatible = "ti,ina220";
-+ reg = <0x40>;
-+ shunt-resistor = <500>;
-+ };
-+ };
-+
-+ i2c@3 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x3>;
-+
-+ adt7481@4c {
-+ compatible = "adi,adt7461";
-+ reg = <0x4c>;
-+ };
-+ };
-+ };
-+};
-+
-+&dspi {
-+ status = "okay";
-+ dflash0: n25q512a {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "st,m25p80";
-+ spi-max-frequency = <3000000>;
-+ reg = <0>;
-+ };
-+};
-+
-+&qspi {
-+ status = "okay";
-+ fsl,qspi-has-second-chip;
-+ flash0: s25fs512s@0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "spansion,m25p80";
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <4>;
-+ spi-max-frequency = <20000000>;
-+ reg = <0>;
-+ };
-+ flash1: s25fs512s@1 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <4>;
-+ compatible = "spansion,m25p80";
-+ spi-max-frequency = <20000000>;
-+ reg = <1>;
-+ };
-+};
-+
-+&sata0 {
-+ status = "okay";
-+};
-+
-+&sata1 {
-+ status = "okay";
-+};
-+
-+&usb0 {
-+ status = "okay";
-+};
-+
-+&usb1 {
-+ status = "okay";
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree file for Freescale LS2088A QDS Board.
- *
-@@ -6,43 +7,6 @@
- *
- * Abhimanyu Saini <abhimanyu.saini@nxp.com>
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- /dts-v1/;
-@@ -58,3 +22,123 @@
- stdout-path = "serial0:115200n8";
- };
- };
-+
-+&ifc {
-+ boardctrl: board-control@3,0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
-+ reg = <3 0 0x300>; /* TODO check address */
-+ ranges = <0 3 0 0x300>;
-+
-+ mdio_mux_emi1 {
-+ compatible = "mdio-mux-mmioreg", "mdio-mux";
-+ mdio-parent-bus = <&emdio1>;
-+ reg = <0x54 1>; /* BRDCFG4 */
-+ mux-mask = <0xe0>; /* EMI1_MDIO */
-+
-+ #address-cells=<1>;
-+ #size-cells = <0>;
-+
-+ /* Child MDIO buses, one for each riser card:
-+ * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
-+ * VSC8234 PHYs on the riser cards.
-+ */
-+
-+ mdio_mux3: mdio@60 {
-+ reg = <0x60>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ mdio0_phy12: mdio_phy0@1c {
-+ reg = <0x1c>;
-+ phy-connection-type = "sgmii";
-+ };
-+ mdio0_phy13: mdio_phy1@1d {
-+ reg = <0x1d>;
-+ phy-connection-type = "sgmii";
-+ };
-+ mdio0_phy14: mdio_phy2@1e {
-+ reg = <0x1e>;
-+ phy-connection-type = "sgmii";
-+ };
-+ mdio0_phy15: mdio_phy3@1f {
-+ reg = <0x1f>;
-+ phy-connection-type = "sgmii";
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+&pcs_mdio1 {
-+ pcs_phy1: ethernet-phy@0 {
-+ backplane-mode = "10gbase-kr";
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ reg = <0x0>;
-+ fsl,lane-handle = <&serdes1>;
-+ fsl,lane-reg = <0x9C0 0x40>;/* lane H */
-+ };
-+};
-+
-+&pcs_mdio2 {
-+ pcs_phy2: ethernet-phy@0 {
-+ backplane-mode = "10gbase-kr";
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ reg = <0x0>;
-+ fsl,lane-handle = <&serdes1>;
-+ fsl,lane-reg = <0x980 0x40>;/* lane G */
-+ };
-+};
-+
-+&pcs_mdio3 {
-+ pcs_phy3: ethernet-phy@0 {
-+ backplane-mode = "10gbase-kr";
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ reg = <0x0>;
-+ fsl,lane-handle = <&serdes1>;
-+ fsl,lane-reg = <0x940 0x40>;/* lane F */
-+ };
-+};
-+
-+&pcs_mdio4 {
-+ pcs_phy4: ethernet-phy@0 {
-+ backplane-mode = "10gbase-kr";
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ reg = <0x0>;
-+ fsl,lane-handle = <&serdes1>;
-+ fsl,lane-reg = <0x900 0x40>;/* lane E */
-+ };
-+};
-+
-+/* Update DPMAC connections to backplane PHYs, under SerDes 0x2a_0xXX.
-+ * &dpmac1 {
-+ * phy-handle = <&pcs_phy1>;
-+ * };
-+ *
-+ * &dpmac2 {
-+ * phy-handle = <&pcs_phy2>;
-+ * };
-+ *
-+ * &dpmac3 {
-+ * phy-handle = <&pcs_phy3>;
-+ * };
-+ *
-+ * &dpmac4 {
-+ * phy-handle = <&pcs_phy4>;
-+ * };
-+ */
-+
-+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
-+&dpmac9 {
-+ phy-handle = <&mdio0_phy12>;
-+};
-+&dpmac10 {
-+ phy-handle = <&mdio0_phy13>;
-+};
-+&dpmac11 {
-+ phy-handle = <&mdio0_phy14>;
-+};
-+&dpmac12 {
-+ phy-handle = <&mdio0_phy15>;
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree file for Freescale LS2088A RDB Board.
- *
-@@ -6,43 +7,6 @@
- *
- * Abhimanyu Saini <abhimanyu.saini@nxp.com>
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- /dts-v1/;
-@@ -58,3 +22,83 @@
- stdout-path = "serial1:115200n8";
- };
- };
-+
-+&emdio1 {
-+ status = "disabled";
-+ /* CS4340 PHYs */
-+ mdio1_phy1: emdio1_phy@1 {
-+ reg = <0x10>;
-+ phy-connection-type = "xfi";
-+ };
-+ mdio1_phy2: emdio1_phy@2 {
-+ reg = <0x11>;
-+ phy-connection-type = "xfi";
-+ };
-+ mdio1_phy3: emdio1_phy@3 {
-+ reg = <0x12>;
-+ phy-connection-type = "xfi";
-+ };
-+ mdio1_phy4: emdio1_phy@4 {
-+ reg = <0x13>;
-+ phy-connection-type = "xfi";
-+ };
-+};
-+
-+&emdio2 {
-+ /* AQR405 PHYs */
-+ mdio2_phy1: emdio2_phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ interrupts = <0 1 0x4>; /* Level high type */
-+ reg = <0x0>;
-+ phy-connection-type = "xfi";
-+ };
-+ mdio2_phy2: emdio2_phy@2 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ interrupts = <0 2 0x4>; /* Level high type */
-+ reg = <0x1>;
-+ phy-connection-type = "xfi";
-+ };
-+ mdio2_phy3: emdio2_phy@3 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ interrupts = <0 4 0x4>; /* Level high type */
-+ reg = <0x2>;
-+ phy-connection-type = "xfi";
-+ };
-+ mdio2_phy4: emdio2_phy@4 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ interrupts = <0 5 0x4>; /* Level high type */
-+ reg = <0x3>;
-+ phy-connection-type = "xfi";
-+ };
-+};
-+
-+/* Update DPMAC connections to external PHYs, under the assumption of
-+ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
-+ */
-+/* Leave Cortina PHYs commented out until proper driver is integrated
-+ *&dpmac1 {
-+ * phy-handle = <&mdio1_phy1>;
-+ *};
-+ *&dpmac2 {
-+ * phy-handle = <&mdio1_phy2>;
-+ *};
-+ *&dpmac3 {
-+ * phy-handle = <&mdio1_phy3>;
-+ *};
-+ *&dpmac4 {
-+ * phy-handle = <&mdio1_phy4>;
-+ *};
-+ */
-+
-+&dpmac5 {
-+ phy-handle = <&mdio2_phy1>;
-+};
-+&dpmac6 {
-+ phy-handle = <&mdio2_phy2>;
-+};
-+&dpmac7 {
-+ phy-handle = <&mdio2_phy3>;
-+};
-+&dpmac8 {
-+ phy-handle = <&mdio2_phy4>;
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree Include file for Freescale Layerscape-2088A family SoC.
- *
-@@ -6,49 +7,12 @@
- *
- * Abhimanyu Saini <abhimanyu.saini@nxp.com>
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- #include "fsl-ls208xa.dtsi"
-
- &cpu {
-- cpu0: cpu@0 {
-+ cooling_map0: cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a72";
- reg = <0x0>;
-@@ -67,7 +31,7 @@
- next-level-cache = <&cluster0_l2>;
- };
-
-- cpu2: cpu@100 {
-+ cooling_map1: cpu2: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a72";
- reg = <0x100>;
-@@ -86,7 +50,7 @@
- next-level-cache = <&cluster1_l2>;
- };
-
-- cpu4: cpu@200 {
-+ cooling_map2: cpu4: cpu@200 {
- device_type = "cpu";
- compatible = "arm,cortex-a72";
- reg = <0x200>;
-@@ -105,7 +69,7 @@
- next-level-cache = <&cluster2_l2>;
- };
-
-- cpu6: cpu@300 {
-+ cooling_map3: cpu6: cpu@300 {
- device_type = "cpu";
- compatible = "arm,cortex-a72";
- reg = <0x300>;
-@@ -143,7 +107,7 @@
- CPU_PW20: cpu-pw20 {
- compatible = "arm,idle-state";
- idle-state-name = "PW20";
-- arm,psci-suspend-param = <0x00010000>;
-+ arm,psci-suspend-param = <0x0>;
- entry-latency-us = <2000>;
- exit-latency-us = <2000>;
- min-residency-us = <6000>;
-@@ -151,6 +115,7 @@
- };
-
- &pcie1 {
-+ compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
-
-@@ -159,6 +124,7 @@
- };
-
- &pcie2 {
-+ compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
-
-@@ -167,6 +133,7 @@
- };
-
- &pcie3 {
-+ compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
-
-@@ -175,6 +142,7 @@
- };
-
- &pcie4 {
-+ compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
- reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
- 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
-
---- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree file for Freescale LS2080A QDS Board.
- *
-@@ -6,43 +7,6 @@
- *
- * Abhimanyu Saini <abhimanyu.saini@nxp.com>
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- &esdhc {
-@@ -165,16 +129,21 @@
-
- &qspi {
- status = "okay";
-+ fsl,qspi-has-second-chip;
- flash0: s25fl256s1@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,m25p80";
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <4>;
- spi-max-frequency = <20000000>;
- reg = <0>;
- };
- flash2: s25fl256s1@2 {
- #address-cells = <1>;
- #size-cells = <1>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <4>;
- compatible = "st,m25p80";
- spi-max-frequency = <20000000>;
- reg = <0>;
---- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree file for Freescale LS2080A RDB Board.
- *
-@@ -6,43 +7,6 @@
- *
- * Abhimanyu Saini <abhimanyu.saini@nxp.com>
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- &esdhc {
-@@ -85,6 +49,7 @@
- reg = <0x75>;
- #address-cells = <1>;
- #size-cells = <0>;
-+ i2c-mux-never-disable;
- i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-@@ -95,6 +60,17 @@
- };
- };
-
-+ i2c@2 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x02>;
-+ ina220@40 {
-+ compatible = "ti,ina220";
-+ reg = <0x40>;
-+ shunt-resistor = <500>;
-+ };
-+ };
-+
- i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
-@@ -132,7 +108,15 @@
- };
-
- &qspi {
-- status = "disabled";
-+ status = "okay";
-+ flash0: s25fs512s@0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "spansion,m25p80";
-+ m25p,fast-read;
-+ spi-max-frequency = <20000000>;
-+ reg = <0>;
-+ };
- };
-
- &sata0 {
---- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
- * Device Tree Include file for Freescale Layerscape-2080A family SoC.
- *
-@@ -6,43 +7,6 @@
- *
- * Abhimanyu Saini <abhimanyu.saini@nxp.com>
- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- * a) This library is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of the
-- * License, or (at your option) any later version.
-- *
-- * This library is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- * b) Permission is hereby granted, free of charge, to any person
-- * obtaining a copy of this software and associated documentation
-- * files (the "Software"), to deal in the Software without
-- * restriction, including without limitation the rights to use,
-- * copy, modify, merge, publish, distribute, sublicense, and/or
-- * sell copies of the Software, and to permit persons to whom the
-- * Software is furnished to do so, subject to the following
-- * conditions:
-- *
-- * The above copyright notice and this permission notice shall be
-- * included in all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
- #include <dt-bindings/thermal/thermal.h>
-@@ -111,13 +75,12 @@
- mask = <0x2>;
- };
-
-- timer {
-+ timer: timer {
- compatible = "arm,armv8-timer";
- interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
- <1 14 4>, /* Physical Non-Secure PPI, active-low */
- <1 11 4>, /* Virtual PPI, active-low */
- <1 10 4>; /* Hypervisor PPI, active-low */
-- fsl,erratum-a008585;
- };
-
- pmu {
-@@ -135,6 +98,7 @@
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
-
- clockgen: clocking@1300000 {
- compatible = "fsl,ls2080a-clockgen";
-@@ -194,54 +158,7 @@
- #thermal-sensor-cells = <1>;
- };
-
-- thermal-zones {
-- cpu_thermal: cpu-thermal {
-- polling-delay-passive = <1000>;
-- polling-delay = <5000>;
--
-- thermal-sensors = <&tmu 4>;
--
-- trips {
-- cpu_alert: cpu-alert {
-- temperature = <75000>;
-- hysteresis = <2000>;
-- type = "passive";
-- };
-- cpu_crit: cpu-crit {
-- temperature = <85000>;
-- hysteresis = <2000>;
-- type = "critical";
-- };
-- };
--
-- cooling-maps {
-- map0 {
-- trip = <&cpu_alert>;
-- cooling-device =
-- <&cpu0 THERMAL_NO_LIMIT
-- THERMAL_NO_LIMIT>;
-- };
-- map1 {
-- trip = <&cpu_alert>;
-- cooling-device =
-- <&cpu2 THERMAL_NO_LIMIT
-- THERMAL_NO_LIMIT>;
-- };
-- map2 {
-- trip = <&cpu_alert>;
-- cooling-device =
-- <&cpu4 THERMAL_NO_LIMIT
-- THERMAL_NO_LIMIT>;
-- };
-- map3 {
-- trip = <&cpu_alert>;
-- cooling-device =
-- <&cpu6 THERMAL_NO_LIMIT
-- THERMAL_NO_LIMIT>;
-- };
-- };
-- };
-- };
-+ #include "fsl-tmu.dtsi"
-
- serial0: serial@21c0500 {
- compatible = "fsl,ns16550", "ns16550a";
-@@ -357,6 +274,8 @@
- reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
- <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
- msi-parent = <&its>;
-+ iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
-+ dma-coherent;
- #address-cells = <3>;
- #size-cells = <1>;
-
-@@ -460,6 +379,8 @@
- compatible = "arm,mmu-500";
- reg = <0 0x5000000 0 0x800000>;
- #global-interrupts = <12>;
-+ #iommu-cells = <1>;
-+ stream-match-mask = <0x7C00>;
- interrupts = <0 13 4>, /* global secure fault */
- <0 14 4>, /* combined secure interrupt */
- <0 15 4>, /* global non-secure fault */
-@@ -502,7 +423,6 @@
- <0 204 4>, <0 205 4>,
- <0 206 4>, <0 207 4>,
- <0 208 4>, <0 209 4>;
-- mmu-masters = <&fsl_mc 0x300 0>;
- };
-
- dspi: dspi@2100000 {
-@@ -574,15 +494,126 @@
- #interrupt-cells = <2>;
- };
-
-+ /* TODO: WRIOP (CCSR?) */
-+ emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
-+ * E-MDIO1: 0x1_6000
-+ */
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8B96000 0x0 0x1000>;
-+ device_type = "mdio"; /* TODO: is this necessary? */
-+ little-endian; /* force the driver in LE mode */
-+
-+ /* Not necessary on the QDS, but needed on the RDB */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
-+ * E-MDIO2: 0x1_7000
-+ */
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8B97000 0x0 0x1000>;
-+ device_type = "mdio"; /* TODO: is this necessary? */
-+ little-endian; /* force the driver in LE mode */
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio1: mdio@0x8c07000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c07000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio2: mdio@0x8c0b000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c0b000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio3: mdio@0x8c0f000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c0f000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio4: mdio@0x8c13000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c13000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio5: mdio@0x8c17000 {
-+ status = "disabled";
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c17000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio6: mdio@0x8c1b000 {
-+ status = "disabled";
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c1b000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio7: mdio@0x8c1f000 {
-+ status = "disabled";
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c1f000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio8: mdio@0x8c23000 {
-+ status = "disabled";
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c23000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- i2c0: i2c@2000000 {
- status = "disabled";
-- compatible = "fsl,vf610-i2c";
-+ compatible = "fsl,vf610-i2c", "fsl,ls208xa-vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2000000 0x0 0x10000>;
- interrupts = <0 34 0x4>; /* Level high type */
- clock-names = "i2c";
-- clocks = <&clockgen 4 3>;
-+ clocks = <&clockgen 4 1>;
-+ scl-gpios = <&gpio3 10 0>;
- };
-
- i2c1: i2c@2010000 {
-@@ -593,7 +624,7 @@
- reg = <0x0 0x2010000 0x0 0x10000>;
- interrupts = <0 34 0x4>; /* Level high type */
- clock-names = "i2c";
-- clocks = <&clockgen 4 3>;
-+ clocks = <&clockgen 4 1>;
- };
-
- i2c2: i2c@2020000 {
-@@ -604,7 +635,7 @@
- reg = <0x0 0x2020000 0x0 0x10000>;
- interrupts = <0 35 0x4>; /* Level high type */
- clock-names = "i2c";
-- clocks = <&clockgen 4 3>;
-+ clocks = <&clockgen 4 1>;
- };
-
- i2c3: i2c@2030000 {
-@@ -615,7 +646,7 @@
- reg = <0x0 0x2030000 0x0 0x10000>;
- interrupts = <0 35 0x4>; /* Level high type */
- clock-names = "i2c";
-- clocks = <&clockgen 4 3>;
-+ clocks = <&clockgen 4 1>;
- };
-
- ifc: ifc@2240000 {
-@@ -648,8 +679,8 @@
- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
- "snps,dw-pcie";
- reg-names = "regs", "config";
-- interrupts = <0 108 0x4>; /* Level high type */
-- interrupt-names = "intr";
-+ interrupts = <0 108 0x4>; /* aer interrupt */
-+ interrupt-names = "aer";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
-@@ -657,20 +688,22 @@
- num-lanes = <4>;
- bus-range = <0x0 0xff>;
- msi-parent = <&its>;
-+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
- <0000 0 0 2 &gic 0 0 0 110 4>,
- <0000 0 0 3 &gic 0 0 0 111 4>,
- <0000 0 0 4 &gic 0 0 0 112 4>;
-+ status = "disabled";
- };
-
- pcie2: pcie@3500000 {
- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
- "snps,dw-pcie";
- reg-names = "regs", "config";
-- interrupts = <0 113 0x4>; /* Level high type */
-- interrupt-names = "intr";
-+ interrupts = <0 113 0x4>; /* aer interrupt */
-+ interrupt-names = "aer";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
-@@ -678,20 +711,22 @@
- num-lanes = <4>;
- bus-range = <0x0 0xff>;
- msi-parent = <&its>;
-+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
- <0000 0 0 2 &gic 0 0 0 115 4>,
- <0000 0 0 3 &gic 0 0 0 116 4>,
- <0000 0 0 4 &gic 0 0 0 117 4>;
-+ status = "disabled";
- };
-
- pcie3: pcie@3600000 {
- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
- "snps,dw-pcie";
- reg-names = "regs", "config";
-- interrupts = <0 118 0x4>; /* Level high type */
-- interrupt-names = "intr";
-+ interrupts = <0 118 0x4>; /* aer interrupt */
-+ interrupt-names = "aer";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
-@@ -699,20 +734,22 @@
- num-lanes = <8>;
- bus-range = <0x0 0xff>;
- msi-parent = <&its>;
-+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
- <0000 0 0 2 &gic 0 0 0 120 4>,
- <0000 0 0 3 &gic 0 0 0 121 4>,
- <0000 0 0 4 &gic 0 0 0 122 4>;
-+ status = "disabled";
- };
-
- pcie4: pcie@3700000 {
- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
- "snps,dw-pcie";
- reg-names = "regs", "config";
-- interrupts = <0 123 0x4>; /* Level high type */
-- interrupt-names = "intr";
-+ interrupts = <0 123 0x4>; /* aer interrupt */
-+ interrupt-names = "aer";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
-@@ -720,12 +757,14 @@
- num-lanes = <4>;
- bus-range = <0x0 0xff>;
- msi-parent = <&its>;
-+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
- <0000 0 0 2 &gic 0 0 0 125 4>,
- <0000 0 0 3 &gic 0 0 0 126 4>,
- <0000 0 0 4 &gic 0 0 0 127 4>;
-+ status = "disabled";
- };
-
- sata0: sata@3200000 {
-@@ -754,6 +793,8 @@
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
-+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+ snps,host-vbus-glitches;
- };
-
- usb1: usb3@3110000 {
-@@ -764,6 +805,14 @@
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
-+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+ snps,host-vbus-glitches;
-+ };
-+
-+ serdes1: serdes@1ea0000 {
-+ compatible = "fsl,serdes-10g";
-+ reg = <0x0 0x1ea0000 0 0x00002000>;
-+ little-endian;
- };
-
- ccn@4000000 {
-@@ -771,6 +820,14 @@
- reg = <0x0 0x04000000 0x0 0x01000000>;
- interrupts = <0 12 4>;
- };
-+
-+ ftm0: ftm0@2800000 {
-+ compatible = "fsl,ls208xa-ftm-alarm";
-+ reg = <0x0 0x2800000 0x0 0x10000>,
-+ <0x0 0x1e34050 0x0 0x4>;
-+ reg-names = "ftm", "pmctrl";
-+ interrupts = <0 44 4>;
-+ };
- };
-
- ddr1: memory-controller@1080000 {
-@@ -786,4 +843,44 @@
- interrupts = <0 18 0x4>;
- little-endian;
- };
-+
-+ firmware {
-+ optee {
-+ compatible = "linaro,optee-tz";
-+ method = "smc";
-+ };
-+ };
-+};
-+
-+#include "fsl-tmu-map1.dtsi"
-+#include "fsl-tmu-map2.dtsi"
-+#include "fsl-tmu-map3.dtsi"
-+&thermal_zones {
-+ thermal-zone1 {
-+ status = "okay";
-+ };
-+
-+ thermal-zone2{
-+ status = "okay";
-+ };
-+
-+ thermal-zone3{
-+ status = "okay";
-+ };
-+
-+ thermal-zone4{
-+ status = "okay";
-+ };
-+
-+ thermal-zone5{
-+ status = "okay";
-+ };
-+
-+ thermal-zone6{
-+ status = "okay";
-+ };
-+
-+ thermal-zone7 {
-+ status = "okay";
-+ };
- };
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
-@@ -0,0 +1,353 @@
-+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-+//
-+// Device Tree file for LX2160AQDS
-+//
-+// Copyright 2018 NXP
-+
-+/dts-v1/;
-+
-+#include "fsl-lx2160a.dtsi"
-+
-+/ {
-+ model = "NXP Layerscape LX2160AQDS";
-+ compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
-+
-+ aliases {
-+ crypto = &crypto;
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ sb_3v3: regulator-sb3v3 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "MC34717-3.3VSB";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-boot-on;
-+ regulator-always-on;
-+ };
-+
-+ mdio-mux-1 {
-+ compatible = "mdio-mux-multiplexer";
-+ mux-controls = <&mux 0>;
-+ mdio-parent-bus = <&emdio1>;
-+ #address-cells=<1>;
-+ #size-cells = <0>;
-+
-+ mdio@0 { /* On-board PHY #1 RGMI1*/
-+ reg = <0x00>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mdio@8 { /* On-board PHY #2 RGMI2*/
-+ reg = <0x8>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mdio@18 { /* Slot #1 */
-+ reg = <0x18>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mdio@19 { /* Slot #2 */
-+ reg = <0x19>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mdio@1a { /* Slot #3 */
-+ reg = <0x1a>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mdio@1b { /* Slot #4 */
-+ reg = <0x1b>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mdio@1c { /* Slot #5 */
-+ reg = <0x1c>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mdio@1d { /* Slot #6 */
-+ reg = <0x1d>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mdio@1e { /* Slot #7 */
-+ reg = <0x1e>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mdio@1f { /* Slot #8 */
-+ reg = <0x1f>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+ };
-+
-+ mdio-mux-2 {
-+ compatible = "mdio-mux-multiplexer";
-+ mux-controls = <&mux 1>;
-+ mdio-parent-bus = <&emdio2>;
-+ #address-cells=<1>;
-+ #size-cells = <0>;
-+
-+ mdio@0 { /* Slot #1 (secondary EMI) */
-+ reg = <0x00>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mdio@1 { /* Slot #2 (secondary EMI) */
-+ reg = <0x01>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mdio@2 { /* Slot #3 (secondary EMI) */
-+ reg = <0x02>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mdio@3 { /* Slot #4 (secondary EMI) */
-+ reg = <0x03>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mdio@4 { /* Slot #5 (secondary EMI) */
-+ reg = <0x04>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mdio@5 { /* Slot #6 (secondary EMI) */
-+ reg = <0x05>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mdio@6 { /* Slot #7 (secondary EMI) */
-+ reg = <0x06>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mdio@7 { /* Slot #8 (secondary EMI) */
-+ reg = <0x07>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+ };
-+};
-+
-+&crypto {
-+ status = "okay";
-+};
-+
-+&dspi0 {
-+ status = "okay";
-+
-+ dflash0: flash@0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "jedec,spi-nor";
-+ reg = <0>;
-+ spi-max-frequency = <1000000>;
-+ };
-+};
-+
-+&dspi1 {
-+ status = "okay";
-+
-+ dflash1: flash@0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "jedec,spi-nor";
-+ reg = <0>;
-+ spi-max-frequency = <1000000>;
-+ };
-+};
-+
-+&dspi2 {
-+ status = "okay";
-+
-+ dflash2: flash@0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "jedec,spi-nor";
-+ reg = <0>;
-+ spi-max-frequency = <1000000>;
-+ };
-+};
-+
-+&emdio1 {
-+ status = "okay";
-+};
-+
-+&emdio2 {
-+ status = "okay";
-+};
-+
-+&esdhc0 {
-+ status = "okay";
-+};
-+
-+&esdhc1 {
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+
-+ fpga@66 {
-+ compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
-+ "simple-mfd";
-+ reg = <0x66>;
-+
-+ mux: mux-controller {
-+ compatible = "reg-mux";
-+ #mux-control-cells = <1>;
-+ mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
-+ <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
-+ };
-+ };
-+
-+ i2c-mux@77 {
-+ compatible = "nxp,pca9547";
-+ reg = <0x77>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ i2c@2 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x2>;
-+
-+ power-monitor@40 {
-+ compatible = "ti,ina220";
-+ reg = <0x40>;
-+ shunt-resistor = <500>;
-+ };
-+
-+ power-monitor@41 {
-+ compatible = "ti,ina220";
-+ reg = <0x41>;
-+ shunt-resistor = <1000>;
-+ };
-+ };
-+
-+ i2c@3 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x3>;
-+
-+ temperature-sensor@4c {
-+ compatible = "nxp,sa56004";
-+ reg = <0x4c>;
-+ vcc-supply = <&sb_3v3>;
-+ };
-+
-+ temperature-sensor@4d {
-+ compatible = "nxp,sa56004";
-+ reg = <0x4d>;
-+ vcc-supply = <&sb_3v3>;
-+ };
-+
-+ rtc@51 {
-+ compatible = "nxp,pcf2129";
-+ reg = <0x51>;
-+ };
-+ };
-+ };
-+};
-+
-+&uart0 {
-+ status = "okay";
-+};
-+
-+&uart1 {
-+ status = "okay";
-+};
-+
-+&usb0 {
-+ status = "okay";
-+};
-+
-+&usb1 {
-+ status = "okay";
-+};
-+
-+&pcs_mdio1 {
-+ pcs_phy1: ethernet-phy@0 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ backplane-mode = "40gbase-kr";
-+ reg = <0x0>;
-+ fsl,lane-handle = <&serdes1>;
-+ fsl,lane-reg = <0xF00 0xE00 0xD00 0xC00>; /* lanes H, G, F, E */
-+ };
-+};
-+
-+&pcs_mdio2 {
-+ pcs_phy2: ethernet-phy@0 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ backplane-mode = "40gbase-kr";
-+ reg = <0x0>;
-+ fsl,lane-handle = <&serdes1>;
-+ fsl,lane-reg = <0xB00 0xA00 0x900 0x800>; /* lanes D, C, B, A */
-+ };
-+};
-+
-+&pcs_mdio3 {
-+ pcs_phy3: ethernet-phy@0 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ backplane-mode = "10gbase-kr";
-+ reg = <0x0>;
-+ fsl,lane-handle = <&serdes1>;
-+ fsl,lane-reg = <0xF00 0x100>; /* lane H */
-+ };
-+};
-+
-+&pcs_mdio4 {
-+ pcs_phy4: ethernet-phy@0 {
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ backplane-mode = "10gbase-kr";
-+ reg = <0x0>;
-+ fsl,lane-handle = <&serdes1>;
-+ fsl,lane-reg = <0xE00 0x100>; /* lane G */
-+ };
-+};
-+
-+/* Update DPMAC connections to 40G backplane PHYs
-+ * &dpmac1 {
-+ * phy-handle = <&pcs_phy1>;
-+ * };
-+ *
-+ * &dpmac2 {
-+ * phy-handle = <&pcs_phy2>;
-+ * };
-+ */
-+
-+/* Update DPMAC connections to 10G backplane PHYs
-+ * &dpmac3 {
-+ * phy-handle = <&pcs_phy3>;
-+ * };
-+ *
-+ * &dpmac4 {
-+ * phy-handle = <&pcs_phy4>;
-+ * };
-+ */
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
-@@ -0,0 +1,233 @@
-+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-+//
-+// Device Tree file for LX2160ARDB
-+//
-+// Copyright 2018 NXP
-+
-+/dts-v1/;
-+
-+#include "fsl-lx2160a.dtsi"
-+
-+/ {
-+ model = "NXP Layerscape LX2160ARDB";
-+ compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
-+
-+ aliases {
-+ crypto = &crypto;
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ sb_3v3: regulator-sb3v3 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "MC34717-3.3VSB";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-boot-on;
-+ regulator-always-on;
-+ };
-+};
-+
-+&crypto {
-+ status = "okay";
-+};
-+
-+&emdio1 {
-+ status = "okay";
-+};
-+
-+&emdio2 {
-+ status = "okay";
-+};
-+
-+&esdhc0 {
-+ sd-uhs-sdr104;
-+ sd-uhs-sdr50;
-+ sd-uhs-sdr25;
-+ sd-uhs-sdr12;
-+ status = "okay";
-+};
-+
-+&esdhc1 {
-+ mmc-hs200-1_8v;
-+ mmc-hs400-1_8v;
-+ bus-width = <8>;
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+
-+ i2c-mux@77 {
-+ compatible = "nxp,pca9547";
-+ reg = <0x77>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ i2c@2 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x2>;
-+
-+ power-monitor@40 {
-+ compatible = "ti,ina220";
-+ reg = <0x40>;
-+ shunt-resistor = <1000>;
-+ };
-+ };
-+
-+ i2c@3 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x3>;
-+
-+ temperature-sensor@4c {
-+ compatible = "nxp,sa56004";
-+ reg = <0x4c>;
-+ vcc-supply = <&sb_3v3>;
-+ };
-+
-+ temperature-sensor@4d {
-+ compatible = "nxp,sa56004";
-+ reg = <0x4d>;
-+ vcc-supply = <&sb_3v3>;
-+ };
-+ };
-+ };
-+};
-+
-+&i2c4 {
-+ status = "okay";
-+
-+ rtc@51 {
-+ compatible = "nxp,pcf2129";
-+ reg = <0x51>;
-+ // IRQ10_B
-+ interrupts = <0 150 0x4>;
-+ };
-+};
-+
-+&fspi {
-+ status = "okay";
-+ nxp,fspi-has-second-chip;
-+ flash0: mt35xu512aba@0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "micron,m25p80";
-+ m25p,fast-read;
-+ spi-max-frequency = <50000000>;
-+ reg = <0>;
-+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
-+ spi-rx-bus-width = <8>;
-+ spi-tx-bus-width = <1>;
-+ };
-+
-+ flash1: mt35xu512aba@1 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "micron,m25p80";
-+ m25p,fast-read;
-+ spi-max-frequency = <50000000>;
-+ reg = <1>;
-+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
-+ spi-rx-bus-width = <8>;
-+ spi-tx-bus-width = <1>;
-+ };
-+};
-+
-+&uart0 {
-+ status = "okay";
-+};
-+
-+&uart1 {
-+ status = "okay";
-+};
-+
-+&usb0 {
-+ status = "okay";
-+};
-+
-+&usb1 {
-+ status = "okay";
-+};
-+
-+&emdio1 {
-+ rgmii_phy1: ethernet-phy@1 {
-+ /* AR8035 PHY - "compatible" property not strictly needed */
-+ compatible = "ethernet-phy-id004d.d072";
-+ reg = <0x1>;
-+ /* Poll mode - no "interrupts" property defined */
-+ };
-+ rgmii_phy2: ethernet-phy@2 {
-+ /* AR8035 PHY - "compatible" property not strictly needed */
-+ compatible = "ethernet-phy-id004d.d072";
-+ reg = <0x2>;
-+ /* Poll mode - no "interrupts" property defined */
-+ };
-+ aquantia_phy1: ethernet-phy@4 {
-+ /* AQR107 PHY - "compatible" property not strictly needed */
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ reg = <0x4>;
-+ /* Poll mode - no "interrupts" property defined */
-+ };
-+ aquantia_phy2: ethernet-phy@5 {
-+ /* AQR107 PHY - "compatible" property not strictly needed */
-+ compatible = "ethernet-phy-ieee802.3-c45";
-+ reg = <0x5>;
-+ /* Poll mode - no "interrupts" property defined */
-+ };
-+};
-+
-+&emdio2 {
-+ inphi_phy: ethernet-phy@0 {
-+ compatible = "ethernet-phy-id0210.7440";
-+ reg = <0x0>;
-+ };
-+};
-+
-+&dpmac3 {
-+ phy-handle = <&aquantia_phy1>;
-+ phy-connection-type = "xgmii";
-+};
-+
-+&dpmac4 {
-+ phy-handle = <&aquantia_phy2>;
-+ phy-connection-type = "xgmii";
-+};
-+
-+&dpmac5 {
-+ phy-handle = <&inphi_phy>;
-+};
-+
-+&dpmac6 {
-+ phy-handle = <&inphi_phy>;
-+};
-+
-+&dpmac17 {
-+ phy-handle = <&rgmii_phy1>;
-+ phy-connection-type = "rgmii-id";
-+};
-+
-+&dpmac18 {
-+ phy-handle = <&rgmii_phy2>;
-+ phy-connection-type = "rgmii-id";
-+};
-+
-+&sata0 {
-+ status = "okay";
-+};
-+
-+&sata1 {
-+ status = "okay";
-+};
-+
-+&sata2 {
-+ status = "okay";
-+};
-+
-+&sata3 {
-+ status = "okay";
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
-@@ -0,0 +1,1318 @@
-+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-+//
-+// Device Tree Include file for Layerscape-LX2160A family SoC.
-+//
-+// Copyright 2018 NXP
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+
-+/memreserve/ 0x80000000 0x00010000;
-+
-+/ {
-+ compatible = "fsl,lx2160a";
-+ interrupt-parent = <&gic>;
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+
-+ cpus {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ // 8 clusters having 2 Cortex-A72 cores each
-+ cpu@0 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
-+ reg = <0x0>;
-+ clocks = <&clockgen 1 0>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ i-cache-size = <0xC000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <192>;
-+ next-level-cache = <&cluster0_l2>;
-+ };
-+
-+ cpu@1 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
-+ reg = <0x1>;
-+ clocks = <&clockgen 1 0>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ i-cache-size = <0xC000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <192>;
-+ next-level-cache = <&cluster0_l2>;
-+ };
-+
-+ cpu@100 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
-+ reg = <0x100>;
-+ clocks = <&clockgen 1 1>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ i-cache-size = <0xC000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <192>;
-+ next-level-cache = <&cluster1_l2>;
-+ };
-+
-+ cpu@101 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
-+ reg = <0x101>;
-+ clocks = <&clockgen 1 1>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ i-cache-size = <0xC000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <192>;
-+ next-level-cache = <&cluster1_l2>;
-+ };
-+
-+ cpu@200 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
-+ reg = <0x200>;
-+ clocks = <&clockgen 1 2>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ i-cache-size = <0xC000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <192>;
-+ next-level-cache = <&cluster2_l2>;
-+ };
-+
-+ cpu@201 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
-+ reg = <0x201>;
-+ clocks = <&clockgen 1 2>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ i-cache-size = <0xC000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <192>;
-+ next-level-cache = <&cluster2_l2>;
-+ };
-+
-+ cpu@300 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
-+ reg = <0x300>;
-+ clocks = <&clockgen 1 3>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ i-cache-size = <0xC000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <192>;
-+ next-level-cache = <&cluster3_l2>;
-+ };
-+
-+ cpu@301 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
-+ reg = <0x301>;
-+ clocks = <&clockgen 1 3>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ i-cache-size = <0xC000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <192>;
-+ next-level-cache = <&cluster3_l2>;
-+ };
-+
-+ cpu@400 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
-+ reg = <0x400>;
-+ clocks = <&clockgen 1 4>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ i-cache-size = <0xC000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <192>;
-+ next-level-cache = <&cluster4_l2>;
-+ };
-+
-+ cpu@401 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
-+ reg = <0x401>;
-+ clocks = <&clockgen 1 4>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ i-cache-size = <0xC000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <192>;
-+ next-level-cache = <&cluster4_l2>;
-+ };
-+
-+ cpu@500 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
-+ reg = <0x500>;
-+ clocks = <&clockgen 1 5>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ i-cache-size = <0xC000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <192>;
-+ next-level-cache = <&cluster5_l2>;
-+ };
-+
-+ cpu@501 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
-+ reg = <0x501>;
-+ clocks = <&clockgen 1 5>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ i-cache-size = <0xC000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <192>;
-+ next-level-cache = <&cluster5_l2>;
-+ };
-+
-+ cpu@600 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
-+ reg = <0x600>;
-+ clocks = <&clockgen 1 6>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ i-cache-size = <0xC000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <192>;
-+ next-level-cache = <&cluster6_l2>;
-+ };
-+
-+ cpu@601 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
-+ reg = <0x601>;
-+ clocks = <&clockgen 1 6>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ i-cache-size = <0xC000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <192>;
-+ next-level-cache = <&cluster6_l2>;
-+ };
-+
-+ cpu@700 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
-+ reg = <0x700>;
-+ clocks = <&clockgen 1 7>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ i-cache-size = <0xC000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <192>;
-+ next-level-cache = <&cluster7_l2>;
-+ };
-+
-+ cpu@701 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
-+ reg = <0x701>;
-+ clocks = <&clockgen 1 7>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ i-cache-size = <0xC000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <192>;
-+ next-level-cache = <&cluster7_l2>;
-+ };
-+
-+ cluster0_l2: l2-cache0 {
-+ compatible = "cache";
-+ cache-size = <0x100000>;
-+ cache-line-size = <64>;
-+ cache-sets = <1024>;
-+ cache-level = <2>;
-+ };
-+
-+ cluster1_l2: l2-cache1 {
-+ compatible = "cache";
-+ cache-size = <0x100000>;
-+ cache-line-size = <64>;
-+ cache-sets = <1024>;
-+ cache-level = <2>;
-+ };
-+
-+ cluster2_l2: l2-cache2 {
-+ compatible = "cache";
-+ cache-size = <0x100000>;
-+ cache-line-size = <64>;
-+ cache-sets = <1024>;
-+ cache-level = <2>;
-+ };
-+
-+ cluster3_l2: l2-cache3 {
-+ compatible = "cache";
-+ cache-size = <0x100000>;
-+ cache-line-size = <64>;
-+ cache-sets = <1024>;
-+ cache-level = <2>;
-+ };
-+
-+ cluster4_l2: l2-cache4 {
-+ compatible = "cache";
-+ cache-size = <0x100000>;
-+ cache-line-size = <64>;
-+ cache-sets = <1024>;
-+ cache-level = <2>;
-+ };
-+
-+ cluster5_l2: l2-cache5 {
-+ compatible = "cache";
-+ cache-size = <0x100000>;
-+ cache-line-size = <64>;
-+ cache-sets = <1024>;
-+ cache-level = <2>;
-+ };
-+
-+ cluster6_l2: l2-cache6 {
-+ compatible = "cache";
-+ cache-size = <0x100000>;
-+ cache-line-size = <64>;
-+ cache-sets = <1024>;
-+ cache-level = <2>;
-+ };
-+
-+ cluster7_l2: l2-cache7 {
-+ compatible = "cache";
-+ cache-size = <0x100000>;
-+ cache-line-size = <64>;
-+ cache-sets = <1024>;
-+ cache-level = <2>;
-+ };
-+ };
-+
-+ gic: interrupt-controller@6000000 {
-+ compatible = "arm,gic-v3";
-+ reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
-+ <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
-+ // SGI_base)
-+ <0x0 0x0c0c0000 0 0x2000>, // GICC
-+ <0x0 0x0c0d0000 0 0x1000>, // GICH
-+ <0x0 0x0c0e0000 0 0x20000>; // GICV
-+ #interrupt-cells = <3>;
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+ interrupt-controller;
-+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-+
-+ its: gic-its@6020000 {
-+ compatible = "arm,gic-v3-its";
-+ msi-controller;
-+ reg = <0x0 0x6020000 0 0x20000>;
-+ };
-+ };
-+
-+ timer {
-+ compatible = "arm,armv8-timer";
-+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ pmu {
-+ compatible = "arm,cortex-a72-pmu";
-+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
-+ };
-+
-+ psci {
-+ compatible = "arm,psci-0.2";
-+ method = "smc";
-+ };
-+
-+ memory@80000000 {
-+ // DRAM space - 1, size : 2 GB DRAM
-+ device_type = "memory";
-+ reg = <0x00000000 0x80000000 0 0x80000000>;
-+ };
-+
-+ ddr1: memory-controller@1080000 {
-+ compatible = "fsl,qoriq-memory-controller";
-+ reg = <0x0 0x1080000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-+ little-endian;
-+ };
-+
-+ ddr2: memory-controller@1090000 {
-+ compatible = "fsl,qoriq-memory-controller";
-+ reg = <0x0 0x1090000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-+ little-endian;
-+ };
-+
-+ sysclk: sysclk {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <100000000>;
-+ clock-output-names = "sysclk";
-+ };
-+
-+ soc {
-+ compatible = "simple-bus";
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
-+
-+ crypto: crypto@8000000 {
-+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
-+ fsl,sec-era = <10>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x00 0x8000000 0x100000>;
-+ reg = <0x00 0x8000000 0x0 0x100000>;
-+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
-+ dma-coherent;
-+ status = "disabled";
-+
-+ sec_jr0: jr@10000 {
-+ compatible = "fsl,sec-v5.0-job-ring",
-+ "fsl,sec-v4.0-job-ring";
-+ reg = <0x10000 0x10000>;
-+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ sec_jr1: jr@20000 {
-+ compatible = "fsl,sec-v5.0-job-ring",
-+ "fsl,sec-v4.0-job-ring";
-+ reg = <0x20000 0x10000>;
-+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ sec_jr2: jr@30000 {
-+ compatible = "fsl,sec-v5.0-job-ring",
-+ "fsl,sec-v4.0-job-ring";
-+ reg = <0x30000 0x10000>;
-+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ sec_jr3: jr@40000 {
-+ compatible = "fsl,sec-v5.0-job-ring",
-+ "fsl,sec-v4.0-job-ring";
-+ reg = <0x40000 0x10000>;
-+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+ };
-+
-+ clockgen: clock-controller@1300000 {
-+ compatible = "fsl,lx2160a-clockgen";
-+ reg = <0 0x1300000 0 0xa0000>;
-+ #clock-cells = <2>;
-+ clocks = <&sysclk>;
-+ };
-+
-+ dcfg: syscon@1e00000 {
-+ compatible = "fsl,lx2160a-dcfg", "syscon";
-+ reg = <0x0 0x1e00000 0x0 0x10000>;
-+ little-endian;
-+ };
-+
-+ /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
-+ emdio1: mdio@8b96000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8b96000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ little-endian; /* force the driver in LE mode */
-+ status = "disabled";
-+ };
-+
-+ /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
-+ emdio2: mdio@8b97000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8b97000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ little-endian; /* force the driver in LE mode */
-+ status = "disabled";
-+ };
-+
-+ pcs_mdio1: mdio@0x8c07000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c07000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio2: mdio@0x8c0b000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c0b000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio3: mdio@0x8c0f000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c0f000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio4: mdio@0x8c13000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c13000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio5: mdio@0x8c17000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c17000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio6: mdio@0x8c1b000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c1b000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio7: mdio@0x8c1f000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c1f000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ pcs_mdio8: mdio@0x8c23000 {
-+ compatible = "fsl,fman-memac-mdio";
-+ reg = <0x0 0x8c23000 0x0 0x1000>;
-+ device_type = "mdio";
-+ little-endian;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ serdes1: serdes@1ea0000 {
-+ compatible = "fsl,serdes-28g";
-+ reg = <0x0 0x1ea0000 0 0x00002000>;
-+ little-endian;
-+ };
-+
-+ i2c0: i2c@2000000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2000000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 7>;
-+ scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ i2c1: i2c@2010000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2010000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 7>;
-+ status = "disabled";
-+ };
-+
-+ i2c2: i2c@2020000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2020000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 7>;
-+ status = "disabled";
-+ };
-+
-+ i2c3: i2c@2030000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2030000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 7>;
-+ status = "disabled";
-+ };
-+
-+ i2c4: i2c@2040000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2040000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 7>;
-+ scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ i2c5: i2c@2050000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2050000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 7>;
-+ status = "disabled";
-+ };
-+
-+ i2c6: i2c@2060000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2060000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 7>;
-+ status = "disabled";
-+ };
-+
-+ i2c7: i2c@2070000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2070000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 7>;
-+ status = "disabled";
-+ };
-+
-+ dspi0: spi@2100000 {
-+ compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2100000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 7>;
-+ clock-names = "dspi";
-+ spi-num-chipselects = <5>;
-+ bus-num = <0>;
-+ status = "disabled";
-+ };
-+
-+ dspi1: spi@2110000 {
-+ compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2110000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 7>;
-+ clock-names = "dspi";
-+ spi-num-chipselects = <5>;
-+ bus-num = <1>;
-+ status = "disabled";
-+ };
-+
-+ dspi2: spi@2120000 {
-+ compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2120000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 7>;
-+ clock-names = "dspi";
-+ spi-num-chipselects = <5>;
-+ bus-num = <2>;
-+ status = "disabled";
-+ };
-+
-+ esdhc0: esdhc@2140000 {
-+ compatible = "fsl,esdhc";
-+ reg = <0x0 0x2140000 0x0 0x10000>;
-+ interrupts = <0 28 0x4>; /* Level high type */
-+ clocks = <&clockgen 4 1>;
-+ voltage-ranges = <1800 1800 3300 3300>;
-+ sdhci,auto-cmd12;
-+ little-endian;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ esdhc1: esdhc@2150000 {
-+ compatible = "fsl,esdhc";
-+ reg = <0x0 0x2150000 0x0 0x10000>;
-+ interrupts = <0 63 0x4>; /* Level high type */
-+ clocks = <&clockgen 4 1>;
-+ voltage-ranges = <1800 1800 3300 3300>;
-+ sdhci,auto-cmd12;
-+ broken-cd;
-+ little-endian;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ uart0: serial@21c0000 {
-+ compatible = "arm,sbsa-uart","arm,pl011";
-+ reg = <0x0 0x21c0000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-+ current-speed = <115200>;
-+ status = "disabled";
-+ };
-+
-+ uart1: serial@21d0000 {
-+ compatible = "arm,sbsa-uart","arm,pl011";
-+ reg = <0x0 0x21d0000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-+ current-speed = <115200>;
-+ status = "disabled";
-+ };
-+
-+ uart2: serial@21e0000 {
-+ compatible = "arm,sbsa-uart","arm,pl011";
-+ reg = <0x0 0x21e0000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-+ current-speed = <115200>;
-+ status = "disabled";
-+ };
-+
-+ uart3: serial@21f0000 {
-+ compatible = "arm,sbsa-uart","arm,pl011";
-+ reg = <0x0 0x21f0000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-+ current-speed = <115200>;
-+ status = "disabled";
-+ };
-+
-+ gpio0: gpio@2300000 {
-+ compatible = "fsl,qoriq-gpio";
-+ reg = <0x0 0x2300000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-+ gpio-controller;
-+ little-endian;
-+ #gpio-cells = <2>;
-+ interrupt-controller;
-+ #interrupt-cells = <2>;
-+ };
-+
-+ gpio1: gpio@2310000 {
-+ compatible = "fsl,qoriq-gpio";
-+ reg = <0x0 0x2310000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-+ gpio-controller;
-+ little-endian;
-+ #gpio-cells = <2>;
-+ interrupt-controller;
-+ #interrupt-cells = <2>;
-+ };
-+
-+ gpio2: gpio@2320000 {
-+ compatible = "fsl,qoriq-gpio";
-+ reg = <0x0 0x2320000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-+ gpio-controller;
-+ little-endian;
-+ #gpio-cells = <2>;
-+ interrupt-controller;
-+ #interrupt-cells = <2>;
-+ };
-+
-+ gpio3: gpio@2330000 {
-+ compatible = "fsl,qoriq-gpio";
-+ reg = <0x0 0x2330000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-+ gpio-controller;
-+ little-endian;
-+ #gpio-cells = <2>;
-+ interrupt-controller;
-+ #interrupt-cells = <2>;
-+ };
-+
-+ watchdog@23a0000 {
-+ compatible = "arm,sbsa-gwdt";
-+ reg = <0x0 0x23a0000 0 0x1000>,
-+ <0x0 0x2390000 0 0x1000>;
-+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-+ timeout-sec = <30>;
-+ };
-+
-+ ftm0: ftm0@2800000 {
-+ compatible = "fsl,ftm-alarm", "fsl,lx2160a-ftm-alarm";
-+ reg = <0x0 0x2800000 0x0 0x10000>,
-+ <0x0 0x1e34050 0x0 0x4>;
-+ reg-names = "ftm", "FlexTimer1";
-+ interrupts = <0 44 0x4>;
-+ status = "okay";
-+ };
-+
-+ usb0: usb@3100000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x3100000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-+ dr_mode = "host";
-+ snps,quirk-frame-length-adjustment = <0x20>;
-+ snps,dis_rxdet_inp3_quirk;
-+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+ snps,host-vbus-glitches;
-+ status = "disabled";
-+ };
-+
-+ usb1: usb@3110000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x3110000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
-+ dr_mode = "host";
-+ snps,quirk-frame-length-adjustment = <0x20>;
-+ snps,dis_rxdet_inp3_quirk;
-+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+ snps,host-vbus-glitches;
-+ status = "disabled";
-+ };
-+
-+ smmu: iommu@5000000 {
-+ compatible = "arm,mmu-500";
-+ reg = <0 0x5000000 0 0x800000>;
-+ #iommu-cells = <1>;
-+ #global-interrupts = <14>;
-+ // global secure fault
-+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
-+ // combined secure
-+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
-+ // global non-secure fault
-+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
-+ // combined non-secure
-+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
-+ // performance counter interrupts 0-9
-+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
-+ // per context interrupt, 64 interrupts
-+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
-+ dma-coherent;
-+ };
-+
-+ fsl_mc: fsl-mc@80c000000 {
-+ compatible = "fsl,qoriq-mc";
-+ reg = <0x00000008 0x0c000000 0 0x40>,
-+ <0x00000000 0x08340000 0 0x40000>;
-+ msi-parent = <&its>;
-+ /* iommu-map property is fixed up by u-boot */
-+ iommu-map = <0 &smmu 0 0>;
-+ dma-coherent;
-+ #address-cells = <3>;
-+ #size-cells = <1>;
-+
-+ /*
-+ * Region type 0x0 - MC portals
-+ * Region type 0x1 - QBMAN portals
-+ */
-+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
-+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
-+
-+ /*
-+ * Define the maximum number of MACs present on the SoC.
-+ */
-+ dpmacs {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ dpmac1: dpmac@1 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0x1>;
-+ };
-+
-+ dpmac2: dpmac@2 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0x2>;
-+ };
-+
-+ dpmac3: dpmac@3 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0x3>;
-+ };
-+
-+ dpmac4: dpmac@4 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0x4>;
-+ };
-+
-+ dpmac5: dpmac@5 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0x5>;
-+ };
-+
-+ dpmac6: dpmac@6 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0x6>;
-+ };
-+
-+ dpmac7: dpmac@7 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0x7>;
-+ };
-+
-+ dpmac8: dpmac@8 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0x8>;
-+ };
-+
-+ dpmac9: dpmac@9 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0x9>;
-+ };
-+
-+ dpmac10: dpmac@a {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0xa>;
-+ };
-+
-+ dpmac11: dpmac@b {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0xb>;
-+ };
-+
-+ dpmac12: dpmac@c {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0xc>;
-+ };
-+
-+ dpmac13: dpmac@d {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0xd>;
-+ };
-+
-+ dpmac14: dpmac@e {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0xe>;
-+ };
-+
-+ dpmac15: dpmac@f {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0xf>;
-+ };
-+
-+ dpmac16: dpmac@10 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0x10>;
-+ };
-+
-+ dpmac17: dpmac@11 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0x11>;
-+ };
-+
-+ dpmac18: dpmac@12 {
-+ compatible = "fsl,qoriq-mc-dpmac";
-+ reg = <0x12>;
-+ };
-+ };
-+ };
-+
-+ fspi: flexspi@20c0000 {
-+ status = "disabled";
-+ compatible = "nxp,lx2160a-fspi";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x20c0000 0x0 0x10000>,
-+ <0x0 0x20000000 0x0 0x10000000>;
-+ reg-names = "FSPI", "FSPI-memory";
-+ interrupts = <0 25 0x4>; /* Level high type */
-+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+ clock-names = "fspi_en", "fspi";
-+ };
-+
-+ sata0: sata@3200000 {
-+ status = "disabled";
-+ compatible = "fsl,lx2160a-ahci";
-+ reg = <0x0 0x3200000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 3>;
-+ dma-coherent;
-+ };
-+
-+ sata1: sata@3210000 {
-+ status = "disabled";
-+ compatible = "fsl,lx2160a-ahci";
-+ reg = <0x0 0x3210000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 3>;
-+ dma-coherent;
-+ };
-+
-+ sata2: sata@3220000 {
-+ status = "disabled";
-+ compatible = "fsl,lx2160a-ahci";
-+ reg = <0x0 0x3220000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 3>;
-+ dma-coherent;
-+ };
-+
-+ sata3: sata@3230000 {
-+ status = "disabled";
-+ compatible = "fsl,lx2160a-ahci";
-+ reg = <0x0 0x3230000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 3>;
-+ dma-coherent;
-+ };
-+
-+ pcie@3400000 {
-+ compatible = "fsl,lx2160a-pcie";
-+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
-+ 0x80 0x00000000 0x0 0x00001000>; /* configuration space */
-+ reg-names = "csr_axi_slave", "config_axi_slave";
-+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
-+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
-+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-+ interrupt-names = "aer", "pme", "intr";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ dma-coherent;
-+ apio-wins = <8>;
-+ ppio-wins = <8>;
-+ bus-range = <0x0 0xff>;
-+ ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+ msi-parent = <&its>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ pcie_ep@3400000 {
-+ compatible = "fsl,lx2160a-pcie-ep";
-+ reg = <0x00 0x03400000 0x0 0x00100000
-+ 0x80 0x00000000 0x8 0x00000000>;
-+ reg-names = "regs", "addr_space";
-+ num-ob-windows = <256>;
-+ status = "disabled";
-+ };
-+
-+ pcie@3500000 {
-+ compatible = "fsl,lx2160a-pcie";
-+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
-+ 0x88 0x00000000 0x0 0x00001000>; /* configuration space */
-+ reg-names = "csr_axi_slave", "config_axi_slave";
-+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
-+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
-+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-+ interrupt-names = "aer", "pme", "intr";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ dma-coherent;
-+ apio-wins = <8>;
-+ ppio-wins = <8>;
-+ bus-range = <0x0 0xff>;
-+ ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+ msi-parent = <&its>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ pcie_ep@3500000 {
-+ compatible = "fsl,lx2160a-pcie-ep";
-+ reg = <0x00 0x03500000 0x0 0x00100000
-+ 0x88 0x00000000 0x8 0x00000000>;
-+ reg-names = "regs", "addr_space";
-+ num-ob-windows = <256>;
-+ status = "disabled";
-+ };
-+
-+ pcie@3600000 {
-+ compatible = "fsl,lx2160a-pcie";
-+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
-+ 0x90 0x00000000 0x0 0x00001000>; /* configuration space */
-+ reg-names = "csr_axi_slave", "config_axi_slave";
-+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
-+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
-+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-+ interrupt-names = "aer", "pme", "intr";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ dma-coherent;
-+ apio-wins = <8>;
-+ ppio-wins = <8>;
-+ bus-range = <0x0 0xff>;
-+ ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+ msi-parent = <&its>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ pcie_ep@3600000 {
-+ compatible = "fsl,lx2160a-pcie-ep";
-+ reg = <0x00 0x03600000 0x0 0x00100000
-+ 0x90 0x00000000 0x8 0x00000000>;
-+ reg-names = "regs", "addr_space";
-+ num-ob-windows = <256>;
-+ max-functions = <2>;
-+ status = "disabled";
-+ };
-+
-+ pcie@3700000 {
-+ compatible = "fsl,lx2160a-pcie";
-+ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
-+ 0x98 0x00000000 0x0 0x00001000>; /* configuration space */
-+ reg-names = "csr_axi_slave", "config_axi_slave";
-+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
-+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
-+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-+ interrupt-names = "aer", "pme", "intr";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ dma-coherent;
-+ apio-wins = <8>;
-+ ppio-wins = <8>;
-+ bus-range = <0x0 0xff>;
-+ ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+ msi-parent = <&its>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ pcie_ep@3700000 {
-+ compatible = "fsl,lx2160a-pcie-ep";
-+ reg = <0x00 0x03700000 0x0 0x00100000
-+ 0x98 0x00000000 0x8 0x00000000>;
-+ reg-names = "regs", "addr_space";
-+ num-ob-windows = <256>;
-+ status = "disabled";
-+ };
-+
-+ pcie@3800000 {
-+ compatible = "fsl,lx2160a-pcie";
-+ reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
-+ 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */
-+ reg-names = "csr_axi_slave", "config_axi_slave";
-+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
-+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
-+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-+ interrupt-names = "aer", "pme", "intr";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ dma-coherent;
-+ apio-wins = <8>;
-+ ppio-wins = <8>;
-+ bus-range = <0x0 0xff>;
-+ ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+ msi-parent = <&its>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ pcie_ep@3800000 {
-+ compatible = "fsl,lx2160a-pcie-ep";
-+ reg = <0x00 0x03800000 0x0 0x00100000
-+ 0xa0 0x00000000 0x8 0x00000000>;
-+ reg-names = "regs", "addr_space";
-+ num-ob-windows = <256>;
-+ max-functions = <2>;
-+ status = "disabled";
-+ };
-+
-+ pcie@3900000 {
-+ compatible = "fsl,lx2160a-pcie";
-+ reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
-+ 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */
-+ reg-names = "csr_axi_slave", "config_axi_slave";
-+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
-+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
-+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-+ interrupt-names = "aer", "pme", "intr";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ dma-coherent;
-+ apio-wins = <8>;
-+ ppio-wins = <8>;
-+ bus-range = <0x0 0xff>;
-+ ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+ msi-parent = <&its>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
-+ <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ pcie_ep@3900000 {
-+ compatible = "fsl,lx2160a-pcie-ep";
-+ reg = <0x00 0x03900000 0x0 0x00100000
-+ 0xa8 0x00000000 0x8 0x00000000>;
-+ reg-names = "regs", "addr_space";
-+ num-ob-windows = <256>;
-+ status = "disabled";
-+ };
-+
-+ };
-+
-+ firmware {
-+ optee {
-+ compatible = "linaro,optee-tz";
-+ method = "smc";
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi
-@@ -0,0 +1,99 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Device Tree Include file for Thermal Monitor Unit.
-+ *
-+ * Copyright 2018 NXP
-+ *
-+ * Tang Yuantian <andy.tang@nxp.com>
-+ *
-+ */
-+
-+&thermal_zones {
-+ thermal-zone0 {
-+ cooling-maps {
-+ map1 {
-+ trip = <&alert0>;
-+ cooling-device =
-+ <&cooling_map1 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone1 {
-+ cooling-maps {
-+ map1 {
-+ trip = <&alert1>;
-+ cooling-device =
-+ <&cooling_map1 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone2 {
-+ cooling-maps {
-+ map1 {
-+ trip = <&alert2>;
-+ cooling-device =
-+ <&cooling_map1 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone3 {
-+ cooling-maps {
-+ map1 {
-+ trip = <&alert3>;
-+ cooling-device =
-+ <&cooling_map1 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone4 {
-+ cooling-maps {
-+ map1 {
-+ trip = <&alert4>;
-+ cooling-device =
-+ <&cooling_map1 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone5 {
-+ cooling-maps {
-+ map1 {
-+ trip = <&alert5>;
-+ cooling-device =
-+ <&cooling_map1 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone6 {
-+ cooling-maps {
-+ map1 {
-+ trip = <&alert6>;
-+ cooling-device =
-+ <&cooling_map1 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone7 {
-+ cooling-maps {
-+ map1 {
-+ trip = <&alert7>;
-+ cooling-device =
-+ <&cooling_map1 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi
-@@ -0,0 +1,99 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Device Tree Include file for Thermal Monitor Unit.
-+ *
-+ * Copyright 2018 NXP
-+ *
-+ * Tang Yuantian <andy.tang@nxp.com>
-+ *
-+ */
-+
-+&thermal_zones {
-+ thermal-zone0 {
-+ cooling-maps {
-+ map2 {
-+ trip = <&alert0>;
-+ cooling-device =
-+ <&cooling_map2 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone1 {
-+ cooling-maps {
-+ map2 {
-+ trip = <&alert1>;
-+ cooling-device =
-+ <&cooling_map2 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone2 {
-+ cooling-maps {
-+ map2 {
-+ trip = <&alert2>;
-+ cooling-device =
-+ <&cooling_map2 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone3 {
-+ cooling-maps {
-+ map2 {
-+ trip = <&alert3>;
-+ cooling-device =
-+ <&cooling_map2 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone4 {
-+ cooling-maps {
-+ map2 {
-+ trip = <&alert4>;
-+ cooling-device =
-+ <&cooling_map2 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone5 {
-+ cooling-maps {
-+ map2 {
-+ trip = <&alert5>;
-+ cooling-device =
-+ <&cooling_map2 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone6 {
-+ cooling-maps {
-+ map2 {
-+ trip = <&alert6>;
-+ cooling-device =
-+ <&cooling_map2 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone7 {
-+ cooling-maps {
-+ map2 {
-+ trip = <&alert7>;
-+ cooling-device =
-+ <&cooling_map2 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi
-@@ -0,0 +1,99 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Device Tree Include file for Thermal Monitor Unit.
-+ *
-+ * Copyright 2018 NXP
-+ *
-+ * Tang Yuantian <andy.tang@nxp.com>
-+ *
-+ */
-+
-+&thermal_zones {
-+ thermal-zone0 {
-+ cooling-maps {
-+ map3 {
-+ trip = <&alert0>;
-+ cooling-device =
-+ <&cooling_map3 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone1 {
-+ cooling-maps {
-+ map3 {
-+ trip = <&alert1>;
-+ cooling-device =
-+ <&cooling_map3 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone2 {
-+ cooling-maps {
-+ map3 {
-+ trip = <&alert2>;
-+ cooling-device =
-+ <&cooling_map3 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone3 {
-+ cooling-maps {
-+ map3 {
-+ trip = <&alert3>;
-+ cooling-device =
-+ <&cooling_map3 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone4 {
-+ cooling-maps {
-+ map3 {
-+ trip = <&alert4>;
-+ cooling-device =
-+ <&cooling_map3 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone5 {
-+ cooling-maps {
-+ map3 {
-+ trip = <&alert5>;
-+ cooling-device =
-+ <&cooling_map3 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone6 {
-+ cooling-maps {
-+ map3 {
-+ trip = <&alert6>;
-+ cooling-device =
-+ <&cooling_map3 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone7 {
-+ cooling-maps {
-+ map3 {
-+ trip = <&alert7>;
-+ cooling-device =
-+ <&cooling_map3 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-tmu.dtsi
-@@ -0,0 +1,251 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Device Tree Include file for Thermal Monitor Unit.
-+ *
-+ * Copyright 2018 NXP
-+ *
-+ * Tang Yuantian <andy.tang@nxp.com>
-+ *
-+ */
-+
-+thermal_zones: thermal-zones {
-+ thermal_zone0: thermal-zone0 {
-+ polling-delay-passive = <1000>;
-+ polling-delay = <5000>;
-+ thermal-sensors = <&tmu 0>;
-+ status = "disabled";
-+
-+ trips {
-+ alert0: alert0 {
-+ temperature = <75000>;
-+ hysteresis = <2000>;
-+ type = "passive";
-+ };
-+
-+ crit0: crit0 {
-+ temperature = <85000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+ };
-+
-+ cooling-maps {
-+ map0 {
-+ trip = <&alert0>;
-+ cooling-device =
-+ <&cooling_map0 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone1 {
-+ polling-delay-passive = <1000>;
-+ polling-delay = <5000>;
-+ thermal-sensors = <&tmu 1>;
-+ status = "disabled";
-+
-+ trips {
-+ alert1: alert1 {
-+ temperature = <75000>;
-+ hysteresis = <2000>;
-+ type = "passive";
-+ };
-+
-+ crit1: crit1 {
-+ temperature = <85000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+ };
-+
-+ cooling-maps {
-+ map0 {
-+ trip = <&alert1>;
-+ cooling-device =
-+ <&cooling_map0 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone2 {
-+ polling-delay-passive = <1000>;
-+ polling-delay = <5000>;
-+ thermal-sensors = <&tmu 2>;
-+ status = "disabled";
-+
-+ trips {
-+ alert2: alert2 {
-+ temperature = <75000>;
-+ hysteresis = <2000>;
-+ type = "passive";
-+ };
-+
-+ crit2: crit2 {
-+ temperature = <85000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+ };
-+
-+ cooling-maps {
-+ map0 {
-+ trip = <&alert2>;
-+ cooling-device =
-+ <&cooling_map0 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone3 {
-+ polling-delay-passive = <1000>;
-+ polling-delay = <5000>;
-+ thermal-sensors = <&tmu 3>;
-+ status = "disabled";
-+
-+ trips {
-+ alert3: alert3 {
-+ temperature = <75000>;
-+ hysteresis = <2000>;
-+ type = "passive";
-+ };
-+
-+ crit3: crit3 {
-+ temperature = <85000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+ };
-+
-+ cooling-maps {
-+ map0 {
-+ trip = <&alert3>;
-+ cooling-device =
-+ <&cooling_map0 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone4 {
-+ polling-delay-passive = <1000>;
-+ polling-delay = <5000>;
-+ thermal-sensors = <&tmu 4>;
-+ status = "disabled";
-+
-+ trips {
-+ alert4: alert4 {
-+ temperature = <75000>;
-+ hysteresis = <2000>;
-+ type = "passive";
-+ };
-+
-+ crit4: crit4 {
-+ temperature = <85000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+ };
-+
-+ cooling-maps {
-+ map0 {
-+ trip = <&alert4>;
-+ cooling-device =
-+ <&cooling_map0 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone5 {
-+ polling-delay-passive = <1000>;
-+ polling-delay = <5000>;
-+ thermal-sensors = <&tmu 5>;
-+ status = "disabled";
-+
-+ trips {
-+ alert5: alert5 {
-+ temperature = <75000>;
-+ hysteresis = <2000>;
-+ type = "passive";
-+ };
-+
-+ crit5: crit5 {
-+ temperature = <85000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+ };
-+
-+ cooling-maps {
-+ map0 {
-+ trip = <&alert5>;
-+ cooling-device =
-+ <&cooling_map0 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone6 {
-+ polling-delay-passive = <1000>;
-+ polling-delay = <5000>;
-+ thermal-sensors = <&tmu 6>;
-+ status = "disabled";
-+
-+ trips {
-+ alert6: alert6 {
-+ temperature = <75000>;
-+ hysteresis = <2000>;
-+ type = "passive";
-+ };
-+
-+ crit6: crit6 {
-+ temperature = <85000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+ };
-+
-+ cooling-maps {
-+ map0 {
-+ trip = <&alert6>;
-+ cooling-device =
-+ <&cooling_map0 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ thermal-zone7 {
-+ polling-delay-passive = <1000>;
-+ polling-delay = <5000>;
-+ thermal-sensors = <&tmu 7>;
-+ status = "disabled";
-+
-+ trips {
-+ alert7: alert7 {
-+ temperature = <75000>;
-+ hysteresis = <2000>;
-+ type = "passive";
-+ };
-+
-+ crit7: crit7 {
-+ temperature = <85000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+ };
-+
-+ cooling-maps {
-+ map0 {
-+ trip = <&alert7>;
-+ cooling-device =
-+ <&cooling_map0 THERMAL_NO_LIMIT
-+ THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi
-@@ -0,0 +1,55 @@
-+/*
-+ * QorIQ BMan SDK Portals device tree nodes
-+ *
-+ * Copyright 2011-2016 Freescale Semiconductor Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-+ */
-+
-+&bportals {
-+ bman-portal@0 {
-+ cell-index = <0>;
-+ };
-+
-+ bman-portal@10000 {
-+ cell-index = <1>;
-+ };
-+
-+ bman-portal@20000 {
-+ cell-index = <2>;
-+ };
-+
-+ bman-portal@30000 {
-+ cell-index = <3>;
-+ };
-+
-+ bman-portal@40000 {
-+ cell-index = <4>;
-+ };
-+
-+ bman-portal@50000 {
-+ cell-index = <5>;
-+ };
-+
-+ bman-portal@60000 {
-+ cell-index = <6>;
-+ };
-+
-+ bman-portal@70000 {
-+ cell-index = <7>;
-+ };
-+
-+ bman-portal@80000 {
-+ cell-index = <8>;
-+ };
-+
-+ bman-portal@90000 {
-+ cell-index = <9>;
-+ };
-+
-+ bman-bpids@0 {
-+ compatible = "fsl,bpid-range";
-+ fsl,bpid-range = <32 32>;
-+ };
-+};
---- a/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi
-@@ -1,9 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
- * QorIQ BMan Portals device tree
- *
- * Copyright 2011-2016 Freescale Semiconductor Inc.
- *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- */
-
- &bportals {
-@@ -68,4 +68,10 @@
- reg = <0x80000 0x4000>, <0x4080000 0x4000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- };
-+
-+ bman-portal@90000 {
-+ compatible = "fsl,bman-portal";
-+ reg = <0x90000 0x4000>, <0x4090000 0x4000>;
-+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
-+ };
- };
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
-@@ -0,0 +1,97 @@
-+/*
-+ * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
-+ *
-+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of Freescale Semiconductor nor the
-+ * names of its contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
-+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
-+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+fsldpaa: fsl,dpaa {
-+ compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa";
-+ ethernet@0 {
-+ compatible = "fsl,dpa-ethernet";
-+ fsl,fman-mac = <&enet0>;
-+ dma-coherent;
-+ };
-+ ethernet@1 {
-+ compatible = "fsl,dpa-ethernet";
-+ fsl,fman-mac = <&enet1>;
-+ dma-coherent;
-+ };
-+ ethernet@2 {
-+ compatible = "fsl,dpa-ethernet";
-+ fsl,fman-mac = <&enet2>;
-+ dma-coherent;
-+ };
-+ ethernet@3 {
-+ compatible = "fsl,dpa-ethernet";
-+ fsl,fman-mac = <&enet3>;
-+ dma-coherent;
-+ };
-+ ethernet@4 {
-+ compatible = "fsl,dpa-ethernet";
-+ fsl,fman-mac = <&enet4>;
-+ dma-coherent;
-+ };
-+ ethernet@5 {
-+ compatible = "fsl,dpa-ethernet";
-+ fsl,fman-mac = <&enet5>;
-+ dma-coherent;
-+ };
-+ ethernet@8 {
-+ compatible = "fsl,dpa-ethernet";
-+ fsl,fman-mac = <&enet6>;
-+ dma-coherent;
-+ };
-+ ethernet@6 {
-+ compatible = "fsl,im-ethernet";
-+ fsl,fman-mac = <&enet2>;
-+ dma-coherent;
-+ fpmevt-sel = <0>;
-+ };
-+ ethernet@7 {
-+ compatible = "fsl,im-ethernet";
-+ fsl,fman-mac = <&enet3>;
-+ dma-coherent;
-+ fpmevt-sel = <1>;
-+ };
-+ ethernet@10 {
-+ compatible = "fsl,im-ethernet";
-+ fsl,fman-mac = <&enet4>;
-+ dma-coherent;
-+ fpmevt-sel = <2>;
-+ };
-+ ethernet@11 {
-+ compatible = "fsl,im-ethernet";
-+ fsl,fman-mac = <&enet5>;
-+ dma-coherent;
-+ fpmevt-sel = <3>;
-+ };
-+};
-+
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
-@@ -1,27 +1,28 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
- * QorIQ FMan v3 10g port #0 device tree
- *
- * Copyright 2012-2015 Freescale Semiconductor Inc.
- *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- */
-
- fman@1a00000 {
- fman0_rx_0x10: port@90000 {
- cell-index = <0x10>;
-- compatible = "fsl,fman-v3-port-rx";
-+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
- reg = <0x90000 0x1000>;
- fsl,fman-10g-port;
- };
-
- fman0_tx_0x30: port@b0000 {
- cell-index = <0x30>;
-- compatible = "fsl,fman-v3-port-tx";
-+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
- reg = <0xb0000 0x1000>;
- fsl,fman-10g-port;
-+ fsl,qman-channel-id = <0x800>;
- };
-
-- ethernet@f0000 {
-+ mac9: ethernet@f0000 {
- cell-index = <0x8>;
- compatible = "fsl,fman-memac";
- reg = <0xf0000 0x1000>;
-@@ -29,7 +30,7 @@ fman@1a00000 {
- pcsphy-handle = <&pcsphy6>;
- };
-
-- mdio@f1000 {
-+ mdio9: mdio@f1000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
-@@ -1,27 +1,28 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
- * QorIQ FMan v3 10g port #1 device tree
- *
- * Copyright 2012-2015 Freescale Semiconductor Inc.
- *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- */
-
- fman@1a00000 {
- fman0_rx_0x11: port@91000 {
- cell-index = <0x11>;
-- compatible = "fsl,fman-v3-port-rx";
-+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
- reg = <0x91000 0x1000>;
- fsl,fman-10g-port;
- };
-
- fman0_tx_0x31: port@b1000 {
- cell-index = <0x31>;
-- compatible = "fsl,fman-v3-port-tx";
-+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
- reg = <0xb1000 0x1000>;
- fsl,fman-10g-port;
-+ fsl,qman-channel-id = <0x801>;
- };
-
-- ethernet@f2000 {
-+ mac10: ethernet@f2000 {
- cell-index = <0x9>;
- compatible = "fsl,fman-memac";
- reg = <0xf2000 0x1000>;
-@@ -29,7 +30,7 @@ fman@1a00000 {
- pcsphy-handle = <&pcsphy7>;
- };
-
-- mdio@f3000 {
-+ mdio10: mdio@f3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
-@@ -1,22 +1,23 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
- * QorIQ FMan v3 1g port #0 device tree
- *
- * Copyright 2012-2015 Freescale Semiconductor Inc.
- *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- */
-
- fman@1a00000 {
- fman0_rx_0x08: port@88000 {
- cell-index = <0x8>;
-- compatible = "fsl,fman-v3-port-rx";
-+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
- reg = <0x88000 0x1000>;
- };
-
- fman0_tx_0x28: port@a8000 {
- cell-index = <0x28>;
-- compatible = "fsl,fman-v3-port-tx";
-+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
- reg = <0xa8000 0x1000>;
-+ fsl,qman-channel-id = <0x802>;
- };
-
- ethernet@e0000 {
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
-@@ -1,22 +1,23 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
- * QorIQ FMan v3 1g port #1 device tree
- *
- * Copyright 2012-2015 Freescale Semiconductor Inc.
- *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- */
-
- fman@1a00000 {
- fman0_rx_0x09: port@89000 {
- cell-index = <0x9>;
-- compatible = "fsl,fman-v3-port-rx";
-+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
- reg = <0x89000 0x1000>;
- };
-
- fman0_tx_0x29: port@a9000 {
- cell-index = <0x29>;
-- compatible = "fsl,fman-v3-port-tx";
-+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
- reg = <0xa9000 0x1000>;
-+ fsl,qman-channel-id = <0x803>;
- };
-
- ethernet@e2000 {
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
-@@ -1,22 +1,23 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
- * QorIQ FMan v3 1g port #2 device tree
- *
- * Copyright 2012-2015 Freescale Semiconductor Inc.
- *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- */
-
- fman@1a00000 {
- fman0_rx_0x0a: port@8a000 {
- cell-index = <0xa>;
-- compatible = "fsl,fman-v3-port-rx";
-+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
- reg = <0x8a000 0x1000>;
- };
-
- fman0_tx_0x2a: port@aa000 {
- cell-index = <0x2a>;
-- compatible = "fsl,fman-v3-port-tx";
-+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
- reg = <0xaa000 0x1000>;
-+ fsl,qman-channel-id = <0x804>;
- };
-
- ethernet@e4000 {
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
-@@ -1,22 +1,23 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
- * QorIQ FMan v3 1g port #3 device tree
- *
- * Copyright 2012-2015 Freescale Semiconductor Inc.
- *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- */
-
- fman@1a00000 {
- fman0_rx_0x0b: port@8b000 {
- cell-index = <0xb>;
-- compatible = "fsl,fman-v3-port-rx";
-+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
- reg = <0x8b000 0x1000>;
- };
-
- fman0_tx_0x2b: port@ab000 {
- cell-index = <0x2b>;
-- compatible = "fsl,fman-v3-port-tx";
-+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
- reg = <0xab000 0x1000>;
-+ fsl,qman-channel-id = <0x805>;
- };
-
- ethernet@e6000 {
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
-@@ -1,22 +1,23 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
- * QorIQ FMan v3 1g port #4 device tree
- *
- * Copyright 2012-2015 Freescale Semiconductor Inc.
- *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- */
-
- fman@1a00000 {
- fman0_rx_0x0c: port@8c000 {
- cell-index = <0xc>;
-- compatible = "fsl,fman-v3-port-rx";
-+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
- reg = <0x8c000 0x1000>;
- };
-
- fman0_tx_0x2c: port@ac000 {
- cell-index = <0x2c>;
-- compatible = "fsl,fman-v3-port-tx";
-+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
- reg = <0xac000 0x1000>;
-+ fsl,qman-channel-id = <0x806>;
- };
-
- ethernet@e8000 {
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
-@@ -1,22 +1,23 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
- * QorIQ FMan v3 1g port #5 device tree
- *
- * Copyright 2012-2015 Freescale Semiconductor Inc.
- *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- */
-
- fman@1a00000 {
- fman0_rx_0x0d: port@8d000 {
- cell-index = <0xd>;
-- compatible = "fsl,fman-v3-port-rx";
-+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
- reg = <0x8d000 0x1000>;
- };
-
- fman0_tx_0x2d: port@ad000 {
- cell-index = <0x2d>;
-- compatible = "fsl,fman-v3-port-tx";
-+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
- reg = <0xad000 0x1000>;
-+ fsl,qman-channel-id = <0x807>;
- };
-
- ethernet@ea000 {
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
-@@ -0,0 +1,47 @@
-+/*
-+ * QorIQ FMan v3 OH ports device tree
-+ *
-+ * Copyright 2012-2015 Freescale Semiconductor Inc.
-+ *
-+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-+ */
-+
-+fman@1a00000 {
-+
-+ fman0_oh1: port@82000 {
-+ cell-index = <0>;
-+ compatible = "fsl,fman-port-oh";
-+ reg = <0x82000 0x1000>;
-+ };
-+
-+ fman0_oh2: port@83000 {
-+ cell-index = <1>;
-+ compatible = "fsl,fman-port-oh";
-+ reg = <0x83000 0x1000>;
-+ };
-+
-+ fman0_oh3: port@84000 {
-+ cell-index = <2>;
-+ compatible = "fsl,fman-port-oh";
-+ reg = <0x84000 0x1000>;
-+ };
-+
-+ fman0_oh4: port@85000 {
-+ cell-index = <3>;
-+ compatible = "fsl,fman-port-oh";
-+ reg = <0x85000 0x1000>;
-+ };
-+
-+ fman0_oh5: port@86000 {
-+ cell-index = <4>;
-+ compatible = "fsl,fman-port-oh";
-+ reg = <0x86000 0x1000>;
-+ };
-+
-+ fman0_oh6: port@87000 {
-+ cell-index = <5>;
-+ compatible = "fsl,fman-port-oh";
-+ reg = <0x87000 0x1000>;
-+ };
-+
-+};
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
-@@ -1,9 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
- * QorIQ FMan v3 device tree
- *
- * Copyright 2012-2015 Freescale Semiconductor Inc.
- *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- */
-
- fman0: fman@1a00000 {
-@@ -11,53 +11,104 @@ fman0: fman@1a00000 {
- #size-cells = <1>;
- cell-index = <0>;
- compatible = "fsl,fman";
-- ranges = <0x0 0x0 0x1a00000 0x100000>;
-- reg = <0x0 0x1a00000 0x0 0x100000>;
-+ ranges = <0x0 0x0 0x1a00000 0xfe000>;
-+ reg = <0x0 0x1a00000 0x0 0xfe000>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 3 0>;
- clock-names = "fmanclk";
- fsl,qman-channel-range = <0x800 0x10>;
-+ ptimer-handle = <&ptp_timer0>;
-+
-+ cc {
-+ compatible = "fsl,fman-cc";
-+ };
-
- muram@0 {
- compatible = "fsl,fman-muram";
- reg = <0x0 0x60000>;
- };
-
-+ bmi@80000 {
-+ compatible = "fsl,fman-bmi";
-+ reg = <0x80000 0x400>;
-+ };
-+
-+ qmi@80400 {
-+ compatible = "fsl,fman-qmi";
-+ reg = <0x80400 0x400>;
-+ };
-+
- fman0_oh_0x2: port@82000 {
- cell-index = <0x2>;
- compatible = "fsl,fman-v3-port-oh";
- reg = <0x82000 0x1000>;
-+ fsl,qman-channel-id = <0x809>;
- };
-
- fman0_oh_0x3: port@83000 {
- cell-index = <0x3>;
- compatible = "fsl,fman-v3-port-oh";
- reg = <0x83000 0x1000>;
-+ fsl,qman-channel-id = <0x80a>;
- };
-
- fman0_oh_0x4: port@84000 {
- cell-index = <0x4>;
- compatible = "fsl,fman-v3-port-oh";
- reg = <0x84000 0x1000>;
-+ fsl,qman-channel-id = <0x80b>;
- };
-
- fman0_oh_0x5: port@85000 {
- cell-index = <0x5>;
- compatible = "fsl,fman-v3-port-oh";
- reg = <0x85000 0x1000>;
-+ fsl,qman-channel-id = <0x80c>;
- };
-
- fman0_oh_0x6: port@86000 {
- cell-index = <0x6>;
- compatible = "fsl,fman-v3-port-oh";
- reg = <0x86000 0x1000>;
-+ fsl,qman-channel-id = <0x80d>;
- };
-
- fman0_oh_0x7: port@87000 {
- cell-index = <0x7>;
- compatible = "fsl,fman-v3-port-oh";
- reg = <0x87000 0x1000>;
-+ fsl,qman-channel-id = <0x80e>;
-+ };
-+
-+ policer@c0000 {
-+ compatible = "fsl,fman-policer";
-+ reg = <0xc0000 0x1000>;
-+ };
-+
-+ keygen@c1000 {
-+ compatible = "fsl,fman-keygen";
-+ reg = <0xc1000 0x1000>;
-+ };
-+
-+ dma@c2000 {
-+ compatible = "fsl,fman-dma";
-+ reg = <0xc2000 0x1000>;
-+ };
-+
-+ fpm@c3000 {
-+ compatible = "fsl,fman-fpm";
-+ reg = <0xc3000 0x1000>;
-+ };
-+
-+ parser@c7000 {
-+ compatible = "fsl,fman-parser";
-+ reg = <0xc7000 0x1000>;
-+ };
-+
-+ vsps@dc000 {
-+ compatible = "fsl,fman-vsps";
-+ reg = <0xdc000 0x1000>;
- };
-
- mdio0: mdio@fc000 {
-@@ -73,9 +124,11 @@ fman0: fman@1a00000 {
- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
- reg = <0xfd000 0x1000>;
- };
-+};
-
-- ptp_timer0: ptp-timer@fe000 {
-- compatible = "fsl,fman-ptp-timer";
-- reg = <0xfe000 0x1000>;
-- };
-+ptp_timer0: ptp-timer@1afe000 {
-+ compatible = "fsl,fman-ptp-timer";
-+ reg = <0x0 0x1afe000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 3 0>;
- };
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi
-@@ -0,0 +1,38 @@
-+/*
-+ * QorIQ QMan SDK Portals device tree nodes
-+ *
-+ * Copyright 2011-2016 Freescale Semiconductor Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-+ */
-+
-+&qportals {
-+ qman-fqids@0 {
-+ compatible = "fsl,fqid-range";
-+ fsl,fqid-range = <256 256>;
-+ };
-+
-+ qman-fqids@1 {
-+ compatible = "fsl,fqid-range";
-+ fsl,fqid-range = <32768 32768>;
-+ };
-+
-+ qman-pools@0 {
-+ compatible = "fsl,pool-channel-range";
-+ fsl,pool-channel-range = <0x401 0xf>;
-+ };
-+
-+ qman-cgrids@0 {
-+ compatible = "fsl,cgrid-range";
-+ fsl,cgrid-range = <0 256>;
-+ };
-+
-+ qman-ceetm@0 {
-+ compatible = "fsl,qman-ceetm";
-+ fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
-+ fsl,ceetm-sp-range = <0 16>;
-+ fsl,ceetm-lni-range = <0 8>;
-+ fsl,ceetm-channel-range = <0 32>;
-+ };
-+};
---- a/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi
-@@ -1,9 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
- * QorIQ QMan Portals device tree
- *
- * Copyright 2011-2016 Freescale Semiconductor Inc.
- *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- */
-
- &qportals {
-@@ -77,4 +77,11 @@
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- cell-index = <8>;
- };
-+
-+ qportal9: qman-portal@90000 {
-+ compatible = "fsl,qman-portal";
-+ reg = <0x90000 0x4000>, <0x4090000 0x4000>;
-+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
-+ cell-index = <9>;
-+ };
- };
---- a/arch/arm64/boot/dts/freescale/traverse-ls1043s.dts
-+++ b/arch/arm64/boot/dts/freescale/traverse-ls1043s.dts
-@@ -330,3 +330,32 @@
- &sata {
- status = "disabled";
- };
-+
-+/* Additions for Layerscape SDK (4.4/4.9) Kernel only
-+ * These kernels need additional setup for FMan/QMan DMA shared memory
-+ */
-+
-+#include "qoriq-qman-portals-sdk.dtsi"
-+#include "qoriq-bman-portals-sdk.dtsi"
-+
-+&bman_fbpr {
-+ compatible = "fsl,bman-fbpr";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_fqd {
-+ compatible = "fsl,qman-fqd";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_pfdr {
-+ compatible = "fsl,qman-pfdr";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+
-+&soc {
-+#include "qoriq-dpaa-eth.dtsi"
-+#include "qoriq-fman3-0-6oh.dtsi"
-+};
-+
-+&fman0 {
-+ compatible = "fsl,fman", "simple-bus";
-+};
---- a/arch/arm64/boot/dts/freescale/traverse-ls1043v.dts
-+++ b/arch/arm64/boot/dts/freescale/traverse-ls1043v.dts
-@@ -251,3 +251,32 @@
- &sata {
- status = "disabled";
- };
-+
-+/* Additions for Layerscape SDK (4.4/4.9) Kernel only
-+ * These kernels need additional setup for FMan/QMan DMA shared memory
-+ */
-+
-+#include "qoriq-qman-portals-sdk.dtsi"
-+#include "qoriq-bman-portals-sdk.dtsi"
-+
-+&bman_fbpr {
-+ compatible = "fsl,bman-fbpr";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_fqd {
-+ compatible = "fsl,qman-fqd";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_pfdr {
-+ compatible = "fsl,qman-pfdr";
-+ alloc-ranges = <0 0 0x10000 0>;
-+};
-+
-+&soc {
-+#include "qoriq-dpaa-eth.dtsi"
-+#include "qoriq-fman3-0-6oh.dtsi"
-+};
-+
-+&fman0 {
-+ compatible = "fsl,fman", "simple-bus";
-+};
projects / openwrt / staging / stintel.git / blobdiff