uboot-hifiveu: add bootloader package for HiFive Ux40 boards

[openwrt/staging/wigyori.git] / package / boot / uboot-hifiveu / patches / 0010-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch

diff --git a/package/boot/uboot-hifiveu/patches/0010-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch b/package/boot/uboot-hifiveu/patches/0010-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch
new file mode 100644 (file)
index 0000000..53eae73
--- /dev/null
+++ b/package/boot/uboot-hifiveu/patches/0010-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch
@@ -0,0 +1,89 @@
+From ac71430a203ae7073d92c5f3026f0863e6b7e22b Mon Sep 17 00:00:00 2001
+From: Vincent Chen <vincent.chen@sifive.com>
+Date: Fri, 26 Mar 2021 13:58:59 +0800
+Subject: [PATCH 10/16] board: sifive: spl: Initialized the PWM setting in the
+ SPL stage
+
+LEDs and multiple fans can be controlled by SPL. This patch ensures
+that all fans have been enabled in the SPL stage. In addition, the
+LED's color will be set to yellow.
+---
+ board/sifive/unmatched/spl.c       |  2 ++
+ board/sifive/unmatched/unmatched.c | 48 ++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 50 insertions(+)
+
+diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
+index d566327..3c3b22d 100644
+--- a/board/sifive/unmatched/spl.c
++++ b/board/sifive/unmatched/spl.c
+@@ -89,6 +89,8 @@ int spl_board_init_f(void)
+               goto end;
+       }
+ 
++      pwm_device_init();
++
+       ret = spl_gemgxl_init();
+       if (ret) {
+               debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
+diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c
+index 6d60559..9924da9 100644
+--- a/board/sifive/unmatched/unmatched.c
++++ b/board/sifive/unmatched/unmatched.c
+@@ -9,6 +9,54 @@
+ #include <common.h>
+ #include <dm.h>
+ #include <asm/arch/cache.h>
++#include <linux/io.h>
++#include <asm/arch/eeprom.h>
++
++struct pwm_sifive_regs {
++      unsigned int cfg;       /* PWM configuration register */
++      unsigned int pad0;      /* Reserved */
++      unsigned int cnt;       /* PWM count register */
++      unsigned int pad1;      /* Reserved */
++      unsigned int pwms;      /* Scaled PWM count register */
++      unsigned int pad2;      /* Reserved */
++      unsigned int pad3;      /* Reserved */
++      unsigned int pad4;      /* Reserved */
++      unsigned int cmp0;      /* PWM 0 compare register */
++      unsigned int cmp1;      /* PWM 1 compare register */
++      unsigned int cmp2;      /* PWM 2 compare register */
++      unsigned int cmp3;      /* PWM 3 compare register */
++};
++
++#define PWM0_BASE             0x10020000
++#define PWM1_BASE             0x10021000
++#define PWM_CFG_INIT          0x1000
++#define PWM_CMP_ENABLE_VAL    0x0
++#define PWM_CMP_DISABLE_VAL   0xffff
++
++void pwm_device_init(void)
++{
++      struct pwm_sifive_regs *pwm0, *pwm1;
++      pwm0 = (struct pwm_sifive_regs *)PWM0_BASE;
++      pwm1 = (struct pwm_sifive_regs *)PWM1_BASE;
++      writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp0);
++      /* Set the 3-color PWM LEDs to yellow in SPL */
++      writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp1);
++      writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp2);
++      writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
++      writel(PWM_CFG_INIT, (void *)&pwm0->cfg);
++
++      writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
++      /* Turn on all the fans, (J21), (J23) and (J24), on the unmatched board */
++      /* The SoC fan(J21) on the rev3 board cannot be controled by PWM_COMP0,
++         so here sets the initial value of PWM_COMP0 as DISABLE */
++      if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3)
++              writel(PWM_CMP_DISABLE_VAL, (void *)&pwm1->cmp1);
++      else
++              writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp1);
++      writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp2);
++      writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp3);
++      writel(PWM_CFG_INIT, (void *)&pwm1->cfg);
++}
+ 
+ int board_init(void)
+ {
+-- 
+2.7.4
+