lantiq: xrx200: switch the subtarget to the mainline DSA driver

[openwrt/staging/wigyori.git] / target / linux / lantiq / files / arch / mips / boot / dts / lantiq / vr9_tplink_vr200.dtsi

diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi
index aa76f66267f7d215f9c8a5154fc55f82908317e0..d3d89078602a32fbe78b958b82450899b04848dc 100644 (file)
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi
@@ -100,66 +100,7 @@
 };
 
 &eth0 {
-       pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>;
-       pinctrl-names = "default";
-
-       lan: interface@0 {
-               compatible = "lantiq,xrx200-pdi";
-               #address-cells = <1>;
-               #size-cells = <0>;
-               reg = <0>;
-               mtd-mac-address = <&romfile 0xf100>;
-               lantiq,switch;
-
-               ethernet@0 {
-                       compatible = "lantiq,xrx200-pdi-port";
-                       reg = <0>;
-                       phy-mode = "rgmii";
-                       phy-handle = <&phy0>;
-                       // gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
-               };
-               ethernet@2 {
-                       compatible = "lantiq,xrx200-pdi-port";
-                       reg = <2>;
-                       phy-mode = "gmii";
-                       phy-handle = <&phy11>;
-               };
-               ethernet@4 {
-                       compatible = "lantiq,xrx200-pdi-port";
-                       reg = <4>;
-                       phy-mode = "gmii";
-                       phy-handle = <&phy13>;
-               };
-               ethernet@5 {
-                       compatible = "lantiq,xrx200-pdi-port";
-                       reg = <5>;
-                       phy-mode = "rgmii";
-                       phy-handle = <&phy5>;
-               };
-       };
-
-       mdio {
-               #address-cells = <1>;
-               #size-cells = <0>;
-               compatible = "lantiq,xrx200-mdio";
-
-               phy0: ethernet-phy@0 {
-                       reg = <0x0>;
-                       compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
-               };
-               phy5: ethernet-phy@5 {
-                       reg = <0x5>;
-                       compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
-               };
-               phy11: ethernet-phy@11 {
-                       reg = <0x11>;
-                       compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
-               };
-               phy13: ethernet-phy@13 {
-                       reg = <0x13>;
-                       compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
-               };
-       };
+       mtd-mac-address = <&romfile 0xf100>;
 };
 
 &gphy0 {
@@ -189,6 +130,54 @@
        };
 };
 
+&gswip {
+       pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>;
+       pinctrl-names = "default";
+};
+
+&gswip_mdio {
+       phy0: ethernet-phy@0 {
+               reg = <0x0>;
+               // reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
+       };
+       phy5: ethernet-phy@5 {
+               reg = <0x5>;
+       };
+       phy11: ethernet-phy@11 {
+               reg = <0x11>;
+       };
+       phy13: ethernet-phy@13 {
+               reg = <0x13>;
+       };
+};
+
+&gswip_ports {
+       port@0 {
+               reg = <0>;
+               label = "lan3";
+               phy-mode = "rgmii";
+               phy-handle = <&phy0>;
+       };
+       port@2 {
+               reg = <2>;
+               label = "lan2";
+               phy-mode = "internal";
+               phy-handle = <&phy11>;
+       };
+       port@4 {
+               reg = <4>;
+               label = "lan1";
+               phy-mode = "internal";
+               phy-handle = <&phy13>;
+       };
+       port@5 {
+               reg = <5>;
+               label = "lan4";
+               phy-mode = "rgmii";
+               phy-handle = <&phy5>;
+       };
+};
+
 &pcie0 {
        pcie@0 {
                reg = <0 0 0 0 0>;