layerscape: add patches-5.4

[openwrt/staging/wigyori.git] / target / linux / layerscape / patches-5.4 / 302-dts-0003-arm64-dts-ls1012a-Add-LS1012A-2G5RDB-board-support.patch

diff --git a/target/linux/layerscape/patches-5.4/302-dts-0003-arm64-dts-ls1012a-Add-LS1012A-2G5RDB-board-support.patch b/target/linux/layerscape/patches-5.4/302-dts-0003-arm64-dts-ls1012a-Add-LS1012A-2G5RDB-board-support.patch
new file mode 100644 (file)
index 0000000..56501c3
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/302-dts-0003-arm64-dts-ls1012a-Add-LS1012A-2G5RDB-board-support.patch
@@ -0,0 +1,114 @@
+From 3261cabf5607c9f434faa4930ab5c2b0150579c4 Mon Sep 17 00:00:00 2001
+From: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
+Date: Wed, 29 Nov 2017 06:23:14 +0530
+Subject: [PATCH] arm64: dts: ls1012a: Add LS1012A-2G5RDB board support
+
+LS1012A-2G5RDB is a different design from LS1012ARDB,
+but has some common SoC features. Key feature on this
+board is 2.5Gbps SGMII.
+
+Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
+Signed-off-by: Li Yang <leoyang.li@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/Makefile             |  1 +
+ .../boot/dts/freescale/fsl-ls1012a-2g5rdb.dts      | 86 ++++++++++++++++++++++
+ 2 files changed, 87 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
+
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -1,4 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
+@@ -0,0 +1,86 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree file for NXP LS1012A 2G5RDB Board.
++ *
++ * Copyright 2017 NXP
++ *
++ * Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
++ */
++/dts-v1/;
++
++#include "fsl-ls1012a.dtsi"
++
++/ {
++      model = "LS1012A 2G5RDB Board";
++      compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
++
++      aliases {
++              ethernet0 = &pfe_mac0;
++              ethernet1 = &pfe_mac1;
++      };
++};
++
++&duart0 {
++      status = "okay";
++};
++
++&i2c0 {
++      status = "okay";
++};
++
++&qspi {
++      num-cs = <2>;
++      bus-num = <0>;
++      status = "okay";
++
++      qflash0: s25fs512s@0 {
++              compatible = "spansion,m25p80";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              spi-max-frequency = <20000000>;
++              m25p,fast-read;
++              reg = <0>;
++      };
++};
++
++&sata {
++      status = "okay";
++};
++
++&pfe {
++      status = "okay";
++      #address-cells = <1>;
++      #size-cells = <0>;
++
++      ethernet@0 {
++              compatible = "fsl,pfe-gemac-port";
++              #address-cells = <1>;
++              #size-cells = <0>;
++              reg = <0x0>;    /* GEM_ID */
++              fsl,gemac-bus-id = <0x0>;       /* BUS_ID */
++              fsl,gemac-phy-id = <0x1>;       /* PHY_ID */
++              fsl,mdio-mux-val = <0x0>;
++              phy-mode = "sgmii-2500";
++              fsl,pfe-phy-if-flags = <0x0>;
++
++              mdio@0 {
++                      reg = <0x1>; /* enabled/disabled */
++              };
++      };
++
++      ethernet@1 {
++              compatible = "fsl,pfe-gemac-port";
++              #address-cells = <1>;
++              #size-cells = <0>;
++              reg = <0x1>;    /* GEM_ID */
++              fsl,gemac-bus-id = < 0x0>;      /* BUS_ID */
++              fsl,gemac-phy-id = < 0x2>;      /* PHY_ID */
++              fsl,mdio-mux-val = <0x0>;
++              phy-mode = "sgmii-2500";
++              fsl,pfe-phy-if-flags = <0x0>;
++
++              mdio@0 {
++                      reg = <0x0>; /* enabled/disabled */
++              };
++      };
++};