layerscape: add patches-5.4

[openwrt/staging/wigyori.git] / target / linux / layerscape / patches-5.4 / 302-dts-0005-arm64-dts-ls2081ardb-Add-DTS-support-for-NXP-LS2081A.patch

diff --git a/target/linux/layerscape/patches-5.4/302-dts-0005-arm64-dts-ls2081ardb-Add-DTS-support-for-NXP-LS2081A.patch b/target/linux/layerscape/patches-5.4/302-dts-0005-arm64-dts-ls2081ardb-Add-DTS-support-for-NXP-LS2081A.patch
new file mode 100644 (file)
index 0000000..3894172
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/302-dts-0005-arm64-dts-ls2081ardb-Add-DTS-support-for-NXP-LS2081A.patch
@@ -0,0 +1,164 @@
+From 5508bc9764760ca32990d5f7fa494be78e711ff6 Mon Sep 17 00:00:00 2001
+From: Li Yang <leoyang.li@nxp.com>
+Date: Fri, 5 Oct 2018 18:22:46 -0500
+Subject: [PATCH] arm64: dts: ls2081ardb: Add DTS support for NXP LS2081ARDB
+
+This patch add support for NXP LS2081ARDB board which has
+LS2081A SoC.
+
+LS2081A SoC is 40-pin derivative of LS2088A SoC
+So, from functional perspective both are same.
+Hence,ls2088a SoC dtsi files are included from ls2081ARDB dts
+
+Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
+Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
+Signed-off-by: Tao Yang <b31903@freescale.com>
+Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
+Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Signed-off-by: Li Yang <leoyang.li@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/Makefile            |   1 +
+ arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts | 127 ++++++++++++++++++++++
+ 2 files changed, 128 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
+
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
+@@ -0,0 +1,127 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree file for NXP LS2081A RDB Board.
++ *
++ * Copyright 2017 NXP
++ *
++ * Priyanka Jain <priyanka.jain@nxp.com>
++ *
++ */
++
++/dts-v1/;
++
++#include "fsl-ls2088a.dtsi"
++
++/ {
++      model = "NXP Layerscape 2081A RDB Board";
++      compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
++
++      aliases {
++              serial0 = &serial0;
++              serial1 = &serial1;
++      };
++
++      chosen {
++              stdout-path = "serial1:115200n8";
++      };
++};
++
++&esdhc {
++      status = "okay";
++};
++
++&ifc {
++      status = "disabled";
++};
++
++&i2c0 {
++      status = "okay";
++      pca9547@75 {
++              compatible = "nxp,pca9547";
++              reg = <0x75>;
++              #address-cells = <1>;
++              #size-cells = <0>;
++              i2c@1 {
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x01>;
++                      rtc@51 {
++                              compatible = "nxp,pcf2129";
++                              reg = <0x51>;
++                      };
++              };
++
++              i2c@2 {
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x02>;
++
++                      ina220@40 {
++                              compatible = "ti,ina220";
++                              reg = <0x40>;
++                              shunt-resistor = <500>;
++                      };
++              };
++
++              i2c@3 {
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x3>;
++
++                      adt7481@4c {
++                              compatible = "adi,adt7461";
++                              reg = <0x4c>;
++                      };
++              };
++      };
++};
++
++&dspi {
++      status = "okay";
++      dflash0: n25q512a@0 {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "st,m25p80";
++              spi-max-frequency = <3000000>;
++              reg = <0>;
++      };
++};
++
++&qspi {
++      status = "okay";
++      fsl,qspi-has-second-chip;
++      flash0: s25fs512s@0 {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "spansion,m25p80";
++              spi-rx-bus-width = <4>;
++              spi-tx-bus-width = <4>;
++              spi-max-frequency = <20000000>;
++              reg = <0>;
++      };
++      flash1: s25fs512s@1 {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              spi-rx-bus-width = <4>;
++              spi-tx-bus-width = <4>;
++              compatible = "spansion,m25p80";
++              spi-max-frequency = <20000000>;
++              reg = <1>;
++      };
++};
++
++&sata0 {
++      status = "okay";
++};
++
++&sata1 {
++      status = "okay";
++};
++
++&usb0 {
++      status = "okay";
++};
++
++&usb1 {
++      status = "okay";
++};