layerscape: add patches-5.4

[openwrt/staging/wigyori.git] / target / linux / layerscape / patches-5.4 / 302-dts-0096-arm64-dts-fsl-ls1028a-Disable-eno3-and-make-swp5-the.patch

diff --git a/target/linux/layerscape/patches-5.4/302-dts-0096-arm64-dts-fsl-ls1028a-Disable-eno3-and-make-swp5-the.patch b/target/linux/layerscape/patches-5.4/302-dts-0096-arm64-dts-fsl-ls1028a-Disable-eno3-and-make-swp5-the.patch
new file mode 100644 (file)
index 0000000..4a3eaaa
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/302-dts-0096-arm64-dts-fsl-ls1028a-Disable-eno3-and-make-swp5-the.patch
@@ -0,0 +1,63 @@
+From 9344f58d60a0a53ec39e7c5d75021843e859970f Mon Sep 17 00:00:00 2001
+From: Vladimir Oltean <vladimir.oltean@nxp.com>
+Date: Fri, 29 Nov 2019 03:18:32 +0200
+Subject: [PATCH] arm64: dts: fsl: ls1028a: Disable eno3 and make swp5 the
+ Felix CPU port
+
+This patch returns to the switch port setup from BSP 0.2, where the
+switch only had a single Ethernet connection to the CPU, via a tagging
+interface. Choose eno2 for this purpose, as it has higher bandwidth and
+also supports TSN offloads.
+
+The reason is that the switch is not able to do DSA tags on 2 CPU ports
+at the same time, and it is confusing to have so many ports with no
+clear indication which should be used for what (a "data" port and a
+"control" port).
+
+We don't revert to the BSP 0.2 RCW configuration, however. The ENETC
+port 3 is still enabled in the RCW, however it is not probed by Linux by
+default, since the large majority of use cases will not need it. For
+those that do (like originating 802.1CB traffic from the CPU), it can be
+enabled back by simply reverting this device tree change.
+
+Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+@@ -755,7 +755,7 @@
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+-                      ethernet@0,2 {
++                      enetc_port2: ethernet@0,2 {
+                               compatible = "fsl,enetc";
+                               reg = <0x000200 0 0 0 0>;
+                               fixed-link {
+@@ -794,6 +794,7 @@
+                                       /* internal to-cpu ports */
+                                       port@4 {
+                                               reg = <4>;
++                                              ethernet = <&enetc_port2>;
+                                               phy-mode = "gmii";
+ 
+                                               fixed-link {
+@@ -803,7 +804,6 @@
+                                       };
+                                       port@5 {
+                                               reg = <5>;
+-                                              ethernet = <&enetc_port3>;
+                                               phy-mode = "gmii";
+ 
+                                               fixed-link {
+@@ -816,6 +816,8 @@
+                       enetc_port3: ethernet@0,6 {
+                               compatible = "fsl,enetc";
+                               reg = <0x000600 0 0 0 0>;
++                              status = "disabled";
++
+                               fixed-link {
+                                       speed = <1000>;
+                                       full-duplex;