layerscape: add patches-5.4

[openwrt/staging/wigyori.git] / target / linux / layerscape / patches-5.4 / 701-net-0324-staging-fsl_ppfe-eth-Disable-termination-of-CRC-fwd.patch

diff --git a/target/linux/layerscape/patches-5.4/701-net-0324-staging-fsl_ppfe-eth-Disable-termination-of-CRC-fwd.patch b/target/linux/layerscape/patches-5.4/701-net-0324-staging-fsl_ppfe-eth-Disable-termination-of-CRC-fwd.patch
new file mode 100644 (file)
index 0000000..3d9870d
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/701-net-0324-staging-fsl_ppfe-eth-Disable-termination-of-CRC-fwd.patch
@@ -0,0 +1,34 @@
+From 6d7e10038aba81d7273f72f36db64c71ae7f8f69 Mon Sep 17 00:00:00 2001
+From: Nagesh Koneti <koneti.nagesh@nxp.com>
+Date: Wed, 25 Sep 2019 12:01:19 +0530
+Subject: [PATCH] staging: fsl_ppfe/eth: Disable termination of CRC fwd.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+LS1012A MAC PCS block has an erratum that is seen with specific PHY AR803x.
+The issue is triggered by the (spec-compliant) operation of the AR803x PHY
+on the LS1012A-FRWY board.Due to this, good FCS packet is reported as error
+packet by MAC, so for these error packets FCS should be validated and
+discard only real error packets in PFE Rx packet path.
+
+Signed-off-by: Nagesh Koneti <koneti.nagesh@nxp.com>
+Signed-off-by: Nagesh Koneti <“koneti.nagesh@nxp.com”>
+---
+ drivers/staging/fsl_ppfe/pfe_hal.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/staging/fsl_ppfe/pfe_hal.c
++++ b/drivers/staging/fsl_ppfe/pfe_hal.c
+@@ -860,8 +860,9 @@ void gemac_set_mode(void *base, int mode
+       /*Remove loopbank*/
+       val &= ~EMAC_RCNTRL_LOOP;
+ 
+-      /* Enable flow control and MII mode and terminate received CRC */
+-      val |= (EMAC_RCNTRL_FCE | EMAC_RCNTRL_MII_MODE | EMAC_RCNTRL_CRC_FWD);
++      /* Enable flow control and MII mode.PFE firmware always expects
++       CRC should be forwarded by MAC to validate CRC in software.*/
++      val |= (EMAC_RCNTRL_FCE | EMAC_RCNTRL_MII_MODE);
+ 
+       writel(val, base + EMAC_RCNTRL_REG);
+ }