layerscape: add patches-5.4

[openwrt/staging/wigyori.git] / target / linux / layerscape / patches-5.4 / 802-can-0011-can-flexcan-rename-struct-flexcan_priv-reg_imask-1-2.patch

diff --git a/target/linux/layerscape/patches-5.4/802-can-0011-can-flexcan-rename-struct-flexcan_priv-reg_imask-1-2.patch b/target/linux/layerscape/patches-5.4/802-can-0011-can-flexcan-rename-struct-flexcan_priv-reg_imask-1-2.patch
new file mode 100644 (file)
index 0000000..12030a2
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/802-can-0011-can-flexcan-rename-struct-flexcan_priv-reg_imask-1-2.patch
@@ -0,0 +1,101 @@
+From a1126887f068def0bc11f5260e55e25b9c03e3ea Mon Sep 17 00:00:00 2001
+From: Marc Kleine-Budde <mkl@pengutronix.de>
+Date: Fri, 1 Mar 2019 09:18:54 +0100
+Subject: [PATCH] can: flexcan: rename struct
+ flexcan_priv::reg_imask{1,2}_default to rx_mask{1,2}
+
+The flexcan IP core has up to 64 mailboxes, each one has a corresponding
+interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
+imask1 or imask2 registers.
+
+In the timestamp (i.e. non FIFO) mode the driver needs to mask out all
+non RX interrupt sources and uses the precomputed values
+reg_imask1_default and reg_imask2_default of struct flexcan_priv for
+this.
+
+However in the current driver the reg_imask{1,2}_default cannot be used
+directly to get the pending RX interrupts. The TX interrupt is part of
+these variables, so it needs to be masked out, too.
+
+This is a preparation patch to clean up calculation of the pending RX
+interrupts, it only renames the variables from
+
+    reg_imask{1,2}_default
+
+to
+
+    rx_mask{1,2}
+
+To better reflect their meaning after the complete conversion. This
+change is done with the following sed command:
+
+    sed -i -e "s/reg_imask\(1\|2\)_default/rx_mask\1/" drivers/net/can/flexcan.c
+
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+---
+ drivers/net/can/flexcan.c | 22 +++++++++++-----------
+ 1 file changed, 11 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/can/flexcan.c
++++ b/drivers/net/can/flexcan.c
+@@ -278,8 +278,8 @@ struct flexcan_priv {
+       u8 clk_src;     /* clock source of CAN Protocol Engine */
+ 
+       u32 reg_ctrl_default;
+-      u32 reg_imask1_default;
+-      u32 reg_imask2_default;
++      u32 rx_mask1;
++      u32 rx_mask2;
+ 
+       struct clk *clk_ipg;
+       struct clk *clk_per;
+@@ -879,9 +879,9 @@ static inline u64 flexcan_read_reg_iflag
+       struct flexcan_regs __iomem *regs = priv->regs;
+       u32 iflag1, iflag2;
+ 
+-      iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default &
++      iflag2 = priv->read(&regs->iflag2) & priv->rx_mask2 &
+               ~FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
+-      iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default;
++      iflag1 = priv->read(&regs->iflag1) & priv->rx_mask1;
+ 
+       return (u64)iflag2 << 32 | iflag1;
+ }
+@@ -1228,8 +1228,8 @@ static int flexcan_chip_start(struct net
+       /* enable interrupts atomically */
+       disable_irq(dev->irq);
+       priv->write(priv->reg_ctrl_default, &regs->ctrl);
+-      priv->write(priv->reg_imask1_default, &regs->imask1);
+-      priv->write(priv->reg_imask2_default, &regs->imask2);
++      priv->write(priv->rx_mask1, &regs->imask1);
++      priv->write(priv->rx_mask2, &regs->imask2);
+       enable_irq(dev->irq);
+ 
+       /* print chip status */
+@@ -1298,8 +1298,8 @@ static int flexcan_open(struct net_devic
+       priv->tx_mb_idx = priv->mb_count - 1;
+       priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
+ 
+-      priv->reg_imask1_default = 0;
+-      priv->reg_imask2_default = FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
++      priv->rx_mask1 = 0;
++      priv->rx_mask2 = FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
+ 
+       priv->offload.mailbox_read = flexcan_mailbox_read;
+ 
+@@ -1311,12 +1311,12 @@ static int flexcan_open(struct net_devic
+ 
+               imask = GENMASK_ULL(priv->offload.mb_last,
+                                   priv->offload.mb_first);
+-              priv->reg_imask1_default |= imask;
+-              priv->reg_imask2_default |= imask >> 32;
++              priv->rx_mask1 |= imask;
++              priv->rx_mask2 |= imask >> 32;
+ 
+               err = can_rx_offload_add_timestamp(dev, &priv->offload);
+       } else {
+-              priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
++              priv->rx_mask1 |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
+                       FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
+               err = can_rx_offload_add_fifo(dev, &priv->offload,
+                                             FLEXCAN_NAPI_WEIGHT);