pistachio: 5:15: copy config and patch from 5.10

[openwrt/staging/wigyori.git] / target / linux / pistachio / patches-5.15 / 105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch

diff --git a/target/linux/pistachio/patches-5.15/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch b/target/linux/pistachio/patches-5.15/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch
new file mode 100644 (file)
index 0000000..5418503
--- /dev/null
+++ b/target/linux/pistachio/patches-5.15/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch
@@ -0,0 +1,59 @@
+From 56466f505f58f44b69feb7eaed3b506842800456 Mon Sep 17 00:00:00 2001
+From: Ionela Voinescu <ionela.voinescu@imgtec.com>
+Date: Tue, 1 Mar 2016 17:49:45 +0000
+Subject: spi: img-spfi: RX maximum burst size for DMA is 8
+
+The depth of the FIFOs is 16 bytes. The DMA request line is tied
+to the half full/empty (depending on the use of the TX or RX FIFO)
+threshold. For the TX FIFO, if you set a burst size of 8 (equal to
+half the depth) the first burst goes into FIFO without any issues,
+but due the latency involved (the time the data leaves  the DMA
+engine to the time it arrives at the FIFO), the DMA might trigger
+another burst of 8. But given that there is no space for 2 additonal
+bursts of 8, this would result in a failure. Therefore, we have to
+keep the burst size for TX to 4 to accomodate for an extra burst.
+
+For the read (RX) scenario, the DMA request line goes high when
+there is at least 8 entries in the FIFO (half full), and we can
+program the burst size to be 8 because the risk of accidental burst
+does not exist. The DMA engine will not trigger another read until
+the read data for all the burst it has sent out has been received.
+
+While here, move the burst size setting outside of the if/else branches
+as they have the same value for both 8 and 32 bit data widths.
+
+Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
+---
+ drivers/spi/spi-img-spfi.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+--- a/drivers/spi/spi-img-spfi.c
++++ b/drivers/spi/spi-img-spfi.c
+@@ -338,12 +338,11 @@ static int img_spfi_start_dma(struct spi
+               if (xfer->len % 4 == 0) {
+                       rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA;
+                       rxconf.src_addr_width = 4;
+-                      rxconf.src_maxburst = 4;
+               } else {
+                       rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA;
+                       rxconf.src_addr_width = 1;
+-                      rxconf.src_maxburst = 4;
+               }
++              rxconf.src_maxburst = 8;
+               dmaengine_slave_config(spfi->rx_ch, &rxconf);
+ 
+               rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl,
+@@ -362,12 +361,11 @@ static int img_spfi_start_dma(struct spi
+               if (xfer->len % 4 == 0) {
+                       txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA;
+                       txconf.dst_addr_width = 4;
+-                      txconf.dst_maxburst = 4;
+               } else {
+                       txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA;
+                       txconf.dst_addr_width = 1;
+-                      txconf.dst_maxburst = 4;
+               }
++              txconf.dst_maxburst = 4;
+               dmaengine_slave_config(spfi->tx_ch, &txconf);
+ 
+               txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl,