ramips/rt305x: add initial support for Rt5350 SoC

[openwrt/staging/wigyori.git] / target / linux / ramips / files / arch / mips / include / asm / mach-ralink / rt305x_regs.h

diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
index db037a583a03e1117be9c481e947f7766237366e..930b3337b9c766f2bf76469342c24c58eda27351 100644 (file)
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
@@ -76,6 +76,9 @@
 #define RT3352_CHIP_NAME0      0x33335452
 #define RT3352_CHIP_NAME1      0x20203235
 
+#define RT5350_CHIP_NAME0      0x33355452
+#define RT5350_CHIP_NAME1      0x20203035
+
 #define CHIP_ID_ID_MASK                0xff
 #define CHIP_ID_ID_SHIFT       8
 #define CHIP_ID_REV_MASK       0xff
@@ -95,6 +98,12 @@
 #define RT3352_SYSCFG0_CPUCLK_LOW      0x0
 #define RT3352_SYSCFG0_CPUCLK_HIGH     0x1
 
+#define RT5350_SYSCFG0_CPUCLK_SHIFT    8
+#define RT5350_SYSCFG0_CPUCLK_MASK     0x3
+#define RT5350_SYSCFG0_CPUCLK_360      0x0
+#define RT5350_SYSCFG0_CPUCLK_320      0x2
+#define RT5350_SYSCFG0_CPUCLK_300      0x3
+
 #define RT3352_SYSCFG1_USB0_HOST_MODE  BIT(10)
 
 #define RT3352_CLKCFG1_UPHY0_CLK_EN    BIT(18)