ramips/mt7621: drop the timer recalibration patch

[openwrt/staging/wigyori.git] / target / linux / ramips / patches-5.10 / 322-mt7621-fix-cpu-clk-add-clkdev.patch

diff --git a/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch b/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch
index 0c997a3f28f64f2907668f410e9fcb21b45f51aa..be5fee54b2dbaa8bd54a29d968200942d4272eb7 100644 (file)
--- a/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch
+++ b/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch
@@ -36,10 +36,10 @@
  #define MT7621_DDR2_SIZE_MAX          256
 --- a/arch/mips/ralink/mt7621.c
 +++ b/arch/mips/ralink/mt7621.c
-@@ -8,6 +8,10 @@
- #include <linux/kernel.h>
+@@ -9,6 +9,10 @@
  #include <linux/init.h>
- #include <linux/jiffies.h>
+ #include <linux/slab.h>
+ #include <linux/sys_soc.h>
 +#include <linux/clk.h>
 +#include <linux/clkdev.h>
 +#include <linux/clk-provider.h>
@@ -47,25 +47,15 @@
  
  #include <asm/mipsregs.h>
  #include <asm/smp-ops.h>
-@@ -16,16 +20,12 @@
+@@ -16,6 +20,7 @@
+ #include <asm/mach-ralink/ralink_regs.h>
  #include <asm/mach-ralink/mt7621.h>
  #include <asm/mips-boards/launch.h>
- #include <asm/delay.h>
 +#include <asm/time.h>
  
  #include <pinmux.h>
  
- #include "common.h"
- 
--#define SYSC_REG_SYSCFG               0x10
--#define SYSC_REG_CPLL_CLKCFG0 0x2c
--#define SYSC_REG_CUR_CLK_STS  0x44
--#define CPU_CLK_SEL           (BIT(30) | BIT(31))
--
- #define MT7621_GPIO_MODE_UART1                1
- #define MT7621_GPIO_MODE_I2C          2
- #define MT7621_GPIO_MODE_UART3_MASK   0x3
-@@ -111,49 +111,89 @@ static struct rt2880_pmx_group mt7621_pi
+@@ -106,11 +111,89 @@ static struct rt2880_pmx_group mt7621_pi
        { 0 }
  };
  
@@ -80,16 +70,9 @@
        panic("Cannot detect cpc address");
  }
  
--void __init ralink_clk_init(void)
 +static struct clk *__init mt7621_add_sys_clkdev(
 +      const char *id, unsigned long rate)
- {
--      int cpu_fdiv = 0;
--      int cpu_ffrac = 0;
--      int fbdiv = 0;
--      u32 clk_sts, syscfg;
--      u8 clk_sel = 0, xtal_mode;
--      u32 cpu_clk;
++{
 +      struct clk *clk;
 +      int err;
 +
@@ -100,9 +83,7 @@
 +      err = clk_register_clkdev(clk, id, NULL);
 +      if (err)
 +              panic("unable to register %s clock device", id);
- 
--      if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
--              clk_sel = 1;
++
 +      return clk;
 +}
 +
@@ -129,38 +110,20 @@
 +              xtal_clk = 40 * 1000 * 1000;
 +      else
 +              xtal_clk = 25 * 1000 * 1000;
- 
-       switch (clk_sel) {
-       case 0:
--              clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
--              cpu_fdiv = ((clk_sts >> 8) & 0x1F);
--              cpu_ffrac = (clk_sts & 0x1F);
--              cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
++
++      switch (clk_sel) {
++      case 0:
 +              cpu_clk = 500 * 1000 * 1000;
-               break;
--
-       case 1:
--              fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
--              syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
--              xtal_mode = (syscfg >> 6) & 0x7;
--              if (xtal_mode >= 6) {
--                      /* 25Mhz Xtal */
--                      cpu_clk = 25 * fbdiv * 1000 * 1000;
--              } else if (xtal_mode >= 3) {
--                      /* 40Mhz Xtal */
--                      cpu_clk = 40 * fbdiv * 1000 * 1000;
--              } else {
--                      /* 20Mhz Xtal */
--                      cpu_clk = 20 * fbdiv * 1000 * 1000;
--              }
++              break;
++      case 1:
 +              pll = rt_memc_r32(MEMC_REG_CPU_PLL);
 +              fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
 +              prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
 +              cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
-               break;
++              break;
 +      default:
 +              cpu_clk = xtal_clk;
-       }
++      }
 +
 +      cpu_clk = cpu_clk / ffiv * ffrac;
 +      bus_clk = cpu_clk / 4;
@@ -170,14 +133,14 @@
 +
 +      pr_info("CPU Clock: %dMHz\n", cpu_clk / 1000000);
 +      mips_hpt_frequency = cpu_clk / 2;
- }
- 
++}
++
 +static void __init mt7621_clocks_init_dt(struct device_node *np)
 +{
 +      of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 +}
 +
-+CLK_OF_DECLARE(ar7100, "mediatek,mt7621-pll", mt7621_clocks_init_dt);
++CLK_OF_DECLARE(mt7621, "mediatek,mt7621-pll", mt7621_clocks_init_dt);
 +
  void __init ralink_of_remap(void)
  {
@@ -187,7 +150,7 @@
 @@ -9,14 +9,14 @@
  
  #include <linux/of.h>
- #include <linux/clk-provider.h>
+ #include <linux/of_clk.h>
 -#include <linux/clocksource.h>
 +#include <asm/time.h>