ramips: 6.1: copy config and patches

[openwrt/staging/wigyori.git] / target / linux / ramips / patches-6.1 / 000-v5.18-02-staging-mt7621-dts-align-resets-with-binding-documen.patch

diff --git a/target/linux/ramips/patches-6.1/000-v5.18-02-staging-mt7621-dts-align-resets-with-binding-documen.patch b/target/linux/ramips/patches-6.1/000-v5.18-02-staging-mt7621-dts-align-resets-with-binding-documen.patch
new file mode 100644 (file)
index 0000000..e4fd34b
--- /dev/null
+++ b/target/linux/ramips/patches-6.1/000-v5.18-02-staging-mt7621-dts-align-resets-with-binding-documen.patch
@@ -0,0 +1,114 @@
+From 64b2d6ffff862c0e7278198b4229e42e1abb3bb1 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 10 Jan 2022 12:49:30 +0100
+Subject: [PATCH 2/2] staging: mt7621-dts: align resets with binding documentation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated
+to be used as a reset provider. Align reset related bits and system controller
+node with binding documentation along the dtsi file.
+
+Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Link: https://lore.kernel.org/r/20220110114930.1406665-5-sergio.paracuellos@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/staging/mt7621-dts/mt7621.dtsi | 21 +++++++++------------
+ 1 file changed, 9 insertions(+), 12 deletions(-)
+
+--- a/drivers/staging/mt7621-dts/mt7621.dtsi
++++ b/drivers/staging/mt7621-dts/mt7621.dtsi
+@@ -1,6 +1,7 @@
+ #include <dt-bindings/interrupt-controller/mips-gic.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/clock/mt7621-clk.h>
++#include <dt-bindings/reset/mt7621-reset.h>
+ 
+ / {
+       #address-cells = <1>;
+@@ -59,6 +60,7 @@
+                       compatible = "mediatek,mt7621-sysc", "syscon";
+                       reg = <0x0 0x100>;
+                       #clock-cells = <1>;
++                      #reset-cells = <1>;
+                       ralink,memctl = <&memc>;
+                       clock-output-names = "xtal", "cpu", "bus",
+                                            "50m", "125m", "150m",
+@@ -88,7 +90,7 @@
+ 
+                       clocks = <&sysc MT7621_CLK_I2C>;
+                       clock-names = "i2c";
+-                      resets = <&rstctrl 16>;
++                      resets = <&sysc MT7621_RST_I2C>;
+                       reset-names = "i2c";
+ 
+                       #address-cells = <1>;
+@@ -161,7 +163,7 @@
+                       clocks = <&sysc MT7621_CLK_SPI>;
+                       clock-names = "spi";
+ 
+-                      resets = <&rstctrl 18>;
++                      resets = <&sysc MT7621_RST_SPI>;
+                       reset-names = "spi";
+ 
+                       #address-cells = <1>;
+@@ -296,11 +298,6 @@
+               };
+       };
+ 
+-      rstctrl: rstctrl {
+-              compatible = "ralink,rt2880-reset";
+-              #reset-cells = <1>;
+-      };
+-
+       sdhci: sdhci@1e130000 {
+               status = "disabled";
+ 
+@@ -383,7 +380,7 @@
+               #address-cells = <1>;
+               #size-cells = <0>;
+ 
+-              resets = <&rstctrl 6 &rstctrl 23>;
++              resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>;
+               reset-names = "fe", "eth";
+ 
+               interrupt-parent = <&gic>;
+@@ -423,7 +420,7 @@
+                               #size-cells = <0>;
+                               reg = <0>;
+                               mediatek,mcm;
+-                              resets = <&rstctrl 2>;
++                              resets = <&sysc MT7621_RST_MCM>;
+                               reset-names = "mcm";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+@@ -516,7 +513,7 @@
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0>;
+                       interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
+-                      resets = <&rstctrl 24>;
++                      resets = <&sysc MT7621_RST_PCIE0>;
+                       clocks = <&sysc MT7621_CLK_PCIE0>;
+                       phys = <&pcie0_phy 1>;
+                       phy-names = "pcie-phy0";
+@@ -531,7 +528,7 @@
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0>;
+                       interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
+-                      resets = <&rstctrl 25>;
++                      resets = <&sysc MT7621_RST_PCIE1>;
+                       clocks = <&sysc MT7621_CLK_PCIE1>;
+                       phys = <&pcie0_phy 1>;
+                       phy-names = "pcie-phy1";
+@@ -546,7 +543,7 @@
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0>;
+                       interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+-                      resets = <&rstctrl 26>;
++                      resets = <&sysc MT7621_RST_PCIE2>;
+                       clocks = <&sysc MT7621_CLK_PCIE2>;
+                       phys = <&pcie2_phy 0>;
+                       phy-names = "pcie-phy2";