brcm2708: remove linux 4.4 support

[openwrt/staging/yousong.git] / target / linux / brcm2708 / patches-4.4 / 0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch

diff --git a/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch b/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch
deleted file mode 100644 (file)
index 20a9cd8..0000000
--- a/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From df502f9589fb2d25ef93906adfb2ce2f8349397d Mon Sep 17 00:00:00 2001
-From: Martin Sperl <kernel@martin.sperl.org>
-Date: Mon, 29 Feb 2016 15:43:56 +0000
-Subject: [PATCH] clk: bcm2835: add missing PLL clock dividers
-
-Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Reviewed-by: Eric Anholt <eric@anholt.net>
-(cherry picked from commit 728436956aa172b24a3212295f8b53feb6479f32)
----
- drivers/clk/bcm/clk-bcm2835.c       | 32 ++++++++++++++++++++++++++++++++
- include/dt-bindings/clock/bcm2835.h |  5 +++++
- 2 files changed, 37 insertions(+)
-
---- a/drivers/clk/bcm/clk-bcm2835.c
-+++ b/drivers/clk/bcm/clk-bcm2835.c
-@@ -1389,6 +1389,22 @@ static const struct bcm2835_clk_desc clk
-               .load_mask = CM_PLLA_LOADPER,
-               .hold_mask = CM_PLLA_HOLDPER,
-               .fixed_divider = 1),
-+      [BCM2835_PLLA_DSI0]     = REGISTER_PLL_DIV(
-+              .name = "plla_dsi0",
-+              .source_pll = "plla",
-+              .cm_reg = CM_PLLA,
-+              .a2w_reg = A2W_PLLA_DSI0,
-+              .load_mask = CM_PLLA_LOADDSI0,
-+              .hold_mask = CM_PLLA_HOLDDSI0,
-+              .fixed_divider = 1),
-+      [BCM2835_PLLA_CCP2]     = REGISTER_PLL_DIV(
-+              .name = "plla_ccp2",
-+              .source_pll = "plla",
-+              .cm_reg = CM_PLLA,
-+              .a2w_reg = A2W_PLLA_CCP2,
-+              .load_mask = CM_PLLA_LOADCCP2,
-+              .hold_mask = CM_PLLA_HOLDCCP2,
-+              .fixed_divider = 1),
- 
-       /* PLLB is used for the ARM's clock. */
-       [BCM2835_PLLB]          = REGISTER_PLL(
-@@ -1503,6 +1519,22 @@ static const struct bcm2835_clk_desc clk
-               .load_mask = CM_PLLD_LOADPER,
-               .hold_mask = CM_PLLD_HOLDPER,
-               .fixed_divider = 1),
-+      [BCM2835_PLLD_DSI0]     = REGISTER_PLL_DIV(
-+              .name = "plld_dsi0",
-+              .source_pll = "plld",
-+              .cm_reg = CM_PLLD,
-+              .a2w_reg = A2W_PLLD_DSI0,
-+              .load_mask = CM_PLLD_LOADDSI0,
-+              .hold_mask = CM_PLLD_HOLDDSI0,
-+              .fixed_divider = 1),
-+      [BCM2835_PLLD_DSI1]     = REGISTER_PLL_DIV(
-+              .name = "plld_dsi1",
-+              .source_pll = "plld",
-+              .cm_reg = CM_PLLD,
-+              .a2w_reg = A2W_PLLD_DSI1,
-+              .load_mask = CM_PLLD_LOADDSI1,
-+              .hold_mask = CM_PLLD_HOLDDSI1,
-+              .fixed_divider = 1),
- 
-       /*
-        * PLLH is used to supply the pixel clock or the AUX clock for the
---- a/include/dt-bindings/clock/bcm2835.h
-+++ b/include/dt-bindings/clock/bcm2835.h
-@@ -45,3 +45,8 @@
- #define BCM2835_CLOCK_PERI_IMAGE      29
- #define BCM2835_CLOCK_PWM             30
- #define BCM2835_CLOCK_PCM             31
-+
-+#define BCM2835_PLLA_DSI0             32
-+#define BCM2835_PLLA_CCP2             33
-+#define BCM2835_PLLD_DSI0             34
-+#define BCM2835_PLLD_DSI1             35