+++ /dev/null
-diff -urN linux.old/arch/mips/kernel/genex.S linux.dev/arch/mips/kernel/genex.S
---- linux.old/arch/mips/kernel/genex.S 2005-12-04 06:10:42.000000000 +0100
-+++ linux.dev/arch/mips/kernel/genex.S 2005-12-18 05:30:48.564937750 +0100
-@@ -72,6 +72,10 @@
- .set push
- .set mips3
- .set noat
-+#ifdef CONFIG_BCM4710
-+ nop
-+ nop
-+#endif
- mfc0 k1, CP0_CAUSE
- li k0, 31<<2
- andi k1, k1, 0x7c
-diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
---- linux.old/arch/mips/mm/c-r4k.c 2005-12-04 06:10:42.000000000 +0100
-+++ linux.dev/arch/mips/mm/c-r4k.c 2005-12-18 06:08:19.112437750 +0100
-@@ -14,6 +14,12 @@
- #include <linux/mm.h>
- #include <linux/bitops.h>
-
-+#ifdef CONFIG_BCM4710
-+#include "../bcm947xx/include/typedefs.h"
-+#include "../bcm947xx/include/sbconfig.h"
-+#include <asm/paccess.h>
-+#endif
-+
- #include <asm/bcache.h>
- #include <asm/bootinfo.h>
- #include <asm/cache.h>
-@@ -29,6 +35,9 @@
- #include <asm/war.h>
- #include <asm/cacheflush.h> /* for run_uncached() */
-
-+/* For enabling BCM4710 cache workarounds */
-+int bcm4710 = 0;
-+
- /*
- * Must die.
- */
-@@ -73,7 +82,9 @@
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-- if (dc_lsize == 16)
-+ if (bcm4710)
-+ r4k_blast_dcache_page = blast_dcache_page;
-+ else if (dc_lsize == 16)
- r4k_blast_dcache_page = blast_dcache16_page;
- else if (dc_lsize == 32)
- r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
-@@ -85,7 +96,9 @@
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-- if (dc_lsize == 16)
-+ if (bcm4710)
-+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
-+ else if (dc_lsize == 16)
- r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
- else if (dc_lsize == 32)
- r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
-@@ -97,7 +110,9 @@
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-- if (dc_lsize == 16)
-+ if (bcm4710)
-+ r4k_blast_dcache = blast_dcache;
-+ else if (dc_lsize == 16)
- r4k_blast_dcache = blast_dcache16;
- else if (dc_lsize == 32)
- r4k_blast_dcache = blast_dcache32;
-@@ -486,6 +501,9 @@
- addr = start & ~(dc_lsize - 1);
- aend = (end - 1) & ~(dc_lsize - 1);
-
-+ BCM4710_PROTECTED_FILL_TLB(addr);
-+ BCM4710_PROTECTED_FILL_TLB(aend);
-+
- while (1) {
- /* Hit_Writeback_Inv_D */
- protected_writeback_dcache_line(addr);
-@@ -657,6 +675,10 @@
- R4600_HIT_CACHEOP_WAR_IMPL;
- a = addr & ~(dc_lsize - 1);
- end = (addr + size - 1) & ~(dc_lsize - 1);
-+
-+ BCM4710_FILL_TLB(a);
-+ BCM4710_FILL_TLB(end);
-+
- while (1) {
- flush_dcache_line(a); /* Hit_Writeback_Inv_D */
- if (a == end)
-@@ -702,6 +724,10 @@
- R4600_HIT_CACHEOP_WAR_IMPL;
- a = addr & ~(dc_lsize - 1);
- end = (addr + size - 1) & ~(dc_lsize - 1);
-+
-+ BCM4710_FILL_TLB(a);
-+ BCM4710_FILL_TLB(end);
-+
- while (1) {
- flush_dcache_line(a); /* Hit_Writeback_Inv_D */
- if (a == end)
-@@ -727,6 +753,8 @@
- unsigned long addr = (unsigned long) arg;
-
- R4600_HIT_CACHEOP_WAR_IMPL;
-+ BCM4710_PROTECTED_FILL_TLB(addr);
-+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
- protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
- if (!cpu_icache_snoops_remote_store)
- protected_writeback_scache_line(addr & ~(sc_lsize - 1));
-@@ -1202,6 +1230,16 @@
- static inline void coherency_setup(void)
- {
- change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
-+#if defined(CONFIG_BCM4310) || defined(CONFIG_BCM4704) || defined(CONFIG_BCM5365)
-+ if (BCM330X(current_cpu_data.processor_id)) {
-+ __u32 cm = read_c0_diag();
-+ /* Enable icache */
-+ cm |= (1 << 31);
-+ /* Enable dcache */
-+ cm |= (1 << 30);
-+ write_c0_diag(cm);
-+ }
-+#endif
-
- /*
- * c0_status.cu=0 specifies that updates by the sc instruction use
-@@ -1231,6 +1269,15 @@
-
- /* Default cache error handler for R4000 and R5000 family */
- set_uncached_handler (0x100, &except_vec2_generic, 0x80);
-+
-+ /* Check if special workarounds are required */
-+#ifdef CONFIG_BCM4710
-+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
-+ printk("Enabling BCM4710A0 cache workarounds.\n");
-+ bcm4710 = 1;
-+ } else
-+#endif
-+ bcm4710 = 0;
-
- probe_pcache();
- setup_scache();
-diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
---- linux.old/arch/mips/mm/tlbex.c 2005-12-15 12:57:27.945158000 +0100
-+++ linux.dev/arch/mips/mm/tlbex.c 2005-12-18 06:06:17.916863500 +0100
-@@ -28,6 +28,10 @@
-
- /* #define DEBUG_TLB */
-
-+#ifdef CONFIG_BCM4710
-+extern int bcm4710;
-+#endif
-+
- static __init int __attribute__((unused)) r45k_bvahwbug(void)
- {
- /* XXX: We should probe for the presence of this bug, but we don't. */
-@@ -1152,6 +1156,12 @@
- memset(relocs, 0, sizeof(relocs));
- memset(final_handler, 0, sizeof(final_handler));
-
-+#ifdef CONFIG_BCM4710
-+ if (bcm4710) {
-+ i_nop(&p);
-+ }
-+#endif
-+
- /*
- * create the plain linear handler
- */
-diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
---- linux.old/include/asm-mips/r4kcache.h 2005-12-17 22:39:19.281320000 +0100
-+++ linux.dev/include/asm-mips/r4kcache.h 2005-12-18 05:22:06.020280750 +0100
-@@ -15,6 +15,18 @@
- #include <asm/asm.h>
- #include <asm/cacheops.h>
-
-+#ifdef CONFIG_BCM4710
-+#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
-+
-+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
-+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
-+#else
-+#define BCM4710_DUMMY_RREG()
-+
-+#define BCM4710_FILL_TLB(addr)
-+#define BCM4710_PROTECTED_FILL_TLB(addr)
-+#endif
-+
- /*
- * This macro return a properly sign-extended address suitable as base address
- * for indexed cache operations. Two issues here:
-@@ -45,6 +57,7 @@
-
- static inline void flush_dcache_line_indexed(unsigned long addr)
- {
-+ BCM4710_DUMMY_RREG();
- cache_op(Index_Writeback_Inv_D, addr);
- }
-
-@@ -60,11 +73,13 @@
-
- static inline void flush_dcache_line(unsigned long addr)
- {
-+ BCM4710_DUMMY_RREG();
- cache_op(Hit_Writeback_Inv_D, addr);
- }
-
- static inline void invalidate_dcache_line(unsigned long addr)
- {
-+ BCM4710_DUMMY_RREG();
- cache_op(Hit_Invalidate_D, addr);
- }
-
-@@ -104,6 +119,7 @@
- */
- static inline void protected_writeback_dcache_line(unsigned long addr)
- {
-+ BCM4710_DUMMY_RREG();
- __asm__ __volatile__(
- " .set push \n"
- " .set noreorder \n"
-@@ -166,6 +182,49 @@
- : "r" (base), \
- "i" (op));
-
-+static inline void blast_dcache(void)
-+{
-+ unsigned long start = KSEG0;
-+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
-+ unsigned long end = (start + dcache_size);
-+
-+ do {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Index_Writeback_Inv_D, start);
-+ start += current_cpu_data.dcache.linesz;
-+ } while(start < end);
-+}
-+
-+static inline void blast_dcache_page(unsigned long page)
-+{
-+ unsigned long start = page;
-+ unsigned long end = start + PAGE_SIZE;
-+
-+ BCM4710_FILL_TLB(start);
-+ do {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Hit_Writeback_Inv_D, start);
-+ start += current_cpu_data.dcache.linesz;
-+ } while(start < end);
-+}
-+
-+static inline void blast_dcache_page_indexed(unsigned long page)
-+{
-+ unsigned long start = page;
-+ unsigned long end = start + PAGE_SIZE;
-+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
-+ unsigned long ws_end = current_cpu_data.dcache.ways <<
-+ current_cpu_data.dcache.waybit;
-+ unsigned long ws, addr;
-+ for (ws = 0; ws < ws_end; ws += ws_inc) {
-+ start = page + ws;
-+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Index_Writeback_Inv_D, addr);
-+ }
-+ }
-+}
-+
- static inline void blast_dcache16(void)
- {
- unsigned long start = INDEX_BASE;
-@@ -213,7 +272,8 @@
- unsigned long ws_end = current_cpu_data.icache.ways <<
- current_cpu_data.icache.waybit;
- unsigned long ws, addr;
--
-+
-+ BCM4710_FILL_TLB(start);
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x200)
- cache16_unroll32(addr|ws,Index_Invalidate_I);
-@@ -357,6 +417,7 @@
- current_cpu_data.icache.waybit;
- unsigned long ws, addr;
-
-+ BCM4710_FILL_TLB(start);
- for (ws = 0; ws < ws_end; ws += ws_inc)
- for (addr = start; addr < end; addr += 0x400)
- cache32_unroll32(addr|ws,Index_Invalidate_I);
-@@ -471,6 +532,7 @@
- unsigned long start = page;
- unsigned long end = start + PAGE_SIZE;
-
-+ BCM4710_FILL_TLB(start);
- do {
- cache64_unroll32(start,Hit_Invalidate_I);
- start += 0x800;
-diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
---- linux.old/include/asm-mips/stackframe.h 2005-12-04 06:10:42.000000000 +0100
-+++ linux.dev/include/asm-mips/stackframe.h 2005-12-18 05:33:02.405302250 +0100
-@@ -285,6 +285,10 @@
- .macro RESTORE_SP_AND_RET
- LONG_L sp, PT_R29(sp)
- .set mips3
-+#ifdef CONFIG_BCM4710
-+ nop
-+ nop
-+#endif
- eret
- .set mips0
- .endm
projects / openwrt / svn-archive / archive.git / blobdiff