---- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
-@@ -3271,6 +3271,18 @@ static bool ar9300_check_eeprom_header(s
- return ar9300_check_header(header);
+--- a/drivers/net/wireless/ath/ath9k/ath9k.h
++++ b/drivers/net/wireless/ath/ath9k/ath9k.h
+@@ -189,7 +189,6 @@ struct ath_txq {
+ u32 axq_ampdu_depth;
+ bool stopped;
+ bool axq_tx_inprogress;
+- bool txq_flush_inprogress;
+ struct list_head axq_acq;
+ struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
+ struct list_head txq_fifo_pending;
+--- a/drivers/net/wireless/ath/ath9k/beacon.c
++++ b/drivers/net/wireless/ath/ath9k/beacon.c
+@@ -373,6 +373,7 @@ void ath_beacon_tasklet(unsigned long da
+ ath_dbg(common, ATH_DBG_BSTUCK,
+ "missed %u consecutive beacons\n",
+ sc->beacon.bmisscnt);
++ ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq);
+ ath9k_hw_bstuck_nfcal(ah);
+ } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
+ ath_dbg(common, ATH_DBG_BSTUCK,
+@@ -450,16 +451,6 @@ void ath_beacon_tasklet(unsigned long da
+ sc->beacon.updateslot = OK;
+ }
+ if (bfaddr != 0) {
+- /*
+- * Stop any current dma and put the new frame(s) on the queue.
+- * This should never fail since we check above that no frames
+- * are still pending on the queue.
+- */
+- if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) {
+- ath_err(common, "beacon queue %u did not stop?\n",
+- sc->beacon.beaconq);
+- }
+-
+ /* NB: cabq traffic should already be queued and primed */
+ ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bfaddr);
+ ath9k_hw_txstart(ah, sc->beacon.beaconq);
+@@ -780,7 +771,7 @@ void ath9k_set_beaconing_status(struct a
+ ah->imask &= ~ATH9K_INT_SWBA;
+ ath9k_hw_set_interrupts(ah, ah->imask);
+ tasklet_kill(&sc->bcon_tasklet);
+- ath9k_hw_stoptxdma(ah, sc->beacon.beaconq);
++ ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq);
+ }
+ ath9k_ps_restore(sc);
}
+--- a/drivers/net/wireless/ath/ath9k/hw.h
++++ b/drivers/net/wireless/ath/ath9k/hw.h
+@@ -95,9 +95,9 @@
+ #define REG_READ_FIELD(_a, _r, _f) \
+ (((REG_READ(_a, _r) & _f) >> _f##_S))
+ #define REG_SET_BIT(_a, _r, _f) \
+- REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
++ REG_WRITE(_a, _r, REG_READ(_a, _r) | (_f))
+ #define REG_CLR_BIT(_a, _r, _f) \
+- REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
++ REG_WRITE(_a, _r, REG_READ(_a, _r) & ~(_f))
-+static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
-+ int mdata_size)
-+{
-+ struct ath_common *common = ath9k_hw_common(ah);
-+ u16 *data = (u16 *) mptr;
-+ int i;
-+
-+ for (i = 0; i < mdata_size / 2; i++, data++)
-+ ath9k_hw_nvram_read(common, i, data);
-+
-+ return 0;
+ #define DO_DELAY(x) do { \
+ if ((++(x) % 64) == 0) \
+--- a/drivers/net/wireless/ath/ath9k/mac.c
++++ b/drivers/net/wireless/ath/ath9k/mac.c
+@@ -143,84 +143,59 @@ bool ath9k_hw_updatetxtriglevel(struct a
+ }
+ EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
+
+-bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
++void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
+ {
+-#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */
+-#define ATH9K_TIME_QUANTUM 100 /* usec */
+- struct ath_common *common = ath9k_hw_common(ah);
+- struct ath9k_hw_capabilities *pCap = &ah->caps;
+- struct ath9k_tx_queue_info *qi;
+- u32 tsfLow, j, wait;
+- u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
++ int i, q;
+
+- if (q >= pCap->total_queues) {
+- ath_dbg(common, ATH_DBG_QUEUE,
+- "Stopping TX DMA, invalid queue: %u\n", q);
+- return false;
+- }
++ REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
+
+- qi = &ah->txq[q];
+- if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
+- ath_dbg(common, ATH_DBG_QUEUE,
+- "Stopping TX DMA, inactive queue: %u\n", q);
+- return false;
+- }
++ REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
++ REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
++ REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
+
+- REG_WRITE(ah, AR_Q_TXD, 1 << q);
++ for (q = 0; q < AR_NUM_QCU; q++) {
++ for (i = 0; i < 1000; i++) {
++ if (i)
++ udelay(5);
+
+- for (wait = wait_time; wait != 0; wait--) {
+- if (ath9k_hw_numtxpending(ah, q) == 0)
+- break;
+- udelay(ATH9K_TIME_QUANTUM);
++ if (!ath9k_hw_numtxpending(ah, q))
++ break;
++ }
+ }
+
+- if (ath9k_hw_numtxpending(ah, q)) {
+- ath_dbg(common, ATH_DBG_QUEUE,
+- "%s: Num of pending TX Frames %d on Q %d\n",
+- __func__, ath9k_hw_numtxpending(ah, q), q);
+-
+- for (j = 0; j < 2; j++) {
+- tsfLow = REG_READ(ah, AR_TSF_L32);
+- REG_WRITE(ah, AR_QUIET2,
+- SM(10, AR_QUIET2_QUIET_DUR));
+- REG_WRITE(ah, AR_QUIET_PERIOD, 100);
+- REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
+- REG_SET_BIT(ah, AR_TIMER_MODE,
+- AR_QUIET_TIMER_EN);
+-
+- if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
+- break;
++ REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
++ REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
++ REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
+
+- ath_dbg(common, ATH_DBG_QUEUE,
+- "TSF has moved while trying to set quiet time TSF: 0x%08x\n",
+- tsfLow);
+- }
++ REG_WRITE(ah, AR_Q_TXD, 0);
+}
- /*
- * Read the configuration data from the eeprom.
- * The data can be put in any specified memory buffer.
-@@ -3293,6 +3305,9 @@ static int ar9300_eeprom_restore_interna
- struct ath_common *common = ath9k_hw_common(ah);
- eeprom_read_op read;
-
-+ if (ath9k_hw_use_flash(ah))
-+ return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
-+
- word = kzalloc(2048, GFP_KERNEL);
- if (!word)
- return -1;
---- a/drivers/net/wireless/ath/ath9k/hw.c
-+++ b/drivers/net/wireless/ath/ath9k/hw.c
-@@ -419,10 +419,6 @@ static void ath9k_hw_init_defaults(struc
- ah->hw_version.magic = AR5416_MAGIC;
- ah->hw_version.subvendorid = 0;
-
-- ah->ah_flags = 0;
-- if (!AR_SREV_9100(ah))
-- ah->ah_flags = AH_USE_EEPROM;
--
- ah->atim_window = 0;
- ah->sta_id1_defaults =
- AR_STA_ID1_CRPT_MIC_ENABLE |
---- a/drivers/net/wireless/ath/ath9k/init.c
-+++ b/drivers/net/wireless/ath/ath9k/init.c
-@@ -533,6 +533,9 @@ static int ath9k_init_softc(u16 devid, s
- ah->hw_version.subsysid = subsysid;
- sc->sc_ah = ah;
-
-+ if (!sc->dev->platform_data)
-+ ah->ah_flags |= AH_USE_EEPROM;
++EXPORT_SYMBOL(ath9k_hw_abort_tx_dma);
+
+- REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
++bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q)
++{
++#define ATH9K_TX_STOP_DMA_TIMEOUT 1000 /* usec */
++#define ATH9K_TIME_QUANTUM 100 /* usec */
++ int wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
++ int wait;
+
+- udelay(200);
+- REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
++ REG_WRITE(ah, AR_Q_TXD, 1 << q);
+
+- wait = wait_time;
+- while (ath9k_hw_numtxpending(ah, q)) {
+- if ((--wait) == 0) {
+- ath_err(common,
+- "Failed to stop TX DMA in 100 msec after killing last frame\n");
+- break;
+- }
++ for (wait = wait_time; wait != 0; wait--) {
++ if (wait != wait_time)
+ udelay(ATH9K_TIME_QUANTUM);
+- }
+
+- REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
++ if (ath9k_hw_numtxpending(ah, q) == 0)
++ break;
+ }
+
+ REG_WRITE(ah, AR_Q_TXD, 0);
+
- common = ath9k_hw_common(ah);
- common->ops = &ath9k_common_ops;
- common->bus_ops = bus_ops;
---- a/drivers/net/wireless/ath/ath9k/pci.c
-+++ b/drivers/net/wireless/ath/ath9k/pci.c
-@@ -16,6 +16,7 @@
-
- #include <linux/nl80211.h>
- #include <linux/pci.h>
-+#include <linux/ath9k_platform.h>
- #include "ath9k.h"
-
- static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
-@@ -53,21 +54,36 @@ static void ath_pci_read_cachesize(struc
-
- static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
+ return wait != 0;
+
+ #undef ATH9K_TX_STOP_DMA_TIMEOUT
+ #undef ATH9K_TIME_QUANTUM
+ }
+-EXPORT_SYMBOL(ath9k_hw_stoptxdma);
++EXPORT_SYMBOL(ath9k_hw_stop_dma_queue);
+
+ void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
{
-- struct ath_hw *ah = (struct ath_hw *) common->ah;
-+ struct ath_softc *sc = (struct ath_softc *) common->priv;
-+ struct ath9k_platform_data *pdata = sc->dev->platform_data;
-
-- common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
-+ if (pdata) {
-+ if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
-+ ath_print(common, ATH_DBG_FATAL,
-+ "%s: eeprom read failed, offset %08x "
-+ "is out of range\n",
-+ __func__, off);
-+ }
+--- a/drivers/net/wireless/ath/ath9k/mac.h
++++ b/drivers/net/wireless/ath/ath9k/mac.h
+@@ -676,7 +676,8 @@ void ath9k_hw_txstart(struct ath_hw *ah,
+ void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds);
+ u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
+ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
+-bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q);
++bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q);
++void ath9k_hw_abort_tx_dma(struct ath_hw *ah);
+ void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
+ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
+ const struct ath9k_tx_queue_info *qinfo);
+--- a/drivers/net/wireless/ath/ath9k/main.c
++++ b/drivers/net/wireless/ath/ath9k/main.c
+@@ -2128,56 +2128,42 @@ static void ath9k_set_coverage_class(str
+
+ static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
+ {
+-#define ATH_FLUSH_TIMEOUT 60 /* ms */
+ struct ath_softc *sc = hw->priv;
+- struct ath_txq *txq = NULL;
+- struct ath_hw *ah = sc->sc_ah;
+- struct ath_common *common = ath9k_hw_common(ah);
+- int i, j, npend = 0;
++ int timeout = 200; /* ms */
++ int i, j;
+
++ ath9k_ps_wakeup(sc);
+ mutex_lock(&sc->mutex);
+
+ cancel_delayed_work_sync(&sc->tx_complete_work);
+
+- for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
+- if (!ATH_TXQ_SETUP(sc, i))
+- continue;
+- txq = &sc->tx.txq[i];
+-
+- if (!drop) {
+- for (j = 0; j < ATH_FLUSH_TIMEOUT; j++) {
+- if (!ath9k_has_pending_frames(sc, txq))
+- break;
+- usleep_range(1000, 2000);
+- }
+- }
++ if (drop)
++ timeout = 1;
+
-+ *data = pdata->eeprom_data[off];
-+ } else {
-+ struct ath_hw *ah = (struct ath_hw *) common->ah;
++ for (j = 0; j < timeout; j++) {
++ int npend = 0;
+
-+ common->ops->read(ah, AR5416_EEPROM_OFFSET +
-+ (off << AR5416_EEPROM_S));
++ if (j)
++ usleep_range(1000, 2000);
+
+- if (drop || ath9k_has_pending_frames(sc, txq)) {
+- ath_dbg(common, ATH_DBG_QUEUE, "Drop frames from hw queue:%d\n",
+- txq->axq_qnum);
+- spin_lock_bh(&txq->axq_lock);
+- txq->txq_flush_inprogress = true;
+- spin_unlock_bh(&txq->axq_lock);
+-
+- ath9k_ps_wakeup(sc);
+- ath9k_hw_stoptxdma(ah, txq->axq_qnum);
+- npend = ath9k_hw_numtxpending(ah, txq->axq_qnum);
+- ath9k_ps_restore(sc);
+- if (npend)
+- break;
++ for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
++ if (!ATH_TXQ_SETUP(sc, i))
++ continue;
+
+- ath_draintxq(sc, txq, false);
+- txq->txq_flush_inprogress = false;
++ npend += ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
+ }
+
-+ if (!ath9k_hw_wait(ah,
-+ AR_EEPROM_STATUS_DATA,
-+ AR_EEPROM_STATUS_DATA_BUSY |
-+ AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
-+ AH_WAIT_TIMEOUT)) {
-+ return false;
-+ }
++ if (!npend)
++ goto out;
+ }
-- if (!ath9k_hw_wait(ah,
-- AR_EEPROM_STATUS_DATA,
-- AR_EEPROM_STATUS_DATA_BUSY |
-- AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
-- AH_WAIT_TIMEOUT)) {
-- return false;
-+ *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
-+ AR_EEPROM_STATUS_DATA_VAL);
+- if (npend) {
++ if (!ath_drain_all_txq(sc, false))
+ ath_reset(sc, false);
+- txq->txq_flush_inprogress = false;
+- }
+
++out:
+ ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
+ mutex_unlock(&sc->mutex);
++ ath9k_ps_restore(sc);
+ }
+
+ struct ieee80211_ops ath9k_ops = {
+--- a/drivers/net/wireless/ath/ath9k/xmit.c
++++ b/drivers/net/wireless/ath/ath9k/xmit.c
+@@ -166,7 +166,7 @@ static void ath_tx_flush_tid(struct ath_
+ fi = get_frame_info(bf->bf_mpdu);
+ if (fi->retries) {
+ ath_tx_update_baw(sc, tid, fi->seqno);
+- ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
++ ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
+ } else {
+ ath_tx_send_normal(sc, txq, NULL, &bf_head);
+ }
+@@ -1194,16 +1194,14 @@ bool ath_drain_all_txq(struct ath_softc
+ if (sc->sc_flags & SC_OP_INVALID)
+ return true;
+
+- /* Stop beacon queue */
+- ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
++ ath9k_hw_abort_tx_dma(ah);
+
+- /* Stop data queues */
++ /* Check if any queue remains active */
+ for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
+- if (ATH_TXQ_SETUP(sc, i)) {
+- txq = &sc->tx.txq[i];
+- ath9k_hw_stoptxdma(ah, txq->axq_qnum);
+- npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
+- }
++ if (!ATH_TXQ_SETUP(sc, i))
++ continue;
++
++ npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum);
}
-- *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
-- AR_EEPROM_STATUS_DATA_VAL);
--
- return true;
+ if (npend)
+@@ -2014,8 +2012,7 @@ static void ath_tx_processq(struct ath_s
+ spin_lock_bh(&txq->axq_lock);
+ if (list_empty(&txq->axq_q)) {
+ txq->axq_link = NULL;
+- if (sc->sc_flags & SC_OP_TXAGGR &&
+- !txq->txq_flush_inprogress)
++ if (sc->sc_flags & SC_OP_TXAGGR)
+ ath_txq_schedule(sc, txq);
+ spin_unlock_bh(&txq->axq_lock);
+ break;
+@@ -2096,7 +2093,7 @@ static void ath_tx_processq(struct ath_s
+
+ spin_lock_bh(&txq->axq_lock);
+
+- if (sc->sc_flags & SC_OP_TXAGGR && !txq->txq_flush_inprogress)
++ if (sc->sc_flags & SC_OP_TXAGGR)
+ ath_txq_schedule(sc, txq);
+ spin_unlock_bh(&txq->axq_lock);
+ }
+@@ -2267,18 +2264,17 @@ void ath_tx_edma_tasklet(struct ath_soft
+
+ spin_lock_bh(&txq->axq_lock);
+
+- if (!txq->txq_flush_inprogress) {
+- if (!list_empty(&txq->txq_fifo_pending)) {
+- INIT_LIST_HEAD(&bf_head);
+- bf = list_first_entry(&txq->txq_fifo_pending,
+- struct ath_buf, list);
+- list_cut_position(&bf_head,
+- &txq->txq_fifo_pending,
+- &bf->bf_lastbf->list);
+- ath_tx_txqaddbuf(sc, txq, &bf_head);
+- } else if (sc->sc_flags & SC_OP_TXAGGR)
+- ath_txq_schedule(sc, txq);
+- }
++ if (!list_empty(&txq->txq_fifo_pending)) {
++ INIT_LIST_HEAD(&bf_head);
++ bf = list_first_entry(&txq->txq_fifo_pending,
++ struct ath_buf, list);
++ list_cut_position(&bf_head,
++ &txq->txq_fifo_pending,
++ &bf->bf_lastbf->list);
++ ath_tx_txqaddbuf(sc, txq, &bf_head);
++ } else if (sc->sc_flags & SC_OP_TXAGGR)
++ ath_txq_schedule(sc, txq);
++
+ spin_unlock_bh(&txq->axq_lock);
+ }
}
+--- a/net/mac80211/chan.c
++++ b/net/mac80211/chan.c
+@@ -77,6 +77,9 @@ bool ieee80211_set_channel_type(struct i
+ switch (tmp->vif.bss_conf.channel_type) {
+ case NL80211_CHAN_NO_HT:
+ case NL80211_CHAN_HT20:
++ if (superchan > tmp->vif.bss_conf.channel_type)
++ break;
++
+ superchan = tmp->vif.bss_conf.channel_type;
+ break;
+ case NL80211_CHAN_HT40PLUS:
+--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+@@ -88,66 +88,6 @@ static void ar9003_hw_init_mode_regs(str
+ ar9485_1_1_pcie_phy_clkreq_disable_L1,
+ ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
+ 2);
+- } else if (AR_SREV_9485(ah)) {
+- /* mac */
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+- ar9485_1_0_mac_core,
+- ARRAY_SIZE(ar9485_1_0_mac_core), 2);
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar9485_1_0_mac_postamble,
+- ARRAY_SIZE(ar9485_1_0_mac_postamble), 5);
+-
+- /* bb */
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_0,
+- ARRAY_SIZE(ar9485_1_0), 2);
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar9485_1_0_baseband_core,
+- ARRAY_SIZE(ar9485_1_0_baseband_core), 2);
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar9485_1_0_baseband_postamble,
+- ARRAY_SIZE(ar9485_1_0_baseband_postamble), 5);
+-
+- /* radio */
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar9485_1_0_radio_core,
+- ARRAY_SIZE(ar9485_1_0_radio_core), 2);
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+- ar9485_1_0_radio_postamble,
+- ARRAY_SIZE(ar9485_1_0_radio_postamble), 2);
+-
+- /* soc */
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar9485_1_0_soc_preamble,
+- ARRAY_SIZE(ar9485_1_0_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
+-
+- /* rx/tx gain */
+- INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9485Common_rx_gain_1_0,
+- ARRAY_SIZE(ar9485Common_rx_gain_1_0), 2);
+- INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9485Modes_lowest_ob_db_tx_gain_1_0,
+- ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
+- 5);
+-
+- /* Load PCIE SERDES settings from INI */
+-
+- /* Awake Setting */
+-
+- INIT_INI_ARRAY(&ah->iniPcieSerdes,
+- ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
+- ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
+- 2);
+-
+- /* Sleep Setting */
+-
+- INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+- ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
+- ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
+- 2);
+ } else {
+ /* mac */
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+@@ -228,11 +168,6 @@ static void ar9003_tx_gain_table_apply(s
+ ar9485_modes_lowest_ob_db_tx_gain_1_1,
+ ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
+ 5);
+- else if (AR_SREV_9485(ah))
+- INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9485Modes_lowest_ob_db_tx_gain_1_0,
+- ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
+- 5);
+ else
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+ ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
+@@ -245,11 +180,6 @@ static void ar9003_tx_gain_table_apply(s
+ ar9485Modes_high_ob_db_tx_gain_1_1,
+ ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
+ 5);
+- else if (AR_SREV_9485(ah))
+- INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9485Modes_high_ob_db_tx_gain_1_0,
+- ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_0),
+- 5);
+ else
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+ ar9300Modes_high_ob_db_tx_gain_table_2p2,
+@@ -262,11 +192,6 @@ static void ar9003_tx_gain_table_apply(s
+ ar9485Modes_low_ob_db_tx_gain_1_1,
+ ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
+ 5);
+- else if (AR_SREV_9485(ah))
+- INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9485Modes_low_ob_db_tx_gain_1_0,
+- ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_0),
+- 5);
+ else
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+ ar9300Modes_low_ob_db_tx_gain_table_2p2,
+@@ -279,11 +204,6 @@ static void ar9003_tx_gain_table_apply(s
+ ar9485Modes_high_power_tx_gain_1_1,
+ ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
+ 5);
+- else if (AR_SREV_9485(ah))
+- INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9485Modes_high_power_tx_gain_1_0,
+- ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_0),
+- 5);
+ else
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+ ar9300Modes_high_power_tx_gain_table_2p2,
+@@ -303,11 +223,6 @@ static void ar9003_rx_gain_table_apply(s
+ ar9485_common_rx_gain_1_1,
+ ARRAY_SIZE(ar9485_common_rx_gain_1_1),
+ 2);
+- else if (AR_SREV_9485(ah))
+- INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9485Common_rx_gain_1_0,
+- ARRAY_SIZE(ar9485Common_rx_gain_1_0),
+- 2);
+ else
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+ ar9300Common_rx_gain_table_2p2,
+@@ -320,11 +235,6 @@ static void ar9003_rx_gain_table_apply(s
+ ar9485Common_wo_xlna_rx_gain_1_1,
+ ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
+ 2);
+- else if (AR_SREV_9485(ah))
+- INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9485Common_wo_xlna_rx_gain_1_0,
+- ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_0),
+- 2);
+ else
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+ ar9300Common_wo_xlna_rx_gain_table_2p2,
+--- a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
++++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
+@@ -17,931 +17,6 @@
+ #ifndef INITVALS_9485_H
+ #define INITVALS_9485_H
+-static const u32 ar9485Common_1_0[][2] = {
+- /* Addr allmodes */
+- {0x00007010, 0x00000022},
+- {0x00007020, 0x00000000},
+- {0x00007034, 0x00000002},
+- {0x00007038, 0x000004c2},
+-};
+-
+-static const u32 ar9485_1_0_mac_postamble[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
+- {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
+- {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
+- {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
+- {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
+- {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
+- {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
+- {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
+-};
+-
+-static const u32 ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
+- /* Addr allmodes */
+- {0x00018c00, 0x10212e5e},
+- {0x00018c04, 0x000801d8},
+- {0x00018c08, 0x0000580c},
+-};
+-
+-static const u32 ar9485Common_wo_xlna_rx_gain_1_0[][2] = {
+- /* Addr allmodes */
+- {0x0000a000, 0x00010000},
+- {0x0000a004, 0x00030002},
+- {0x0000a008, 0x00050004},
+- {0x0000a00c, 0x00810080},
+- {0x0000a010, 0x01800082},
+- {0x0000a014, 0x01820181},
+- {0x0000a018, 0x01840183},
+- {0x0000a01c, 0x01880185},
+- {0x0000a020, 0x018a0189},
+- {0x0000a024, 0x02850284},
+- {0x0000a028, 0x02890288},
+- {0x0000a02c, 0x03850384},
+- {0x0000a030, 0x03890388},
+- {0x0000a034, 0x038b038a},
+- {0x0000a038, 0x038d038c},
+- {0x0000a03c, 0x03910390},
+- {0x0000a040, 0x03930392},
+- {0x0000a044, 0x03950394},
+- {0x0000a048, 0x00000396},
+- {0x0000a04c, 0x00000000},
+- {0x0000a050, 0x00000000},
+- {0x0000a054, 0x00000000},
+- {0x0000a058, 0x00000000},
+- {0x0000a05c, 0x00000000},
+- {0x0000a060, 0x00000000},
+- {0x0000a064, 0x00000000},
+- {0x0000a068, 0x00000000},
+- {0x0000a06c, 0x00000000},
+- {0x0000a070, 0x00000000},
+- {0x0000a074, 0x00000000},
+- {0x0000a078, 0x00000000},
+- {0x0000a07c, 0x00000000},
+- {0x0000a080, 0x28282828},
+- {0x0000a084, 0x28282828},
+- {0x0000a088, 0x28282828},
+- {0x0000a08c, 0x28282828},
+- {0x0000a090, 0x28282828},
+- {0x0000a094, 0x21212128},
+- {0x0000a098, 0x171c1c1c},
+- {0x0000a09c, 0x02020212},
+- {0x0000a0a0, 0x00000202},
+- {0x0000a0a4, 0x00000000},
+- {0x0000a0a8, 0x00000000},
+- {0x0000a0ac, 0x00000000},
+- {0x0000a0b0, 0x00000000},
+- {0x0000a0b4, 0x00000000},
+- {0x0000a0b8, 0x00000000},
+- {0x0000a0bc, 0x00000000},
+- {0x0000a0c0, 0x001f0000},
+- {0x0000a0c4, 0x111f1100},
+- {0x0000a0c8, 0x111d111e},
+- {0x0000a0cc, 0x111b111c},
+- {0x0000a0d0, 0x22032204},
+- {0x0000a0d4, 0x22012202},
+- {0x0000a0d8, 0x221f2200},
+- {0x0000a0dc, 0x221d221e},
+- {0x0000a0e0, 0x33013302},
+- {0x0000a0e4, 0x331f3300},
+- {0x0000a0e8, 0x4402331e},
+- {0x0000a0ec, 0x44004401},
+- {0x0000a0f0, 0x441e441f},
+- {0x0000a0f4, 0x55015502},
+- {0x0000a0f8, 0x551f5500},
+- {0x0000a0fc, 0x6602551e},
+- {0x0000a100, 0x66006601},
+- {0x0000a104, 0x661e661f},
+- {0x0000a108, 0x7703661d},
+- {0x0000a10c, 0x77017702},
+- {0x0000a110, 0x00007700},
+- {0x0000a114, 0x00000000},
+- {0x0000a118, 0x00000000},
+- {0x0000a11c, 0x00000000},
+- {0x0000a120, 0x00000000},
+- {0x0000a124, 0x00000000},
+- {0x0000a128, 0x00000000},
+- {0x0000a12c, 0x00000000},
+- {0x0000a130, 0x00000000},
+- {0x0000a134, 0x00000000},
+- {0x0000a138, 0x00000000},
+- {0x0000a13c, 0x00000000},
+- {0x0000a140, 0x001f0000},
+- {0x0000a144, 0x111f1100},
+- {0x0000a148, 0x111d111e},
+- {0x0000a14c, 0x111b111c},
+- {0x0000a150, 0x22032204},
+- {0x0000a154, 0x22012202},
+- {0x0000a158, 0x221f2200},
+- {0x0000a15c, 0x221d221e},
+- {0x0000a160, 0x33013302},
+- {0x0000a164, 0x331f3300},
+- {0x0000a168, 0x4402331e},
+- {0x0000a16c, 0x44004401},
+- {0x0000a170, 0x441e441f},
+- {0x0000a174, 0x55015502},
+- {0x0000a178, 0x551f5500},
+- {0x0000a17c, 0x6602551e},
+- {0x0000a180, 0x66006601},
+- {0x0000a184, 0x661e661f},
+- {0x0000a188, 0x7703661d},
+- {0x0000a18c, 0x77017702},
+- {0x0000a190, 0x00007700},
+- {0x0000a194, 0x00000000},
+- {0x0000a198, 0x00000000},
+- {0x0000a19c, 0x00000000},
+- {0x0000a1a0, 0x00000000},
+- {0x0000a1a4, 0x00000000},
+- {0x0000a1a8, 0x00000000},
+- {0x0000a1ac, 0x00000000},
+- {0x0000a1b0, 0x00000000},
+- {0x0000a1b4, 0x00000000},
+- {0x0000a1b8, 0x00000000},
+- {0x0000a1bc, 0x00000000},
+- {0x0000a1c0, 0x00000000},
+- {0x0000a1c4, 0x00000000},
+- {0x0000a1c8, 0x00000000},
+- {0x0000a1cc, 0x00000000},
+- {0x0000a1d0, 0x00000000},
+- {0x0000a1d4, 0x00000000},
+- {0x0000a1d8, 0x00000000},
+- {0x0000a1dc, 0x00000000},
+- {0x0000a1e0, 0x00000000},
+- {0x0000a1e4, 0x00000000},
+- {0x0000a1e8, 0x00000000},
+- {0x0000a1ec, 0x00000000},
+- {0x0000a1f0, 0x00000396},
+- {0x0000a1f4, 0x00000396},
+- {0x0000a1f8, 0x00000396},
+- {0x0000a1fc, 0x00000296},
+-};
+-
+-static const u32 ar9485Modes_high_power_tx_gain_1_0[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+- {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+- {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+- {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+- {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+- {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+- {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+- {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+- {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+- {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+- {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+- {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+- {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+- {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
+- {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
+- {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
+- {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
+- {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
+- {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
+- {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
+- {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
+- {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
+- {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
+- {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
+- {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
+- {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
+- {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
+- {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
+-};
+-
+-static const u32 ar9485_1_0[][2] = {
+- /* Addr allmodes */
+- {0x0000a580, 0x00000000},
+- {0x0000a584, 0x00000000},
+- {0x0000a588, 0x00000000},
+- {0x0000a58c, 0x00000000},
+- {0x0000a590, 0x00000000},
+- {0x0000a594, 0x00000000},
+- {0x0000a598, 0x00000000},
+- {0x0000a59c, 0x00000000},
+- {0x0000a5a0, 0x00000000},
+- {0x0000a5a4, 0x00000000},
+- {0x0000a5a8, 0x00000000},
+- {0x0000a5ac, 0x00000000},
+- {0x0000a5b0, 0x00000000},
+- {0x0000a5b4, 0x00000000},
+- {0x0000a5b8, 0x00000000},
+- {0x0000a5bc, 0x00000000},
+-};
+-
+-static const u32 ar9485_1_0_radio_core[][2] = {
+- /* Addr allmodes */
+- {0x00016000, 0x36db6db6},
+- {0x00016004, 0x6db6db40},
+- {0x00016008, 0x73800000},
+- {0x0001600c, 0x00000000},
+- {0x00016040, 0x7f80fff8},
+- {0x00016048, 0x6c92426e},
+- {0x0001604c, 0x000f0278},
+- {0x00016050, 0x6db6db6c},
+- {0x00016054, 0x6db60000},
+- {0x00016080, 0x00080000},
+- {0x00016084, 0x0e48048c},
+- {0x00016088, 0x14214514},
+- {0x0001608c, 0x119f081e},
+- {0x00016090, 0x24926490},
+- {0x00016098, 0xd28b3330},
+- {0x000160a0, 0xc2108ffe},
+- {0x000160a4, 0x812fc370},
+- {0x000160a8, 0x423c8000},
+- {0x000160b4, 0x92480040},
+- {0x000160c0, 0x006db6db},
+- {0x000160c4, 0x0186db60},
+- {0x000160c8, 0x6db6db6c},
+- {0x000160cc, 0x6de6fbe0},
+- {0x000160d0, 0xf7dfcf3c},
+- {0x00016100, 0x04cb0001},
+- {0x00016104, 0xfff80015},
+- {0x00016108, 0x00080010},
+- {0x00016144, 0x01884080},
+- {0x00016148, 0x00008040},
+- {0x00016180, 0x08453333},
+- {0x00016184, 0x18e82f01},
+- {0x00016188, 0x00000000},
+- {0x0001618c, 0x00000000},
+- {0x00016240, 0x08400000},
+- {0x00016244, 0x1bf90f00},
+- {0x00016248, 0x00000000},
+- {0x0001624c, 0x00000000},
+- {0x00016280, 0x01000015},
+- {0x00016284, 0x00d30000},
+- {0x00016288, 0x00318000},
+- {0x0001628c, 0x50000000},
+- {0x00016290, 0x4b96210f},
+- {0x00016380, 0x00000000},
+- {0x00016384, 0x00000000},
+- {0x00016388, 0x00800700},
+- {0x0001638c, 0x00800700},
+- {0x00016390, 0x00800700},
+- {0x00016394, 0x00000000},
+- {0x00016398, 0x00000000},
+- {0x0001639c, 0x00000000},
+- {0x000163a0, 0x00000001},
+- {0x000163a4, 0x00000001},
+- {0x000163a8, 0x00000000},
+- {0x000163ac, 0x00000000},
+- {0x000163b0, 0x00000000},
+- {0x000163b4, 0x00000000},
+- {0x000163b8, 0x00000000},
+- {0x000163bc, 0x00000000},
+- {0x000163c0, 0x000000a0},
+- {0x000163c4, 0x000c0000},
+- {0x000163c8, 0x14021402},
+- {0x000163cc, 0x00001402},
+- {0x000163d0, 0x00000000},
+- {0x000163d4, 0x00000000},
+- {0x00016c40, 0x1319c178},
+- {0x00016c44, 0x10000000},
+-};
+-
+-static const u32 ar9485Modes_lowest_ob_db_tx_gain_1_0[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+- {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+- {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+- {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+- {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+- {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+- {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+- {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+- {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+- {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+- {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+- {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+- {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+- {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
+- {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
+- {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
+- {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
+- {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
+- {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
+- {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
+- {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
+- {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
+- {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
+- {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
+- {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
+- {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
+- {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
+- {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
+-};
+-
+-static const u32 ar9485_1_0_baseband_core[][2] = {
+- /* Addr allmodes */
+- {0x00009800, 0xafe68e30},
+- {0x00009804, 0xfd14e000},
+- {0x00009808, 0x9c0a8f6b},
+- {0x0000980c, 0x04800000},
+- {0x00009814, 0x9280c00a},
+- {0x00009818, 0x00000000},
+- {0x0000981c, 0x00020028},
+- {0x00009834, 0x5f3ca3de},
+- {0x00009838, 0x0108ecff},
+- {0x0000983c, 0x14750600},
+- {0x00009880, 0x201fff00},
+- {0x00009884, 0x00001042},
+- {0x000098a4, 0x00200400},
+- {0x000098b0, 0x52440bbe},
+- {0x000098bc, 0x00000002},
+- {0x000098d0, 0x004b6a8e},
+- {0x000098d4, 0x00000820},
+- {0x000098dc, 0x00000000},
+- {0x000098f0, 0x00000000},
+- {0x000098f4, 0x00000000},
+- {0x00009c04, 0x00000000},
+- {0x00009c08, 0x03200000},
+- {0x00009c0c, 0x00000000},
+- {0x00009c10, 0x00000000},
+- {0x00009c14, 0x00046384},
+- {0x00009c18, 0x05b6b440},
+- {0x00009c1c, 0x00b6b440},
+- {0x00009d00, 0xc080a333},
+- {0x00009d04, 0x40206c10},
+- {0x00009d08, 0x009c4060},
+- {0x00009d0c, 0x1883800a},
+- {0x00009d10, 0x01834061},
+- {0x00009d14, 0x00c00400},
+- {0x00009d18, 0x00000000},
+- {0x00009d1c, 0x00000000},
+- {0x00009e08, 0x0038233c},
+- {0x00009e24, 0x990bb515},
+- {0x00009e28, 0x0a6f0000},
+- {0x00009e30, 0x06336f77},
+- {0x00009e34, 0x6af6532f},
+- {0x00009e38, 0x0cc80c00},
+- {0x00009e40, 0x0d261820},
+- {0x00009e4c, 0x00001004},
+- {0x00009e50, 0x00ff03f1},
+- {0x00009fc0, 0x80be4788},
+- {0x00009fc4, 0x0001efb5},
+- {0x00009fcc, 0x40000014},
+- {0x0000a20c, 0x00000000},
+- {0x0000a210, 0x00000000},
+- {0x0000a220, 0x00000000},
+- {0x0000a224, 0x00000000},
+- {0x0000a228, 0x10002310},
+- {0x0000a23c, 0x00000000},
+- {0x0000a244, 0x0c000000},
+- {0x0000a2a0, 0x00000001},
+- {0x0000a2c0, 0x00000001},
+- {0x0000a2c8, 0x00000000},
+- {0x0000a2cc, 0x18c43433},
+- {0x0000a2d4, 0x00000000},
+- {0x0000a2dc, 0x00000000},
+- {0x0000a2e0, 0x00000000},
+- {0x0000a2e4, 0x00000000},
+- {0x0000a2e8, 0x00000000},
+- {0x0000a2ec, 0x00000000},
+- {0x0000a2f0, 0x00000000},
+- {0x0000a2f4, 0x00000000},
+- {0x0000a2f8, 0x00000000},
+- {0x0000a344, 0x00000000},
+- {0x0000a34c, 0x00000000},
+- {0x0000a350, 0x0000a000},
+- {0x0000a364, 0x00000000},
+- {0x0000a370, 0x00000000},
+- {0x0000a390, 0x00000001},
+- {0x0000a394, 0x00000444},
+- {0x0000a398, 0x001f0e0f},
+- {0x0000a39c, 0x0075393f},
+- {0x0000a3a0, 0xb79f6427},
+- {0x0000a3a4, 0x00000000},
+- {0x0000a3a8, 0xaaaaaaaa},
+- {0x0000a3ac, 0x3c466478},
+- {0x0000a3c0, 0x20202020},
+- {0x0000a3c4, 0x22222220},
+- {0x0000a3c8, 0x20200020},
+- {0x0000a3cc, 0x20202020},
+- {0x0000a3d0, 0x20202020},
+- {0x0000a3d4, 0x20202020},
+- {0x0000a3d8, 0x20202020},
+- {0x0000a3dc, 0x20202020},
+- {0x0000a3e0, 0x20202020},
+- {0x0000a3e4, 0x20202020},
+- {0x0000a3e8, 0x20202020},
+- {0x0000a3ec, 0x20202020},
+- {0x0000a3f0, 0x00000000},
+- {0x0000a3f4, 0x00000006},
+- {0x0000a3f8, 0x0cdbd380},
+- {0x0000a3fc, 0x000f0f01},
+- {0x0000a400, 0x8fa91f01},
+- {0x0000a404, 0x00000000},
+- {0x0000a408, 0x0e79e5c6},
+- {0x0000a40c, 0x00820820},
+- {0x0000a414, 0x1ce739ce},
+- {0x0000a418, 0x2d0011ce},
+- {0x0000a41c, 0x1ce739ce},
+- {0x0000a420, 0x000001ce},
+- {0x0000a424, 0x1ce739ce},
+- {0x0000a428, 0x000001ce},
+- {0x0000a42c, 0x1ce739ce},
+- {0x0000a430, 0x1ce739ce},
+- {0x0000a434, 0x00000000},
+- {0x0000a438, 0x00001801},
+- {0x0000a43c, 0x00000000},
+- {0x0000a440, 0x00000000},
+- {0x0000a444, 0x00000000},
+- {0x0000a448, 0x04000000},
+- {0x0000a44c, 0x00000001},
+- {0x0000a450, 0x00010000},
+- {0x0000a458, 0x00000000},
+- {0x0000a5c4, 0x3fad9d74},
+- {0x0000a5c8, 0x0048060a},
+- {0x0000a5cc, 0x00000637},
+- {0x0000a760, 0x03020100},
+- {0x0000a764, 0x09080504},
+- {0x0000a768, 0x0d0c0b0a},
+- {0x0000a76c, 0x13121110},
+- {0x0000a770, 0x31301514},
+- {0x0000a774, 0x35343332},
+- {0x0000a778, 0x00000036},
+- {0x0000a780, 0x00000838},
+- {0x0000a7c0, 0x00000000},
+- {0x0000a7c4, 0xfffffffc},
+- {0x0000a7c8, 0x00000000},
+- {0x0000a7cc, 0x00000000},
+- {0x0000a7d0, 0x00000000},
+- {0x0000a7d4, 0x00000004},
+- {0x0000a7dc, 0x00000001},
+-};
+-
+-static const u32 ar9485Modes_high_ob_db_tx_gain_1_0[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+- {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+- {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+- {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+- {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+- {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+- {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+- {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+- {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+- {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+- {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+- {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+- {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+- {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
+- {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
+- {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
+- {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
+- {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
+- {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
+- {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
+- {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
+- {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
+- {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
+- {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
+- {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
+- {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
+- {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
+- {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
+-};
+-
+-static const u32 ar9485Common_rx_gain_1_0[][2] = {
+- /* Addr allmodes */
+- {0x0000a000, 0x00010000},
+- {0x0000a004, 0x00030002},
+- {0x0000a008, 0x00050004},
+- {0x0000a00c, 0x00810080},
+- {0x0000a010, 0x01800082},
+- {0x0000a014, 0x01820181},
+- {0x0000a018, 0x01840183},
+- {0x0000a01c, 0x01880185},
+- {0x0000a020, 0x018a0189},
+- {0x0000a024, 0x02850284},
+- {0x0000a028, 0x02890288},
+- {0x0000a02c, 0x03850384},
+- {0x0000a030, 0x03890388},
+- {0x0000a034, 0x038b038a},
+- {0x0000a038, 0x038d038c},
+- {0x0000a03c, 0x03910390},
+- {0x0000a040, 0x03930392},
+- {0x0000a044, 0x03950394},
+- {0x0000a048, 0x00000396},
+- {0x0000a04c, 0x00000000},
+- {0x0000a050, 0x00000000},
+- {0x0000a054, 0x00000000},
+- {0x0000a058, 0x00000000},
+- {0x0000a05c, 0x00000000},
+- {0x0000a060, 0x00000000},
+- {0x0000a064, 0x00000000},
+- {0x0000a068, 0x00000000},
+- {0x0000a06c, 0x00000000},
+- {0x0000a070, 0x00000000},
+- {0x0000a074, 0x00000000},
+- {0x0000a078, 0x00000000},
+- {0x0000a07c, 0x00000000},
+- {0x0000a080, 0x28282828},
+- {0x0000a084, 0x28282828},
+- {0x0000a088, 0x28282828},
+- {0x0000a08c, 0x28282828},
+- {0x0000a090, 0x28282828},
+- {0x0000a094, 0x21212128},
+- {0x0000a098, 0x171c1c1c},
+- {0x0000a09c, 0x02020212},
+- {0x0000a0a0, 0x00000202},
+- {0x0000a0a4, 0x00000000},
+- {0x0000a0a8, 0x00000000},
+- {0x0000a0ac, 0x00000000},
+- {0x0000a0b0, 0x00000000},
+- {0x0000a0b4, 0x00000000},
+- {0x0000a0b8, 0x00000000},
+- {0x0000a0bc, 0x00000000},
+- {0x0000a0c0, 0x001f0000},
+- {0x0000a0c4, 0x111f1100},
+- {0x0000a0c8, 0x111d111e},
+- {0x0000a0cc, 0x111b111c},
+- {0x0000a0d0, 0x22032204},
+- {0x0000a0d4, 0x22012202},
+- {0x0000a0d8, 0x221f2200},
+- {0x0000a0dc, 0x221d221e},
+- {0x0000a0e0, 0x33013302},
+- {0x0000a0e4, 0x331f3300},
+- {0x0000a0e8, 0x4402331e},
+- {0x0000a0ec, 0x44004401},
+- {0x0000a0f0, 0x441e441f},
+- {0x0000a0f4, 0x55015502},
+- {0x0000a0f8, 0x551f5500},
+- {0x0000a0fc, 0x6602551e},
+- {0x0000a100, 0x66006601},
+- {0x0000a104, 0x661e661f},
+- {0x0000a108, 0x7703661d},
+- {0x0000a10c, 0x77017702},
+- {0x0000a110, 0x00007700},
+- {0x0000a114, 0x00000000},
+- {0x0000a118, 0x00000000},
+- {0x0000a11c, 0x00000000},
+- {0x0000a120, 0x00000000},
+- {0x0000a124, 0x00000000},
+- {0x0000a128, 0x00000000},
+- {0x0000a12c, 0x00000000},
+- {0x0000a130, 0x00000000},
+- {0x0000a134, 0x00000000},
+- {0x0000a138, 0x00000000},
+- {0x0000a13c, 0x00000000},
+- {0x0000a140, 0x001f0000},
+- {0x0000a144, 0x111f1100},
+- {0x0000a148, 0x111d111e},
+- {0x0000a14c, 0x111b111c},
+- {0x0000a150, 0x22032204},
+- {0x0000a154, 0x22012202},
+- {0x0000a158, 0x221f2200},
+- {0x0000a15c, 0x221d221e},
+- {0x0000a160, 0x33013302},
+- {0x0000a164, 0x331f3300},
+- {0x0000a168, 0x4402331e},
+- {0x0000a16c, 0x44004401},
+- {0x0000a170, 0x441e441f},
+- {0x0000a174, 0x55015502},
+- {0x0000a178, 0x551f5500},
+- {0x0000a17c, 0x6602551e},
+- {0x0000a180, 0x66006601},
+- {0x0000a184, 0x661e661f},
+- {0x0000a188, 0x7703661d},
+- {0x0000a18c, 0x77017702},
+- {0x0000a190, 0x00007700},
+- {0x0000a194, 0x00000000},
+- {0x0000a198, 0x00000000},
+- {0x0000a19c, 0x00000000},
+- {0x0000a1a0, 0x00000000},
+- {0x0000a1a4, 0x00000000},
+- {0x0000a1a8, 0x00000000},
+- {0x0000a1ac, 0x00000000},
+- {0x0000a1b0, 0x00000000},
+- {0x0000a1b4, 0x00000000},
+- {0x0000a1b8, 0x00000000},
+- {0x0000a1bc, 0x00000000},
+- {0x0000a1c0, 0x00000000},
+- {0x0000a1c4, 0x00000000},
+- {0x0000a1c8, 0x00000000},
+- {0x0000a1cc, 0x00000000},
+- {0x0000a1d0, 0x00000000},
+- {0x0000a1d4, 0x00000000},
+- {0x0000a1d8, 0x00000000},
+- {0x0000a1dc, 0x00000000},
+- {0x0000a1e0, 0x00000000},
+- {0x0000a1e4, 0x00000000},
+- {0x0000a1e8, 0x00000000},
+- {0x0000a1ec, 0x00000000},
+- {0x0000a1f0, 0x00000396},
+- {0x0000a1f4, 0x00000396},
+- {0x0000a1f8, 0x00000396},
+- {0x0000a1fc, 0x00000296},
+-};
+-
+-static const u32 ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
+- /* Addr allmodes */
+- {0x00018c00, 0x10252e5e},
+- {0x00018c04, 0x000801d8},
+- {0x00018c08, 0x0000580c},
+-};
+-
+-static const u32 ar9485_1_0_pcie_phy_clkreq_enable_L1[][2] = {
+- /* Addr allmodes */
+- {0x00018c00, 0x10253e5e},
+- {0x00018c04, 0x000801d8},
+- {0x00018c08, 0x0000580c},
+-};
+-
+-static const u32 ar9485_1_0_soc_preamble[][2] = {
+- /* Addr allmodes */
+- {0x00004090, 0x00aa10aa},
+- {0x000040a4, 0x00a0c9c9},
+- {0x00007048, 0x00000004},
+-};
+-
+-static const u32 ar9485_fast_clock_1_0_baseband_postamble[][3] = {
+- /* Addr 5G_HT20 5G_HT40 */
+- {0x00009e00, 0x03721821, 0x03721821},
+- {0x0000a230, 0x0000400b, 0x00004016},
+- {0x0000a254, 0x00000898, 0x00001130},
+-};
+-
+-static const u32 ar9485_1_0_baseband_postamble[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
+- {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
+- {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
+- {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
+- {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
+- {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
+- {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
+- {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
+- {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
+- {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
+- {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec80d2e, 0x7ec80d2e},
+- {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
+- {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
+- {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
+- {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
+- {0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222},
+- {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
+- {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
+- {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
+- {0x0000a204, 0x01303fc0, 0x01303fc4, 0x01303fc4, 0x01303fc0},
+- {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
+- {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b},
+- {0x0000a234, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff},
+- {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
+- {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
+- {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
+- {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
+- {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
+- {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
+- {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
+- {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
+- {0x0000a284, 0x00000000, 0x00000000, 0x000002a0, 0x000002a0},
+- {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
+- {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982},
+- {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
+- {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+- {0x0000be04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
+- {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+-};
+-
+-static const u32 ar9485Modes_low_ob_db_tx_gain_1_0[][5] = {
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+- {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+- {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+- {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+- {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+- {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+- {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+- {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+- {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+- {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+- {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+- {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+- {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+- {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
+- {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
+- {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
+- {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
+- {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
+- {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
+- {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
+- {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
+- {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
+- {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
+- {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
+- {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
+- {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
+- {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
+- {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+- {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
+-};
+-
+-static const u32 ar9485_1_0_pcie_phy_clkreq_disable_L1[][2] = {
+- /* Addr allmodes */
+- {0x00018c00, 0x10213e5e},
+- {0x00018c04, 0x000801d8},
+- {0x00018c08, 0x0000580c},
+-};
+-
+-static const u32 ar9485_1_0_radio_postamble[][2] = {
+- /* Addr allmodes */
+- {0x0001609c, 0x0b283f31},
+- {0x000160ac, 0x24611800},
+- {0x000160b0, 0x03284f3e},
+- {0x0001610c, 0x00170000},
+- {0x00016140, 0x10804008},
+-};
+-
+-static const u32 ar9485_1_0_mac_core[][2] = {
+- /* Addr allmodes */
+- {0x00000008, 0x00000000},
+- {0x00000030, 0x00020085},
+- {0x00000034, 0x00000005},
+- {0x00000040, 0x00000000},
+- {0x00000044, 0x00000000},
+- {0x00000048, 0x00000008},
+- {0x0000004c, 0x00000010},
+- {0x00000050, 0x00000000},
+- {0x00001040, 0x002ffc0f},
+- {0x00001044, 0x002ffc0f},
+- {0x00001048, 0x002ffc0f},
+- {0x0000104c, 0x002ffc0f},
+- {0x00001050, 0x002ffc0f},
+- {0x00001054, 0x002ffc0f},
+- {0x00001058, 0x002ffc0f},
+- {0x0000105c, 0x002ffc0f},
+- {0x00001060, 0x002ffc0f},
+- {0x00001064, 0x002ffc0f},
+- {0x000010f0, 0x00000100},
+- {0x00001270, 0x00000000},
+- {0x000012b0, 0x00000000},
+- {0x000012f0, 0x00000000},
+- {0x0000143c, 0x00000000},
+- {0x0000147c, 0x00000000},
+- {0x00008000, 0x00000000},
+- {0x00008004, 0x00000000},
+- {0x00008008, 0x00000000},
+- {0x0000800c, 0x00000000},
+- {0x00008018, 0x00000000},
+- {0x00008020, 0x00000000},
+- {0x00008038, 0x00000000},
+- {0x0000803c, 0x00000000},
+- {0x00008040, 0x00000000},
+- {0x00008044, 0x00000000},
+- {0x00008048, 0x00000000},
+- {0x0000804c, 0xffffffff},
+- {0x00008054, 0x00000000},
+- {0x00008058, 0x00000000},
+- {0x0000805c, 0x000fc78f},
+- {0x00008060, 0x0000000f},
+- {0x00008064, 0x00000000},
+- {0x00008070, 0x00000310},
+- {0x00008074, 0x00000020},
+- {0x00008078, 0x00000000},
+- {0x0000809c, 0x0000000f},
+- {0x000080a0, 0x00000000},
+- {0x000080a4, 0x02ff0000},
+- {0x000080a8, 0x0e070605},
+- {0x000080ac, 0x0000000d},
+- {0x000080b0, 0x00000000},
+- {0x000080b4, 0x00000000},
+- {0x000080b8, 0x00000000},
+- {0x000080bc, 0x00000000},
+- {0x000080c0, 0x2a800000},
+- {0x000080c4, 0x06900168},
+- {0x000080c8, 0x13881c20},
+- {0x000080cc, 0x01f40000},
+- {0x000080d0, 0x00252500},
+- {0x000080d4, 0x00a00000},
+- {0x000080d8, 0x00400000},
+- {0x000080dc, 0x00000000},
+- {0x000080e0, 0xffffffff},
+- {0x000080e4, 0x0000ffff},
+- {0x000080e8, 0x3f3f3f3f},
+- {0x000080ec, 0x00000000},
+- {0x000080f0, 0x00000000},
+- {0x000080f4, 0x00000000},
+- {0x000080fc, 0x00020000},
+- {0x00008100, 0x00000000},
+- {0x00008108, 0x00000052},
+- {0x0000810c, 0x00000000},
+- {0x00008110, 0x00000000},
+- {0x00008114, 0x000007ff},
+- {0x00008118, 0x000000aa},
+- {0x0000811c, 0x00003210},
+- {0x00008124, 0x00000000},
+- {0x00008128, 0x00000000},
+- {0x0000812c, 0x00000000},
+- {0x00008130, 0x00000000},
+- {0x00008134, 0x00000000},
+- {0x00008138, 0x00000000},
+- {0x0000813c, 0x0000ffff},
+- {0x00008144, 0xffffffff},
+- {0x00008168, 0x00000000},
+- {0x0000816c, 0x00000000},
+- {0x00008170, 0x18486200},
+- {0x00008174, 0x33332210},
+- {0x00008178, 0x00000000},
+- {0x0000817c, 0x00020000},
+- {0x000081c0, 0x00000000},
+- {0x000081c4, 0x33332210},
+- {0x000081c8, 0x00000000},
+- {0x000081cc, 0x00000000},
+- {0x000081d4, 0x00000000},
+- {0x000081ec, 0x00000000},
+- {0x000081f0, 0x00000000},
+- {0x000081f4, 0x00000000},
+- {0x000081f8, 0x00000000},
+- {0x000081fc, 0x00000000},
+- {0x00008240, 0x00100000},
+- {0x00008244, 0x0010f400},
+- {0x00008248, 0x00000800},
+- {0x0000824c, 0x0001e800},
+- {0x00008250, 0x00000000},
+- {0x00008254, 0x00000000},
+- {0x00008258, 0x00000000},
+- {0x0000825c, 0x40000000},
+- {0x00008260, 0x00080922},
+- {0x00008264, 0x9ca00010},
+- {0x00008268, 0xffffffff},
+- {0x0000826c, 0x0000ffff},
+- {0x00008270, 0x00000000},
+- {0x00008274, 0x40000000},
+- {0x00008278, 0x003e4180},
+- {0x0000827c, 0x00000004},
+- {0x00008284, 0x0000002c},
+- {0x00008288, 0x0000002c},
+- {0x0000828c, 0x000000ff},
+- {0x00008294, 0x00000000},
+- {0x00008298, 0x00000000},
+- {0x0000829c, 0x00000000},
+- {0x00008300, 0x00000140},
+- {0x00008314, 0x00000000},
+- {0x0000831c, 0x0000010d},
+- {0x00008328, 0x00000000},
+- {0x0000832c, 0x00000007},
+- {0x00008330, 0x00000302},
+- {0x00008334, 0x00000700},
+- {0x00008338, 0x00ff0000},
+- {0x0000833c, 0x02400000},
+- {0x00008340, 0x000107ff},
+- {0x00008344, 0xa248105b},
+- {0x00008348, 0x008f0000},
+- {0x0000835c, 0x00000000},
+- {0x00008360, 0xffffffff},
+- {0x00008364, 0xffffffff},
+- {0x00008368, 0x00000000},
+- {0x00008370, 0x00000000},
+- {0x00008374, 0x000000ff},
+- {0x00008378, 0x00000000},
+- {0x0000837c, 0x00000000},
+- {0x00008380, 0xffffffff},
+- {0x00008384, 0xffffffff},
+- {0x00008390, 0xffffffff},
+- {0x00008394, 0xffffffff},
+- {0x00008398, 0x00000000},
+- {0x0000839c, 0x00000000},
+- {0x000083a0, 0x00000000},
+- {0x000083a4, 0x0000fa14},
+- {0x000083a8, 0x000f0c00},
+- {0x000083ac, 0x33332210},
+- {0x000083b0, 0x33332210},
+- {0x000083b4, 0x33332210},
+- {0x000083b8, 0x33332210},
+- {0x000083bc, 0x00000000},
+- {0x000083c0, 0x00000000},
+- {0x000083c4, 0x00000000},
+- {0x000083c8, 0x00000000},
+- {0x000083cc, 0x00000200},
+- {0x000083d0, 0x000301ff},
+-};
+-
+ static const u32 ar9485_1_1_mac_core[][2] = {
+ /* Addr allmodes */
+ {0x00000008, 0x00000000},
projects / openwrt / svn-archive / archive.git / blobdiff