fixes ifxmips pci support and adds GENERIC_GPIO

[openwrt/svn-archive/archive.git] / target / linux / ifxmips / files / arch / mips / ifxmips / pci.c

diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/pci.c b/target/linux/ifxmips/files/arch/mips/ifxmips/pci.c
index d8dac469f27011a017cb549e7a1c780c1a34f731..ae5807677c506d6f204da153f5f3eef1350fc4d5 100644 (file)
--- a/target/linux/ifxmips/files/arch/mips/ifxmips/pci.c
+++ b/target/linux/ifxmips/files/arch/mips/ifxmips/pci.c
@@ -21,7 +21,7 @@
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
 
-//#define CONFIG_IFXMIPS_PCI_HW_SWAP 1
+#define CONFIG_IFXMIPS_PCI_HW_SWAP 1
 
 static int ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
 static int ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
@@ -80,12 +80,12 @@ ifxmips_pci_config_access(unsigned char access_type,
        if (access_type == PCI_ACCESS_WRITE)
        {
 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
-               writel(swab32(*data), ((u32*)cfg_base));
+               ifxmips_w32(swab32(*data), ((u32*)cfg_base));
 #else
-               writel(*data, ((u32*)cfg_base));
+               ifxmips_w32(*data, ((u32*)cfg_base));
 #endif
        } else {
-               *data = readl(((u32*)(cfg_base)));
+               *data = ifxmips_r32(((u32*)(cfg_base)));
 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
                *data = swab32(*data);
 #endif
@@ -94,12 +94,12 @@ ifxmips_pci_config_access(unsigned char access_type,
 
        /* clean possible Master abort */
        cfg_base = (ifxmips_pci_mapped_cfg | (0x0 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
-       temp = readl(((u32*)(cfg_base)));
+       temp = ifxmips_r32(((u32*)(cfg_base)));
 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
        temp = swab32 (temp);
 #endif
        cfg_base = (ifxmips_pci_mapped_cfg | (0x68 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
-       writel(temp, ((u32*)cfg_base));
+       ifxmips_w32(temp, ((u32*)cfg_base));
 
        local_irq_restore(flags);
 
@@ -164,8 +164,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev){
                        break;
                case 1:
                        //falling edge level triggered:0x4, low level:0xc, rising edge:0x2
-                       writel(readl(IFXMIPS_EBU_PCC_CON) | 0xc, IFXMIPS_EBU_PCC_CON);
-                       writel(readl(IFXMIPS_EBU_PCC_IEN) | 0x10, IFXMIPS_EBU_PCC_IEN);
+                       ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_CON) | 0xc, IFXMIPS_EBU_PCC_CON);
+                       ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_IEN) | 0x10, IFXMIPS_EBU_PCC_IEN);
                        break;
                case 2:
                case 3:
@@ -183,44 +183,44 @@ static void __init ifxmips_pci_startup (void){
        /*initialize the first PCI device--ifxmips itself */
        u32 temp_buffer;
        /*TODO: trigger reset */
-       writel(readl(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
-       writel(readl(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
        /* PCIS of IF_CLK of CGU   : 1 =>PCI Clock output
           0 =>clock input
           PADsel of PCI_CR of CGU : 1 =>From CGU
           : 0 =>From pad
         */
-       writel(readl(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
-       writel((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
+       ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
 
        /* prepare GPIO */
        /* PCI_RST: P1.5 ALT 01 */
        //pliu20060613: start
-       writel(readl(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
-       writel(readl(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD);
-       writel(readl(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR);
-       writel(readl(IFXMIPS_GPIO_P1_ALTSEL1) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1);
-       writel(readl(IFXMIPS_GPIO_P1_ALTSEL0) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0);
        //pliu20060613: end
        /* PCI_REQ1: P1.13 ALT 01 */
        /* PCI_GNT1: P1.14 ALT 01 */
-       writel(readl(IFXMIPS_GPIO_P1_DIR) & ~0x2000, IFXMIPS_GPIO_P1_DIR);
-       writel(readl(IFXMIPS_GPIO_P1_DIR) | 0x4000, IFXMIPS_GPIO_P1_DIR);
-       writel(readl(IFXMIPS_GPIO_P1_ALTSEL1) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1);
-       writel(readl(IFXMIPS_GPIO_P1_ALTSEL0) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) & ~0x2000, IFXMIPS_GPIO_P1_DIR);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | 0x4000, IFXMIPS_GPIO_P1_DIR);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0);
        /* PCI_REQ2: P1.15 ALT 10 */
        /* PCI_GNT2: P1.7 ALT 10 */
 
 
        /* enable auto-switching between PCI and EBU */
-       writel(0xa, PCI_CR_CLK_CTRL);
+       ifxmips_w32(0xa, PCI_CR_CLK_CTRL);
        /* busy, i.e. configuration is not done, PCI access has to be retried */
-       writel(readl(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
+       ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
        wmb ();
        /* BUS Master/IO/MEM access */
-       writel(readl(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
+       ifxmips_w32(ifxmips_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
 
-       temp_buffer = readl(PCI_CR_PC_ARB);
+       temp_buffer = ifxmips_r32(PCI_CR_PC_ARB);
        /* enable external 2 PCI masters */
        temp_buffer &= (~(0xf << 16));
        /* enable internal arbiter */
@@ -233,51 +233,51 @@ static void __init ifxmips_pci_startup (void){
 
        /* enable all external masters request */
        temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
-       writel(temp_buffer, PCI_CR_PC_ARB);
+       ifxmips_w32(temp_buffer, PCI_CR_PC_ARB);
 
        wmb ();
 
        /* FPI ==> PCI MEM address mapping */
        /* base: 0xb8000000 == > 0x18000000 */
        /* size: 8x4M = 32M */
-       writel(0x18000000, PCI_CR_FCI_ADDR_MAP0);
-       writel(0x18400000, PCI_CR_FCI_ADDR_MAP1);
-       writel(0x18800000, PCI_CR_FCI_ADDR_MAP2);
-       writel(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
-       writel(0x19000000, PCI_CR_FCI_ADDR_MAP4);
-       writel(0x19400000, PCI_CR_FCI_ADDR_MAP5);
-       writel(0x19800000, PCI_CR_FCI_ADDR_MAP6);
-       writel(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
+       ifxmips_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
+       ifxmips_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
+       ifxmips_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
+       ifxmips_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
+       ifxmips_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
+       ifxmips_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
+       ifxmips_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
+       ifxmips_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
 
        /* FPI ==> PCI IO address mapping */
        /* base: 0xbAE00000 == > 0xbAE00000 */
        /* size: 2M */
-       writel(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
+       ifxmips_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
 
        /* PCI ==> FPI address mapping */
        /* base: 0x0 ==> 0x0 */
        /* size: 32M */
        /* BAR1 32M map to SDR address */
-       writel(0x0e000008, PCI_CR_BAR11MASK);
-       writel(0, PCI_CR_PCI_ADDR_MAP11);
-       writel(0, PCI_CS_BASE_ADDR1);
+       ifxmips_w32(0x0e000008, PCI_CR_BAR11MASK);
+       ifxmips_w32(0, PCI_CR_PCI_ADDR_MAP11);
+       ifxmips_w32(0, PCI_CS_BASE_ADDR1);
 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
        /* both TX and RX endian swap are enabled */
-       writel(readl(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
+       ifxmips_w32(ifxmips_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
        wmb ();
 #endif
        /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
-       writel(readl(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
-       writel(readl(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
+       ifxmips_w32(ifxmips_r32(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
+       ifxmips_w32(ifxmips_r32(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
        /*use 8 dw burse length */
-       writel(0x303, PCI_CR_FCI_BURST_LENGTH);
+       ifxmips_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
 
-       writel(readl(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
+       ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
        wmb();
-       writel(readl(IFXMIPS_GPIO_P1_OUT) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT);
        wmb();
        mdelay (1);
-       writel(readl(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
 }
 
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){