ipq806x: Add support for IPQ806x chip family

[openwrt/svn-archive/archive.git] / target / linux / ipq806x / patches / 0088-soc-qcom-Add-device-tree-binding-for-GSBI.patch

diff --git a/target/linux/ipq806x/patches/0088-soc-qcom-Add-device-tree-binding-for-GSBI.patch b/target/linux/ipq806x/patches/0088-soc-qcom-Add-device-tree-binding-for-GSBI.patch
new file mode 100644 (file)
index 0000000..39762c1
--- /dev/null
+++ b/target/linux/ipq806x/patches/0088-soc-qcom-Add-device-tree-binding-for-GSBI.patch
@@ -0,0 +1,135 @@
+From 5a58dbf4d82c29f7e6d89abc3520bed1aa2af05c Mon Sep 17 00:00:00 2001
+From: Andy Gross <agross@codeaurora.org>
+Date: Thu, 24 Apr 2014 11:31:20 -0500
+Subject: [PATCH 088/182] soc: qcom: Add device tree binding for GSBI
+
+Add device tree binding support for the QCOM GSBI driver.
+
+Signed-off-by: Andy Gross <agross@codeaurora.org>
+Signed-off-by: Kumar Gala <galak@codeaurora.org>
+---
+ .../devicetree/bindings/soc/qcom/qcom,gsbi.txt     |   78 ++++++++++++++++++++
+ include/dt-bindings/soc/qcom,gsbi.h                |   26 +++++++
+ 2 files changed, 104 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
+ create mode 100644 include/dt-bindings/soc/qcom,gsbi.h
+
+diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
+new file mode 100644
+index 0000000..4ce24d4
+--- /dev/null
++++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
+@@ -0,0 +1,78 @@
++QCOM GSBI (General Serial Bus Interface) Driver
++
++The GSBI controller is modeled as a node with zero or more child nodes, each
++representing a serial sub-node device that is mux'd as part of the GSBI
++configuration settings.  The mode setting will govern the input/output mode of
++the 4 GSBI IOs.
++
++Required properties:
++- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
++- reg: Address range for GSBI registers
++- clocks: required clock
++- clock-names: must contain "iface" entry
++- qcom,mode : indicates MUX value for configuration of the serial interface.
++  Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
++
++Optional properties:
++- qcom,crci : indicates CRCI MUX value for QUP CRCI ports.  Please reference
++  dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
++
++Required properties if child node exists:
++- #address-cells: Must be 1
++- #size-cells: Must be 1
++- ranges: Must be present
++
++Properties for children:
++
++A GSBI controller node can contain 0 or more child nodes representing serial
++devices.  These serial devices can be a QCOM UART, I2C controller, spi
++controller, or some combination of aforementioned devices.
++
++See the following for child node definitions:
++Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
++Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
++Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
++
++Example for APQ8064:
++
++#include <dt-bindings/soc/qcom,gsbi.h>
++
++      gsbi4@16300000 {
++              compatible = "qcom,gsbi-v1.0.0";
++              reg = <0x16300000 0x100>;
++              clocks = <&gcc GSBI4_H_CLK>;
++              clock-names = "iface";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              ranges;
++              qcom,mode = <GSBI_PROT_I2C_UART>;
++              qcom,crci = <GSBI_CRCI_QUP>;
++
++              /* child nodes go under here */
++
++              i2c_qup4: i2c@16380000 {
++                      compatible = "qcom,i2c-qup-v1.1.1";
++                      reg = <0x16380000 0x1000>;
++                      interrupts = <0 153 0>;
++
++                      clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
++                      clock-names = "core", "iface";
++
++                      clock-frequency = <200000>;
++
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++
++               };
++
++              uart4:  serial@16340000 {
++                      compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
++                      reg = <0x16340000 0x1000>,
++                              <0x16300000 0x1000>;
++                      interrupts = <0 152 0x0>;
++                      clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
++                      clock-names = "core", "iface";
++                      status = "ok";
++              };
++      };
++
+diff --git a/include/dt-bindings/soc/qcom,gsbi.h b/include/dt-bindings/soc/qcom,gsbi.h
+new file mode 100644
+index 0000000..7ac4292
+--- /dev/null
++++ b/include/dt-bindings/soc/qcom,gsbi.h
+@@ -0,0 +1,26 @@
++/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++#ifndef __DT_BINDINGS_QCOM_GSBI_H
++#define __DT_BINDINGS_QCOM_GSBI_H
++
++#define GSBI_PROT_IDLE                0
++#define GSBI_PROT_I2C_UIM     1
++#define GSBI_PROT_I2C         2
++#define GSBI_PROT_SPI         3
++#define GSBI_PROT_UART_W_FC   4
++#define GSBI_PROT_UIM         5
++#define GSBI_PROT_I2C_UART    6
++
++#define GSBI_CRCI_QUP         0
++#define GSBI_CRCI_UART                1
++
++#endif
+-- 
+1.7.10.4
+