X-Git-Url: http://git.openwrt.org/?p=openwrt%2Fsvn-archive%2Farchive.git;a=blobdiff_plain;f=package%2Fuboot-lantiq%2Ffiles%2Fboard%2Finfineon%2Feasy50812%2Far9_ddr196_settings.h;fp=package%2Fuboot-lantiq%2Ffiles%2Fboard%2Finfineon%2Feasy50812%2Far9_ddr196_settings.h;h=45daa188d3a6a8f84dc995bb89a3d7d8baacc781;hp=b00177e0a5dd70fdd30a7459c1461295caf5e79a;hb=681302b9de7e901026b001a6fe03b90f6e0d6fb2;hpb=b1a0e919c37045abe4c248643da833133e90d806

diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h
index b00177e0a5..45daa188d3 100644
--- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h
+++ b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h
@@ -1,51 +1,51 @@
-/* Settings for Denali DDR SDRAM controller */
-/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
-
-#define MC_DC0_VALUE	0x1B1B
-#define MC_DC1_VALUE	0x0
-#define MC_DC2_VALUE	0x0
-#define MC_DC3_VALUE	0x0
-#define MC_DC4_VALUE	0x0
-#define MC_DC5_VALUE	0x200
-#define MC_DC6_VALUE	0x306
-#define MC_DC7_VALUE	0x303
-#define MC_DC8_VALUE	0x102
-#define MC_DC9_VALUE	0x80B
-#define MC_DC10_VALUE	0x203
-#define MC_DC11_VALUE	0xD02
-#define MC_DC12_VALUE	0x1C8
-#define MC_DC13_VALUE	0x1
-#define MC_DC14_VALUE	0x0
-#define MC_DC15_VALUE	0x144  /* WDQS tuning for clk_wr*/
-#define MC_DC16_VALUE	0xC800
-#define MC_DC17_VALUE	0xF
-#define MC_DC18_VALUE	0x301
-#define MC_DC19_VALUE	0x200
-#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
-#define MC_DC21_VALUE	0x1200
-#define MC_DC22_VALUE	0x1212
-#define MC_DC23_VALUE	0x0
-#define MC_DC24_VALUE	0x66   /* WDQS Tuning for DQS */
-#define MC_DC25_VALUE	0x0
-#define MC_DC26_VALUE	0x0
-#define MC_DC27_VALUE	0x0
-#define MC_DC28_VALUE	0x5FB
-#define MC_DC29_VALUE	0x35DF
-#define MC_DC30_VALUE	0x99E9
-#define MC_DC31_VALUE	0x0
-#define MC_DC32_VALUE	0x0
-#define MC_DC33_VALUE	0x0
-#define MC_DC34_VALUE	0x0
-#define MC_DC35_VALUE	0x0
-#define MC_DC36_VALUE	0x0
-#define MC_DC37_VALUE	0x0
-#define MC_DC38_VALUE	0x0
-#define MC_DC39_VALUE	0x0
-#define MC_DC40_VALUE	0x0
-#define MC_DC41_VALUE	0x0
-#define MC_DC42_VALUE	0x0
-#define MC_DC43_VALUE	0x0
-#define MC_DC44_VALUE	0x0
-#define MC_DC45_VALUE	0x600
-//#define MC_DC45_VALUE	0x400
-#define MC_DC46_VALUE	0x0
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
+
+#define MC_DC0_VALUE	0x1B1B
+#define MC_DC1_VALUE	0x0
+#define MC_DC2_VALUE	0x0
+#define MC_DC3_VALUE	0x0
+#define MC_DC4_VALUE	0x0
+#define MC_DC5_VALUE	0x200
+#define MC_DC6_VALUE	0x306
+#define MC_DC7_VALUE	0x303
+#define MC_DC8_VALUE	0x102
+#define MC_DC9_VALUE	0x80B
+#define MC_DC10_VALUE	0x203
+#define MC_DC11_VALUE	0xD02
+#define MC_DC12_VALUE	0x1C8
+#define MC_DC13_VALUE	0x1
+#define MC_DC14_VALUE	0x0
+#define MC_DC15_VALUE	0x144  /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE	0xC800
+#define MC_DC17_VALUE	0xF
+#define MC_DC18_VALUE	0x301
+#define MC_DC19_VALUE	0x200
+#define MC_DC20_VALUE	0xA04  /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE	0x1200
+#define MC_DC22_VALUE	0x1212
+#define MC_DC23_VALUE	0x0
+#define MC_DC24_VALUE	0x66   /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE	0x0
+#define MC_DC26_VALUE	0x0
+#define MC_DC27_VALUE	0x0
+#define MC_DC28_VALUE	0x5FB
+#define MC_DC29_VALUE	0x35DF
+#define MC_DC30_VALUE	0x99E9
+#define MC_DC31_VALUE	0x0
+#define MC_DC32_VALUE	0x0
+#define MC_DC33_VALUE	0x0
+#define MC_DC34_VALUE	0x0
+#define MC_DC35_VALUE	0x0
+#define MC_DC36_VALUE	0x0
+#define MC_DC37_VALUE	0x0
+#define MC_DC38_VALUE	0x0
+#define MC_DC39_VALUE	0x0
+#define MC_DC40_VALUE	0x0
+#define MC_DC41_VALUE	0x0
+#define MC_DC42_VALUE	0x0
+#define MC_DC43_VALUE	0x0
+#define MC_DC44_VALUE	0x0
+#define MC_DC45_VALUE	0x600
+//#define MC_DC45_VALUE	0x400
+#define MC_DC46_VALUE	0x0