X-Git-Url: http://git.openwrt.org/?p=openwrt%2Fsvn-archive%2Farchive.git;a=blobdiff_plain;f=target%2Flinux%2Fifxmips%2Ffiles%2Finclude%2Fasm-mips%2Fifxmips%2Fifxmips.h;fp=target%2Flinux%2Fifxmips%2Ffiles%2Finclude%2Fasm-mips%2Fifxmips%2Fifxmips.h;h=8389611895fa8adf013716c2f7274fa109d78aaf;hp=1c6c614329ae2d5fa91b97f5117211a6137c3ab2;hb=81dea43759c54dafd4f8905d469f3bf53081bcec;hpb=9e2a23f16cc478ba97cf75c8c6b059daf96651f7

diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
index 1c6c614329..8389611895 100644
--- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
@@ -15,7 +15,6 @@
  *
  *   Copyright (C) 2005 infineon
  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
- *
  */
 #ifndef _IFXMIPS_H__
 #define _IFXMIPS_H__
@@ -71,8 +70,41 @@
 #define ASCOPT_STOPB			0x8
 #define ASCOPT_PARODD			0x0
 #define ASCOPT_CREAD			0x20
-#define ASCFSTAT_TXFFLMASK		0x3F00
-#define ASCFSTAT_TXFFLOFF		8
+#define TXFIFO_FL				1
+#define RXFIFO_FL				1
+#define TXFIFO_FULL				16
+#define ASCCLC_RMCMASK			0x0000FF00
+#define ASCCLC_RMCOFFSET		8
+#define ASCCON_M_8ASYNC			0x0
+#define ASCCON_M_7ASYNC			0x2
+#define ASCCON_ODD				0x00000020
+#define ASCCON_STP				0x00000080
+#define ASCCON_BRS				0x00000100
+#define ASCCON_FDE				0x00000200
+#define ASCCON_R				0x00008000
+#define ASCCON_FEN				0x00020000
+#define ASCCON_ROEN				0x00080000
+#define ASCCON_TOEN				0x00100000
+#define ASCSTATE_PE				0x00010000
+#define ASCSTATE_FE				0x00020000
+#define ASCSTATE_ROE			0x00080000
+#define ASCSTATE_ANY			(ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
+#define ASCWHBSTATE_CLRREN		0x00000001
+#define ASCWHBSTATE_SETREN		0x00000002
+#define ASCWHBSTATE_CLRPE		0x00000004
+#define ASCWHBSTATE_CLRFE		0x00000008
+#define ASCWHBSTATE_CLRROE		0x00000020
+#define ASCTXFCON_TXFEN			0x0001
+#define ASCTXFCON_TXFFLU		0x0002
+#define ASCTXFCON_TXFITLMASK    0x3F00
+#define ASCTXFCON_TXFITLOFF     8
+#define ASCRXFCON_RXFEN         0x0001
+#define ASCRXFCON_RXFFLU        0x0002
+#define ASCRXFCON_RXFITLMASK    0x3F00
+#define ASCRXFCON_RXFITLOFF     8
+#define ASCFSTAT_RXFFLMASK      0x003F
+#define ASCFSTAT_TXFFLMASK      0x3F00
+#define ASCFSTAT_TXFFLOFF       8
 
 
 
@@ -334,7 +366,7 @@
 #define IFXMIPS_SSC_IRN			((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))
 #define IFXMIPS_SSC_SFCON		((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060))
 #define IFXMIPS_SSC_WHBGPOSTAT	((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
-#define IFXMIPS_SSC_STATE    	((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
+#define IFXMIPS_SSC_STATE		((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
 #define IFXMIPS_SSC_WHBSTATE	((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
 #define IFXMIPS_SSC_FSTAT		((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038))
 #define IFXMIPS_SSC_ID			((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008))
@@ -472,7 +504,7 @@
 #define IFXMIPS_MPS_AD0ENR		((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
 #define IFXMIPS_MPS_AD1ENR		((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
 
-#define IFXMIPS_MPS_CHIPID_VERSION_GET(value)	 (((value) >> 28) & ((1 << 4) - 1))
+#define IFXMIPS_MPS_CHIPID_VERSION_GET(value)	(((value) >> 28) & ((1 << 4) - 1))
 #define IFXMIPS_MPS_CHIPID_VERSION_SET(value)	(((( 1 << 4) - 1) & (value)) << 28)
 #define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value)	(((value) >> 12) & ((1 << 16) - 1))
 #define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value)	(((( 1 << 16) - 1) & (value)) << 12)