From 3ecb3bfa809c6128c03862348e3bd550a1d4d099 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Wed, 18 Nov 2015 00:57:22 +0000 Subject: [PATCH] gcc: fix internal compiler error on MIPS with MIPS16 enabled (triggered by libpcap) Signed-off-by: Felix Fietkau SVN-Revision: 47494 --- .../5.2.0/040-fix-mips-ICE-PR-68400.patch | 23 +++++++++++++++++++ .../5.2.0/930-fix-mips-noexecstack.patch | 2 +- 2 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 toolchain/gcc/patches/5.2.0/040-fix-mips-ICE-PR-68400.patch diff --git a/toolchain/gcc/patches/5.2.0/040-fix-mips-ICE-PR-68400.patch b/toolchain/gcc/patches/5.2.0/040-fix-mips-ICE-PR-68400.patch new file mode 100644 index 0000000000..e88af34032 --- /dev/null +++ b/toolchain/gcc/patches/5.2.0/040-fix-mips-ICE-PR-68400.patch @@ -0,0 +1,23 @@ +--- a/gcc/config/mips/mips.c ++++ b/gcc/config/mips/mips.c +@@ -8001,9 +8001,17 @@ mask_low_and_shift_p (machine_mode mode, + bool + and_operands_ok (machine_mode mode, rtx op1, rtx op2) + { +- return (memory_operand (op1, mode) +- ? and_load_operand (op2, mode) +- : and_reg_operand (op2, mode)); ++ if (!memory_operand (op1, mode)) ++ return and_reg_operand (op2, mode); ++ ++ if (!and_load_operand (op2, mode)) ++ return false; ++ ++ if (!TARGET_MIPS16 || si_mask_operand(op2, mode)) ++ return true; ++ ++ op1 = XEXP (op1, 0); ++ return !(REG_P (op1) && REGNO (op1) == STACK_POINTER_REGNUM); + } + + /* The canonical form of a mask-low-and-shift-left operation is diff --git a/toolchain/gcc/patches/5.2.0/930-fix-mips-noexecstack.patch b/toolchain/gcc/patches/5.2.0/930-fix-mips-noexecstack.patch index 4bb126eb99..c05844d2e4 100644 --- a/toolchain/gcc/patches/5.2.0/930-fix-mips-noexecstack.patch +++ b/toolchain/gcc/patches/5.2.0/930-fix-mips-noexecstack.patch @@ -48,7 +48,7 @@ sellcey@mips.com --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c -@@ -19621,6 +19621,9 @@ mips_lra_p (void) +@@ -19629,6 +19629,9 @@ mips_lra_p (void) #undef TARGET_LRA_P #define TARGET_LRA_P mips_lra_p -- 2.30.2