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authorDaniel Golle2025-11-18 11:17:39 +0000
committerDaniel Golle2025-11-18 11:28:37 +0000
commit1c3b32c45a25a6b80b9b1541a5ec4ce082939e5e (patch)
tree1d6bda1a507ee6f2120b5c53021e542ec1f02122
parent93cfbc7d1ff1a3f5dff9297d912c9b35556fd97d (diff)
downloadopenwrt-1c3b32c45a25a6b80b9b1541a5ec4ce082939e5e.tar.gz
mediatek: fix uart clocks in MT7987 infracfg clock driver
MediaTek has applied a fix for the MT7987 infracfg clock driver in their SDK, pick it. Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/fe98d04c6036a5e142f02021145e528216a8d831/master/files/target/linux/mediatek/patches-6.12/999-clk-01-clk-mediatek-fix-mt7987-infracfg-clk-driver.patch Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-rw-r--r--target/linux/mediatek/patches-6.12/361-clk-mediatek-add-mt7987-clock-drivers-support.patch5
1 files changed, 1 insertions, 4 deletions
diff --git a/target/linux/mediatek/patches-6.12/361-clk-mediatek-add-mt7987-clock-drivers-support.patch b/target/linux/mediatek/patches-6.12/361-clk-mediatek-add-mt7987-clock-drivers-support.patch
index 577b2b7dfc..249e239086 100644
--- a/target/linux/mediatek/patches-6.12/361-clk-mediatek-add-mt7987-clock-drivers-support.patch
+++ b/target/linux/mediatek/patches-6.12/361-clk-mediatek-add-mt7987-clock-drivers-support.patch
@@ -273,7 +273,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+MODULE_LICENSE("GPL");
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7987-infracfg.c
-@@ -0,0 +1,328 @@
+@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 MediaTek Inc.
@@ -301,15 +301,12 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+static DEFINE_SPINLOCK(mt7987_clk_lock);
+
+static const char *const infra_mux_uart0_parents[] = { "csw_infra_f26m_sel",
-+ "infra_hf_66m_uart0_pck",
+ "uart_sel" };
+
+static const char *const infra_mux_uart1_parents[] = { "csw_infra_f26m_sel",
-+ "infra_hf_66m_uart1_pck",
+ "uart_sel" };
+
+static const char *const infra_mux_uart2_parents[] = { "csw_infra_f26m_sel",
-+ "infra_hf_66m_uart1_pck",
+ "uart_sel" };
+
+static const char *const infra_mux_spi0_parents[] = {