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| author | Christian Marangi | 2025-10-28 12:17:38 +0000 |
|---|---|---|
| committer | Christian Marangi | 2025-10-28 12:17:38 +0000 |
| commit | 3ba92e0e3268c07859859968368602d2dc758148 (patch) | |
| tree | 9bb3498bd6afaaf5ac4d9c375831285ea88080d9 | |
| parent | 3db72b71d1929e27068bf927e8e09200e190464d (diff) | |
| download | openwrt-3ba92e0e3268c07859859968368602d2dc758148.tar.gz | |
airoha: an7581: correctly attach the USB2 PHY for 3rd PCIe line
The 3rd PCIe line use the USB2 serdes for PCIe operation. Correctly set
it to the DT node so that the mode can be correctly set in the PHY
driver.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
| -rw-r--r-- | target/linux/airoha/dts/an7581.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/airoha/dts/an7581.dtsi b/target/linux/airoha/dts/an7581.dtsi index 367779e544..32bc6b5df7 100644 --- a/target/linux/airoha/dts/an7581.dtsi +++ b/target/linux/airoha/dts/an7581.dtsi @@ -780,7 +780,7 @@ clocks = <&scuclk EN7523_CLK_PCIE>; clock-names = "sys-ck"; - phys = <&pciephy>; + phys = <&usb1_phy PHY_TYPE_USB3>; phy-names = "pcie-phy"; ranges = <0x02000000 0 0x28000000 0x0 0x28000000 0 0x4000000>; |