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| author | Lech Perczak | 2023-12-11 23:22:04 +0000 |
|---|---|---|
| committer | Hauke Mehrtens | 2024-01-05 22:32:59 +0000 |
| commit | 4e1bf2a50c43b48f9e47c7cdff87a0dcfa998bb8 (patch) | |
| tree | 3763516d45169bce6e594ae66415db84cee9f46b | |
| parent | 88501f82f52a3186f676e8f49a4a92d90642f936 (diff) | |
| download | openwrt-4e1bf2a50c43b48f9e47c7cdff87a0dcfa998bb8.tar.gz | |
ramips: dts: rt3050: reset FE and ESW cores together
Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.
This is behaviour of downstream driver as well, however I
haven't observed bug reports about this SoC in the wild, so this
commit's purpose is to align this chip with all other SoC's - MT7620
were already using this arrangement.
Fixes: 60fadae62b64 ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit c5a399f372535886582f89f3da624ae7465c8ff4)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
| -rw-r--r-- | target/linux/ramips/dts/rt3050.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/ramips/dts/rt3050.dtsi b/target/linux/ramips/dts/rt3050.dtsi index 492474fdc4..6077dd5008 100644 --- a/target/linux/ramips/dts/rt3050.dtsi +++ b/target/linux/ramips/dts/rt3050.dtsi @@ -306,8 +306,8 @@ compatible = "ralink,rt3050-eth"; reg = <0x10100000 0x10000>; - resets = <&rstctrl 21>; - reset-names = "fe"; + resets = <&rstctrl 21>, <&rstctrl 23>; + reset-names = "fe", "esw"; interrupt-parent = <&cpuintc>; interrupts = <5>; @@ -319,8 +319,8 @@ compatible = "ralink,rt3050-esw"; reg = <0x10110000 0x8000>; - resets = <&rstctrl 23 &rstctrl 24>; - reset-names = "esw", "ephy"; + resets = <&rstctrl 24>; + reset-names = "ephy"; interrupt-parent = <&intc>; interrupts = <17>; |