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authorDavid Bauer2024-09-27 17:10:40 +0000
committerDavid Bauer2024-09-27 17:10:40 +0000
commit533235182141392d8031a6d2edb9d7edc91bfd5a (patch)
tree93181649a5ee29d056e6562591370aa0c553f8bd
parent6e561fe0a191230779e05f6ccf6a51f282197d9a (diff)
downloadopenwrt-533235182141392d8031a6d2edb9d7edc91bfd5a.tar.gz
ipq40xx: fix AP-303H PSE GPIO pin
The GPIO chip is at a different start index compared to OpenWrt master. Signed-off-by: David Bauer <mail@david-bauer.net>
-rw-r--r--target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches b/target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches
index f57d4c5888..fcc6e8e745 100644
--- a/target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches
+++ b/target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches
@@ -7,7 +7,7 @@ board=$(board_name)
case "$board" in
aruba,ap-303h)
- ucidef_add_gpio_switch "poe_passtrough" "POE passtrough disable" "546" "1"
+ ucidef_add_gpio_switch "poe_passtrough" "POE passtrough disable" "446" "1"
;;
cellc,rtl30vw)
ucidef_add_gpio_switch "w_disable" "W_DISABLE mPCIE pin" "398" "1"