diff options
| author | Markus Stockhausen | 2026-01-26 16:32:05 +0000 |
|---|---|---|
| committer | Robert Marko | 2026-01-27 08:19:54 +0000 |
| commit | 81f6eca5ec7aeb4ce51e208c6add4508bc7eff2e (patch) | |
| tree | 45968a81620a7cb4194b5f03b30288babef2fefa | |
| parent | ebf169afa63d8c4323da872335d0b17882456baa (diff) | |
| download | openwrt-81f6eca5ec7aeb4ce51e208c6add4508bc7eff2e.tar.gz | |
realtek: pcs: rtl930x: enhance symbol error reset
The symbol error reset function misses the default sequence. E.g. kernel
spits the message "rtpcs_930x_sds_sym_err_reset unsupported phy mode" when
working on 2500base-x.
Align the function with the SDK by
- adding QSGMII mode
- adding the "all other modes" switch
- working with "channels" to make clearer what happens
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21718
Signed-off-by: Robert Marko <robimarko@gmail.com>
| -rw-r--r-- | target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c | 35 |
1 files changed, 24 insertions, 11 deletions
diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c index 6def54b3fd..7356555778 100644 --- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c @@ -2186,29 +2186,42 @@ static void rtpcs_930x_sds_do_rx_calibration(struct rtpcs_serdes *sds, static int rtpcs_930x_sds_sym_err_reset(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode) { - switch (hw_mode) { - case RTPCS_SDS_MODE_XSGMII: - break; + int channel, channels; + switch (hw_mode) { case RTPCS_SDS_MODE_10GBASER: + case RTPCS_SDS_MODE_USXGMII_10GSXGMII: /* Read twice to clear */ rtpcs_sds_read(sds, 5, 1); rtpcs_sds_read(sds, 5, 1); - break; + return 0; - case RTPCS_SDS_MODE_1000BASEX: - case RTPCS_SDS_MODE_SGMII: - case RTPCS_SDS_MODE_USXGMII_10GQXGMII: - rtpcs_sds_write_bits(sds, 0x1, 24, 2, 0, 0); - rtpcs_sds_write_bits(sds, 0x1, 3, 15, 8, 0); - rtpcs_sds_write_bits(sds, 0x1, 2, 15, 0, 0); + case RTPCS_SDS_MODE_XSGMII: + case RTPCS_SDS_MODE_QSGMII: + channels = 4; break; default: - pr_info("%s unsupported phy mode\n", __func__); + channels = 1; + } + + /* TODO: Below reset sequence must run with new xsg_write() function */ + if (hw_mode == RTPCS_SDS_MODE_XSGMII) { + pr_info("%s unsupported PHY-mode\n", __func__); return -1; } + for (channel = 0; channel < channels; channel++) { + rtpcs_sds_write_bits(sds, 0x1, 24, 2, 0, channel); + rtpcs_sds_write_bits(sds, 0x1, 3, 15, 8, 0); + rtpcs_sds_write_bits(sds, 0x1, 2, 15, 0, 0); + } + + if (channels > 1) { + rtpcs_sds_write_bits(sds, 0x1, 0, 15, 0, 0); + rtpcs_sds_write_bits(sds, 0x1, 1, 15, 8, 0); + } + return 0; } |