arch/arm/dts/fsl-ls1028a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP ls1028a SOC common device tree source
   4  *
   5  * Copyright 2019 NXP
   6  *
   7  */
   8
   9 / {
  10         compatible = "fsl,ls1028a";
  11         interrupt-parent = <&gic>;
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         sysclk: sysclk {
  16                 compatible = "fixed-clock";
  17                 #clock-cells = <0>;
  18                 clock-frequency = <100000000>;
  19                 clock-output-names = "sysclk";
  20         };
  21
  22         clockgen: clocking@1300000 {
  23                 compatible = "fsl,ls1028a-clockgen";
  24                 reg = <0x0 0x1300000 0x0 0xa0000>;
  25                 #clock-cells = <2>;
  26                 clocks = <&sysclk>;
  27         };
  28
  29         memory@01080000 {
  30                 device_type = "memory";
  31                 reg = <0x00000000 0x01080000 0 0x80000000>;
  32                       /* DRAM space - 1, size : 2 GB DRAM */
  33         };
  34
  35         gic: interrupt-controller@6000000 {
  36                 compatible = "arm,gic-v3";
  37                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  38                           <0x0 0x06040000 0 0x40000>;
  39                 #interrupt-cells = <3>;
  40                 interrupt-controller;
  41                 interrupts = <1 9 0x4>;
  42         };
  43
  44         timer {
  45                 compatible = "arm,armv8-timer";
  46                 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  47                              <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
  48                              <1 11 0x8>, /* Virtual PPI, active-low */
  49                              <1 10 0x8>; /* Hypervisor PPI, active-low */
  50         };
  51
  52         fspi: flexspi@20C0000 {
  53                 compatible = "nxp,dn-fspi";
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56                 reg = <0x0 0x20C0000 0x0 0x10000>,
  57                         <0x0 0x20000000 0x0 0x10000000>; /*64MB flash*/
  58                 reg-names = "FSPI", "FSPI-memory";
  59                 num-cs = <1>;
  60                 status = "disabled";
  61         };
  62
  63         serial0: serial@21c0500 {
  64                 device_type = "serial";
  65                 compatible = "fsl,ns16550", "ns16550a";
  66                 reg = <0x0 0x21c0500 0x0 0x100>;
  67                 interrupts = <0 32 0x1>; /* edge triggered */
  68                 status = "disabled";
  69         };
  70
  71         serial1: serial@21c0600 {
  72                 device_type = "serial";
  73                 compatible = "fsl,ns16550", "ns16550a";
  74                 reg = <0x0 0x21c0600 0x0 0x100>;
  75                 interrupts = <0 32 0x1>; /* edge triggered */
  76                 status = "disabled";
  77         };
  78
  79         pcie@3400000 {
  80                compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
  81                reg = <0x00 0x03400000 0x0 0x80000
  82                        0x00 0x03480000 0x0 0x40000   /* lut registers */
  83                        0x00 0x034c0000 0x0 0x40000  /* pf controls registers */
  84                        0x80 0x00000000 0x0 0x20000>; /* configuration space */
  85                reg-names = "dbi", "lut", "ctrl", "config";
  86                #address-cells = <3>;
  87                #size-cells = <2>;
  88                device_type = "pci";
  89                num-lanes = <4>;
  90                bus-range = <0x0 0xff>;
  91                ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000   /* downstream I/O */
  92                        0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  93         };
  94
  95         pcie@3500000 {
  96                compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
  97                reg = <0x00 0x03500000 0x0 0x80000
  98                        0x00 0x03580000 0x0 0x40000   /* lut registers */
  99                        0x00 0x035c0000 0x0 0x40000  /* pf controls registers */
 100                        0x88 0x00000000 0x0 0x20000>; /* configuration space */
 101                reg-names = "dbi", "lut", "ctrl", "config";
 102                #address-cells = <3>;
 103                #size-cells = <2>;
 104                device_type = "pci";
 105                num-lanes = <4>;
 106                bus-range = <0x0 0xff>;
 107                ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000   /* downstream I/O */
 108                        0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 109         };
 110
 111         i2c0: i2c@2000000 {
 112                 compatible = "fsl,vf610-i2c";
 113                 #address-cells = <1>;
 114                 #size-cells = <0>;
 115                 reg = <0x0 0x2000000 0x0 0x10000>;
 116                 interrupts = <0 34 0x4>;
 117                 clock-names = "i2c";
 118                 clocks = <&clockgen 4 0>;
 119                 status = "disabled";
 120         };
 121
 122         i2c1: i2c@2010000 {
 123                 compatible = "fsl,vf610-i2c";
 124                 #address-cells = <1>;
 125                 #size-cells = <0>;
 126                 reg = <0x0 0x2010000 0x0 0x10000>;
 127                 interrupts = <0 34 0x4>;
 128                 clock-names = "i2c";
 129                 clocks = <&clockgen 4 0>;
 130                 status = "disabled";
 131         };
 132
 133         i2c2: i2c@2020000 {
 134                 compatible = "fsl,vf610-i2c";
 135                 #address-cells = <1>;
 136                 #size-cells = <0>;
 137                 reg = <0x0 0x2020000 0x0 0x10000>;
 138                 interrupts = <0 35 0x4>;
 139                 clock-names = "i2c";
 140                 clocks = <&clockgen 4 0>;
 141                 status = "disabled";
 142         };
 143
 144         i2c3: i2c@2030000 {
 145                 compatible = "fsl,vf610-i2c";
 146                 #address-cells = <1>;
 147                 #size-cells = <0>;
 148                 reg = <0x0 0x2030000 0x0 0x10000>;
 149                 interrupts = <0 35 0x4>;
 150                 clock-names = "i2c";
 151                 clocks = <&clockgen 4 0>;
 152                 status = "disabled";
 153         };
 154
 155         i2c4: i2c@2040000 {
 156                 compatible = "fsl,vf610-i2c";
 157                 #address-cells = <1>;
 158                 #size-cells = <0>;
 159                 reg = <0x0 0x2040000 0x0 0x10000>;
 160                 interrupts = <0 74 0x4>;
 161                 clock-names = "i2c";
 162                 clocks = <&clockgen 4 0>;
 163                 status = "disabled";
 164         };
 165
 166         i2c5: i2c@2050000 {
 167                 compatible = "fsl,vf610-i2c";
 168                 #address-cells = <1>;
 169                 #size-cells = <0>;
 170                 reg = <0x0 0x2050000 0x0 0x10000>;
 171                 interrupts = <0 74 0x4>;
 172                 clock-names = "i2c";
 173                 clocks = <&clockgen 4 0>;
 174                 status = "disabled";
 175         };
 176
 177         i2c6: i2c@2060000 {
 178                 compatible = "fsl,vf610-i2c";
 179                 #address-cells = <1>;
 180                 #size-cells = <0>;
 181                 reg = <0x0 0x2060000 0x0 0x10000>;
 182                 interrupts = <0 75 0x4>;
 183                 clock-names = "i2c";
 184                 clocks = <&clockgen 4 0>;
 185                 status = "disabled";
 186         };
 187
 188         i2c7: i2c@2070000 {
 189                 compatible = "fsl,vf610-i2c";
 190                 #address-cells = <1>;
 191                 #size-cells = <0>;
 192                 reg = <0x0 0x2070000 0x0 0x10000>;
 193                 interrupts = <0 75 0x4>;
 194                 clock-names = "i2c";
 195                 clocks = <&clockgen 4 0>;
 196                 status = "disabled";
 197         };
 198
 199         usb1: usb3@3100000 {
 200                 compatible = "fsl,layerscape-dwc3";
 201                 reg = <0x0 0x3100000 0x0 0x10000>;
 202                 interrupts = <0 80 0x4>;
 203                 dr_mode = "host";
 204                 status = "disabled";
 205         };
 206
 207         usb2: usb3@3110000 {
 208                 compatible = "fsl,layerscape-dwc3";
 209                 reg = <0x0 0x3110000 0x0 0x10000>;
 210                 interrupts = <0 81 0x4>;
 211                 dr_mode = "host";
 212                 status = "disabled";
 213         };
 214
 215         dspi0: dspi@2100000 {
 216                 compatible = "fsl,vf610-dspi";
 217                 #address-cells = <1>;
 218                 #size-cells = <0>;
 219                 reg = <0x0 0x2100000 0x0 0x10000>;
 220                 interrupts = <0 26 0x4>;
 221                 clock-names = "dspi";
 222                 clocks = <&clockgen 4 0>;
 223                 num-cs = <5>;
 224                 litte-endian;
 225                 status = "disabled";
 226         };
 227
 228         dspi1: dspi@2110000 {
 229                 compatible = "fsl,vf610-dspi";
 230                 #address-cells = <1>;
 231                 #size-cells = <0>;
 232                 reg = <0x0 0x2110000 0x0 0x10000>;
 233                 interrupts = <0 26 0x4>;
 234                 clock-names = "dspi";
 235                 clocks = <&clockgen 4 0>;
 236                 num-cs = <5>;
 237                 little-endian;
 238                 status = "disabled";
 239         };
 240
 241         dspi2: dspi@2120000 {
 242                 compatible = "fsl,vf610-dspi";
 243                 #address-cells = <1>;
 244                 #size-cells = <0>;
 245                 reg = <0x0 0x2120000 0x0 0x10000>;
 246                 interrupts = <0 26 0x4>;
 247                 clock-names = "dspi";
 248                 clocks = <&clockgen 4 0>;
 249                 num-cs = <5>;
 250                 little-endian;
 251                 status = "disabled";
 252         };
 253
 254         esdhc0: esdhc@2140000 {
 255                 compatible = "fsl,esdhc";
 256                 reg = <0x0 0x2140000 0x0 0x10000>;
 257                 interrupts = <0 28 0x4>;
 258                 big-endian;
 259                 bus-width = <4>;
 260                 status = "disabled";
 261         };
 262
 263         esdhc1: esdhc@2150000 {
 264                 compatible = "fsl,esdhc";
 265                 reg = <0x0 0x2150000 0x0 0x10000>;
 266                 interrupts = <0 63 0x4>;
 267                 big-endian;
 268                 non-removable;
 269                 bus-width = <4>;
 270                 status = "disabled";
 271         };
 272
 273         sata: sata@3200000 {
 274                 compatible = "fsl,ls1028a-ahci";
 275                 reg = <0x0 0x3200000 0x0 0x10000        /* ccsr sata base */
 276                        0x7 0x100520  0x0 0x4>;          /* ecc sata addr*/
 277                 reg-names = "sata-base", "ecc-addr";
 278                 interrupts = <0 133 4>;
 279                 status = "disabled";
 280         };
 281
 282         cluster1_core0_watchdog: wdt@c000000 {
 283                 compatible = "arm,sp805-wdt";
 284                 reg = <0x0 0xc000000 0x0 0x1000>;
 285         };
 286 };